Abstract
In one embodiment, the optoelectronic semiconductor chip comprises a semiconductor layer sequence with an active zone for generating radiation with a wavelength of maximum intensity L. A mirror comprises a cover layer. The cover layer is made of a material transparent to the radiation and has an optical thickness between 0.5 L and 3 L inclusive. The cover layer is followed in a direction away from the semiconductor layer sequence by between inclusive two and inclusive ten intermediate layers of the mirror. The intermediate layers alternately have high and low refractive indices. An optical thickness of at least one of the intermediate layers is not equal to L/4. The intermediate layers are followed in the direction away from the semiconductor layer sequence by at least one metal layer of the mirror as a reflection layer.
Claims
1. An optoelectronic semiconductor chip comprising: a semiconductor layer sequence having an active zone for generating radiation with a wavelength of maximum intensity L; and a mirror for the radiation on a rear side opposite a light extraction side, wherein the mirror comprises a cover layer located closest to the semiconductor layer sequence, the cover layer is formed with a material transparent to the radiation and has an optical thickness between 0.5 L and 3 L inclusive, the cover layer is followed by between inclusive 2 and inclusive 10 intermediate layers in a direction away from the semiconductor layer sequence, the intermediate layers have alternately high and low refractive indices for the radiation and are each made of a material transparent to the radiation, and the intermediate layers are followed in the direction away from the semiconductor layer sequence by at least one metal layer as a reflection layer.
2. The optoelectronic semiconductor chip according to claim 1, wherein a thickness of at least one of the intermediate layers is unequal to L/4.
3. The optoelectronic semiconductor chip according to claim 1, wherein at least 50% of the intermediate layers have an optical thickness of L/3, with a tolerance of not more than L/15.
4. The optoelectronic semiconductor chip according to claim 1, wherein the mirror comprises three or four of the intermediate layers and the intermediate layers each have an optical thickness of L/3, with a tolerance of at most L/20.
5. The optoelectronic semiconductor chip according to claim 1, wherein the mirror comprises at most two intermediate layers with an optical thickness of (L/4+N/2)+−L/20, wherein N is a natural number greater than or equal to zero.
6. The optoelectronic semiconductor chip according to claim 1, wherein the cover layer has an optical thickness between 1.1 L and 1.6 L, inclusive.
7. The optoelectronic semiconductor chip according to claim 1, wherein high refractive index layers each have an optical thickness between 0.3 L and 0.4 L, inclusive and an intermediate low refractive index layer has an optical thickness between 0.26 L and 0.35 L, inclusive.
8. The optoelectronic semiconductor chip according to claim 1, wherein an optical thickness of at least three of the intermediate layers increases in a direction away from the cover layer, and wherein a difference in optical thickness between adjacent ones of the intermediate layers is between 0.03 L and 0.15 L, inclusive.
9. The optoelectronic semiconductor chip according to claim 1, wherein the cover layer is of SiO.sub.2 and/or the intermediate layers are alternately of Nb.sub.2O5 and SiO.sub.2, and wherein the metal layer is of gold, silver or aluminum.
10. The optoelectronic semiconductor chip according to claim 1, wherein the semiconductor layer sequence is based on AlInGaAs or on InGaAlP and/or the wavelength of maximum intensity L is between 570 nm and 950 nm inclusive.
11. The optoelectronic semiconductor chip according to claim 1, wherein the mirror is located on a p-doped side of the semiconductor layer sequence, wherein a plurality of electrical connections extend through the mirror for electrically contacting the p-doped side.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0076] In the following, an optoelectronic semiconductor chip described here is explained in more detail with reference to the drawing using exemplary embodiments. Identical reference signs indicate identical elements in the individual figures. However, no scale references are shown; individual elements may be shown in exaggerated size for better understanding.
[0077] In the figures:
[0078] FIG. 1 shows a schematic sectional view of an example of an optoelectronic semiconductor chip described here,
[0079] FIGS. 2 and 3 schematic sectional views of modifications of semiconductor chips,
[0080] FIGS. 4 and 5 schematic sectional views of exemplary embodiments of optoelectronic semiconductor chips described here,
[0081] FIG. 6 shows schematically a reflectivity as a function of the thickness of the cover layer of a modification and an exemplary embodiment of an optoelectronic semiconductor chip described here,
[0082] FIG. 7 shows a schematic comparison of the reflectivity of different semiconductor chips,
[0083] FIGS. 8A to 8G shows schematic representations of reflectivity for modification and exemplary embodiments of semiconductor chips versus angle of incidence and versus wavelength,
[0084] FIG. 9 shows a schematic representation of a dependence of the radiated intensity on a radiation angle, and
[0085] FIGS. 10 to 14 schematic sectional views of exemplary embodiments of optoelectronic semiconductor chips described here.
DETAILED DESCRIPTION
[0086] FIG. 1 shows an exemplary embodiments of a semiconductor chip 1. The semiconductor chip 1 comprises a semiconductor layer sequence 2, in which an active zone 23 is located between a p-doped side 21 and an n-doped side 22.
[0087] A mirror 3 is located directly on the semiconductor layer sequence 2 to reflect radiation generated during operation in the active zone 23, which has a wavelength of maximum intensity L. The mirror 3 comprises a cover layer 31 which is directly adjacent to the semiconductor layer sequence 2. The cover layer 31 may be the thickest layer of the mirror 3. The cover layer 31 has a relatively low refractive index.
[0088] In a direction away from the cover layer 31, the mirror 3 comprises several intermediate layers 32, 33. The intermediate layers 32, 33, preferably together with the cover layer 31, have alternating high and low refractive indices.
[0089] The intermediate layers 32, 33 are directly followed in the direction away from the semiconductor layer sequence 2 by a metal layer 39 as a reflection layer. The metal layer 39 is preferably made of gold, alternatively of silver.
[0090] The intermediate layers 32, 33 of mirror 3 form a modified Bragg mirror, in particular together with the cover layer 31. All intermediate layers 32, 33 have an optical thickness different from L/4, unlike in a classic Bragg mirror. This allows a reduced spectral dependence and angle dependence of the reflection behavior to be achieved.
[0091] The cover layer 31, for example, is made of silicon dioxide with a thickness of 520 nm. The first intermediate layers 32 are for example made of Nb.sub.2O.sub.5 with a thickness of 95 nm. The second intermediate layer 33 is for example made of silicon dioxide with a thickness of 120 nm. At a wavelength of maximum intensity L of 616 nm and at room temperature, the corresponding optical thicknesses of these layers are 0.35 and 0.28 L, as shown in FIG. 1. The cover layer 31 has an optical thickness of 1.23 L. Depending on the wavelength of maximum intensity L, the geometric thicknesses must be adjusted.
[0092] The values given for the optical thicknesses are preferably valid with a tolerance of 0.03 L or 0.02 L maximum, in particular with regard to the intermediate layers 32, 33.
[0093] FIG. 2 shows a modification 1′ of a semiconductor chip. As in a classical Bragg mirror, the intermediate layers 32, 33 are each L/4 layers, i.e., layers with an optical thickness of L/4. 10.5 pairs of layers, i.e., 21 layers, are present, for example. The first intermediate layers 32 are for example made of silicon dioxide and the second intermediate layers 33 of Nb.sub.5O.sub.2. Thus, there is a comparatively large number of layers. Furthermore, FIG. 2 lacks a thick cover layer, as in the exemplary embodiment of FIG. 1.
[0094] In the modification 1′ in FIG. 3, there is a thick cover layer 31 and two pairs of intermediate layers 32, 33, each with an optical thickness of L/4. The materials and geometric layer thicknesses are given as examples for a wavelength of maximum intensity L of 616 nm in FIG. 3.
[0095] In the exemplary embodiment of the semiconductor chip 1, as shown in FIG. 4, three of the intermediate layers 32, 33, 34 are present, which follow the cover layer 31. The cover layer 31 has an optical thickness of approximately 1.22 L. The optical thicknesses of the intermediate layers 32, 33, 34 increase from the cover layer 31 towards the metal layer 39. The differences in optical thickness between adjacent intermediate layers 32, 33, 34 increase towards the metal layer 39.
[0096] The exemplary embodiment of FIG. 5 shows four of the intermediate layers 32, 33, 34, 35. For three of the intermediate layers 33, 34, 35, the optical thickness increases in the direction away from the metal layer 39, starting at the metal layer 39. The intermediate layer 32 nearest to the cover layer 31 has the second highest optical thickness. The intermediate layer 35 closest to the metal layer 39 is significantly thinner than L/4.
[0097] The materials and thicknesses mentioned in FIGS. 4 and 5 are only examples. All layers 31, 32, 33, 34, 35 each have optical thicknesses unequal to L/4. The optical thicknesses of the intermediate layers 32, 33, 34, 35, as shown in FIGS. 4 and 5, may also apply in slightly modified form, for example with a tolerance of not more than 0.04 L or 0.02 L each.
[0098] FIG. 6 shows a reflectivity R in percent as a function of the thickness of the cover layer T in nm. Here the exemplary embodiment of the semiconductor chip 1 from FIG. 1 compared with a modification 1′. This modification 1′, as illustrated in FIG. 6, corresponds to the modification 1′ of FIG. 3, but without the intermediate layers 32, 33.
[0099] It can be seen from FIG. 6 that for the exemplary embodiment of the semiconductor chip 1 the reflectivity R is reduced by a too thin cover layer 31 and that compared to the modification 1′ a reflectivity R is achieved which is about 0.4 percentage points higher.
[0100] FIG. 7 compares the reflectivities R for the modification 1′, as explained in connection with FIG. 6 and based on FIG. 3, as well as the modification 1′ of FIG. 2 and the exemplary embodiment of the semiconductor chip 1 of FIG. 5. It can be seen that a significantly increased reflectivity R can be achieved with the design of the semiconductor chip 1 of FIG. 5. The reflectivity R, as shown in FIG. 7, refers to the reflectivity integrated over all angles.
[0101] In FIGS. 8A to 8F, the reflectivity R is plotted against an angle of incidence E in degrees and the wavelength 2, in nm, for various exemplary embodiments and modifications. The coding of the reflectivity R is shown in FIG. 8G.
[0102] FIG. 8A refers to a modification 1′ with a mirror with a thick silicon dioxide layer and a gold layer directly underneath, i.e., the structure of FIG. 3 without the intermediate layers 32, 33.
[0103] FIG. 8B illustrates a modification 1′ using 10 pairs of layers, corresponding to 20 layers, of silicon dioxide and Nb.sub.2O.sub.5, with the lowest layer directly on the metal mirror being of Nb.sub.2O.sub.5. The component in FIG. 8B thus corresponds to the modification 1′ of FIG. 2, but without the low refractive intermediate layer 32 nearest to the metal layer 39.
[0104] In the modification 1′, as illustrated in FIG. 8C, there are 10.5 pairs of layers, corresponding to 21 layers, as illustrated in FIG. 2. Directly at the metal mirror there is therefore a low refractive index layer.
[0105] FIG. 8D shows the reflectivity for the exemplary embodiment of the semiconductor chip 1 according to FIG. 1.
[0106] FIG. 8E shows the reflectivity R for the exemplary embodiment of the semiconductor chip 1 shown FIG. 5.
[0107] Finally, FIG. 8F shows the reflectivity R for the modification 1′ of FIG. 3.
[0108] FIGS. 8D and 8E in particular show that a uniformly high reflectivity R can be achieved down to comparatively small angles of incidence E, in contrast to FIGS. 8B and 8C. Furthermore, a considerably lower spectral dependence of the reflectivity R can be achieved, in particular at longer wavelengths above 600 nm.
[0109] Due to the strong modulation of the reflectivity R, as shown in FIGS. 8B and 8C, the larger number of layer pairs does not lead to an increased reflectivity overall. This can also be seen in FIG. 7.
[0110] In FIG. 9, a radiated intensity I, normalized to one, is plotted against a radiation angle A. The modification 1′, as described in FIG. 6, i.e., the design of FIG. 3 without the intermediate layers 32, 33, is compared with the exemplary embodiment of the semiconductor chip 1 of FIG. 1. In addition, an ideal Lambertian radiation pattern is illustrated.
[0111] FIG. 9 shows that over a wide range of angles, no deviations between the exemplary embodiment 1 and the modification 1′ can be seen. In particular in the angular range between +−70° there are no significant deviations from a Lambertian radiation pattern. The intensity I refers in particular to a luminous flux averaged over all wavelengths.
[0112] In the exemplary embodiment of the semiconductor chip 1 of FIG. 10, several electrical through-connections 5 are formed through layers 31, 32, 33 of the mirror 3. The through-connections 5 are preferably metallic through-connections. Via the through-connections 5 the semiconductor layer sequence 2 is electrically connected to the metal layer 39 of the mirror 3. The metal layer 39 thus represents a part of an electrode 6 for supplying the semiconductor chip 1 with current.
[0113] The through-connections 5 are, for example, trapezoidal in cross section and may optionally become narrower in a direction towards the semiconductor layer sequence 2. Alternatively, the through-connections 5 can also be rectangular in cross-section.
[0114] The exemplary embodiment of FIG. 11 comprises an additional contact layer 4. The contact layer 4 extends over the semiconductor layer sequence 2 and covers the through-connections 5 completely. Outside the through-connections 5 the contact layer may be removed.
[0115] The contact layer 4 is preferably made of a transparent conductive oxide such as ITO. A thickness of the contact layer 4 is, for example, between 15 nm and 30 nm and is therefore preferably so thin that it has no significant influence on the optical properties of the mirror 3 and/or the semiconductor chip 1. Such a contact layer 4 is preferably also present in the examples of FIGS. 1, 4 and 5. If the contact layer 4 has a greater thickness and becomes optically effective, the thicknesses of the cover layer 31 and the intermediate layers 31, 32, 33, 34 may have to be adjusted accordingly to achieve maximum reflectivity.
[0116] FIG. 12 illustrates that the cover layer 31 and the intermediate layers 32, 33, 34 extend over the entire surface of the metal layer 39. The layers 31, 32, 33, 34 are preferably made of an electrically conductive material such as a transparent conductive oxide. This means that through-connections, as shown in FIG. 10 or 11, are not necessary. The contact layer 4 can also be omitted.
[0117] One electrode 6 is located on the light extraction side 10 and may be connected to a current expansion structure, which is not drawn here. The metal layer 39 of the mirror 3 can be located on an electrode 6 on a carrier 7. Over regions of the electrode 6 next to the semiconductor layer sequence 2, an external electrical contact is optionally possible, for example via bonding wires. The electrode 6 on the light extraction side 10 can also be contacted, for example, via a bonding wire. If the carrier 7 is electrically conductive, a bond wire-free contact can be achieved from the side with the metal layer 39.
[0118] The further electrode 6 on the light extraction side 10 is not illustrated in FIGS. 10 and 11. Flip-chip designs are also possible in deviation from the illustrations in FIGS. 10 to 12.
[0119] The exemplary embodiments of FIGS. 13A to 13C, each comprises an additional adhesion promoting layer 8, which is located between the metal layer 39 and the intermediate layer, which is directly on the metal layer 39. According to FIG. 13B, the adhesion promoting layer layer 8 extends continuously over the metal layer 39 and also completely covers the through-connections 5, so that the through-connections 5 are overmoulded by the adhesion promoting layer 8. In FIG. 13A, however, the adhesion promoting layer 8 is confined to the boundary between the metal layer 39 and the nearest intermediate layer 32.
[0120] In addition, FIG. 13B shows that contact layer 4 is present in addition to the adhesion promoting layer 8. The adhesion promoting layer 8 and the contact layer 4 may be of the same or different materials.
[0121] In FIG. 13C, the adhesion promoting layer 8 is designed as illustrated in FIG. 13A. Additionally, the contact layer 4 is also present.
[0122] The adhesion promoting layer 8 is preferably made of a transparent conductive oxide like ITO. A thickness of the adhesion promoting layer 8, for example, is between 1 nm and 20 nm and is therefore preferably so thin that the adhesion promoting layer 8 is optically ineffective and has no or no significant influence on the optical properties of the mirror 3 and/or the semiconductor chip 1.
[0123] An adhesion promoting layer 8, as shown in FIGS. 13A to 13C, is preferably also present in all other exemplary embodiments.
[0124] FIGS. 14A and 14B each show that the semiconductor layer sequence 2 of semiconductor chip 1 is structured. The through-connections 5 are preferably located in regions of the semiconductor layer sequence 2 which are thicker than other regions. This structuring of the semiconductor layer sequence 2 may prevent that the active zone 23 is supplied with current directly below the electrode 6. The electrode 6 directly at the semiconductor layer sequence 2 is formed, for example, by current distribution ridges. In addition, such a structuring may increase the light outcoupling efficiency, since light can be deflected at the structuring. The cover layer 31 and the intermediate layers 32, 33 and also the metal layer 39 reproduce the semiconductor layer sequence 2 true to form. This means that the mirror 3 extends over the surface of the semiconductor layer sequence 2, but is not plan, but reflects the topography of the semiconductor layer sequence 2.
[0125] FIG. 14B shows that the contact layer 4 is additionally present. The contact layer 4 is only applied locally, in each case starting from the at least one assigned through-connection 5. In deviation from the illustration in FIG. 14B, it is possible to set where the active zone 23 is to be supplied with current due to the low electrical transverse conductivity of the first side 21 of the semiconductor layer sequence 2. Structuring the semiconductor layer sequence 2 itself can then be omitted.
[0126] Unless otherwise indicated, the components shown in the figures follow one another, preferably in the order given. Layers not touching each other in the figures are preferably spaced apart. As far as lines are drawn parallel to each other, the corresponding surfaces are preferably also aligned parallel to each other. Likewise, unless otherwise indicated, the relative positions of the drawn components to each other are correctly shown in the figures.
[0127] The invention is not restricted to the exemplary embodiments by the description on the basis of said exemplary embodiments. Rather, the invention encompasses any new feature and also any combination of features, which in particular comprises any combination of features in the patent claims and any combination of features in the exemplary embodiments, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.
