TEST STRUCTURE AND MANUFACTURING METHOD THEREFOR

Abstract

This application relates to the field of semiconductor technologies, and discloses a test structure and a manufacturing method therefor. Forms of the method may include: providing a top wafer structure, where the top wafer structure includes a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer; providing a bottom wafer structure, where the bottom wafer structure includes a bottom wafer and multiple second pads that are spaced from each other at a top of the bottom wafer, where a side surface of at least one of two adjacent second pads has an insulation layer; bonding the multiple first pads with the multiple second pads in a eutectic bonding manner, where each first pad is bonded with a second pad, to form multiple pads. This application may mitigate a problem that bonded pads are connected to each other.

Claims

1. A test structure manufacturing method, comprising: providing a top wafer structure, wherein the top wafer structure comprises a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer; providing a bottom wafer structure, wherein the bottom wafer structure comprises a bottom wafer and multiple second pads that are spaced from each other at a top of the bottom wafer, where a side surface of at least one of two adjacent second pads has an insulation layer; and bonding the multiple first pads with the multiple second pads in a eutectic bonding manner, wherein each first pad is bonded with a second pad, to form multiple pads.

2. The method according to claim 1, wherein the second pad whose side surface has the insulation layer has a trench.

3. The method according to claim 2, wherein a side wall of the trench has an insulation layer.

4. The method according to claim 2, wherein a bottom of the trench is higher than the top of the bottom wafer.

5. The method according to claim 2, wherein: a side surface of each second pad has an insulation layer; and the step of providing a bottom wafer structure comprises: providing the bottom wafer; forming a pad material layer on the bottom wafer; patterning the pad material layer, to form multiple initial second pads in a pad region; forming the insulation layer on a side surface of the initial second pad; and etching the initial second pad to form the trench, to form the second pad.

6. The method according to claim 3, wherein: a side surface of each second pad has an insulation layer; and providing a bottom wafer structure comprises: providing the bottom wafer; forming a pad material layer on the bottom wafer; patterning the pad material layer, to form the second pad having the trench; and forming the insulation layers on the side wall of the second pad and on the side wall of the trench.

7. The method according to claim 2, wherein the trench comprises multiple trenches whose extension directions are substantially parallel.

8. The method according to claim 1, wherein an area of the first pad accounting for the top wafer is less than an area of the second pad accounting for the bottom wafer.

9. The method according to claim 1, wherein a material of the insulation layer comprises one or more of the followings: a silicon oxide, a silicon nitride, or a silicon oxynitride.

10. The method according to claim 1, wherein: the pad comprises two metal elements; or the pad comprises a metal element and a semiconductor element.

11. The method according to claim 1, wherein a micro-electro-mechanical systems (MEMS) sensor is formed in one of the top wafer or the bottom wafer.

12. A test structure, comprising: a top wafer; a bottom wafer, located under the top wafer; and multiple pads, configured to connect to the top wafer and the bottom wafer, wherein a side surface of at least one of two adjacent pads has an insulation layer.

13. The test structure according to claim 12, wherein separated insulation layers are embedded in the pad whose side surface has the insulation layer.

14. The test structure according to claim 13, wherein a bottom of the insulation layers embedded in the pad is higher than a top of the bottom wafer.

15. The test structure according to claim 12, wherein a material of the insulation layer comprises one or more of the followings: a silicon oxide, a silicon nitride, or a silicon oxynitride.

16. The test structure according to claim 12, wherein the pad comprises two metal elements; or the pad comprises a metal element and a semiconductor element.

17. The test structure according to claim 12, wherein a micro-electro-mechanical systems (MEMS) sensor is formed in one of the top wafer or the bottom wafer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings constitute a part of this specification describing exemplary embodiments and implementations of the present application, and are used, together with this specification, to explain the principles and concepts of the present application. In the accompanying drawings:

[0027] FIG. 1 is a schematic diagram of an existing test structure;

[0028] FIG. 2 is a schematic flowchart of one form of a test structure manufacturing method;

[0029] FIG. 3 is a schematic diagram of a top wafer structure;

[0030] FIG. 4 is a schematic diagram of a bottom wafer structure;

[0031] FIG. 5 is a schematic diagram of one form of a test structure;

[0032] FIG. 6A is a schematic diagram of another implementation of a bottom wafer structure;

[0033] FIG. 6B is a schematic diagram of another implementation of a bottom wafer structure;

[0034] FIG. 6C is a schematic top view of a second pad having a trench;

[0035] FIG. 7A to FIG. 7E are schematic diagrams of stages of forming the bottom wafer shown in FIG. 6A;

[0036] FIG. 8A to FIG. 8D are schematic diagrams of stages of forming the bottom wafer shown in FIG. 6B;

[0037] FIG. 9 is a schematic diagram of another form of a test structure;

[0038] FIG. 10A shows an example of a test result of an existing test structure; and

[0039] FIG. 10B shows an example of a test result of a test structure according to forms of the present application.

DETAILED DESCRIPTION

[0040] Various exemplary embodiments and implementations of the present application are described in detail with reference to the accompanying drawings. It should be understood that, unless otherwise specified, relative layout of the parts and the steps that are described in the embodiments, numerical expressions, and values should not be construed as limiting the scope of this application.

[0041] In addition, it should be understood that, for ease of description, sizes of the parts shown in the accompanying drawings are not necessarily drawn according to actual ratios. For example, thicknesses or widths of some layers may be exaggerated relative to other layers.

[0042] The following descriptions of exemplary embodiments and implementations are merely illustrative, and do not limit this application and application or use of this application.

[0043] Technologies, methods, and apparatuses that are known by a person of ordinary skill in the art may not be discussed in detail, but the technologies, methods, and apparatuses shall be considered as a part of this specification when appropriate.

[0044] It should be noted that, similar reference signs and letters in the following accompanying drawings represent similar items. Therefore, once one item is defined or illustrated in one accompanying drawing, the item does not need to be further discussed in subsequent accompanying drawings.

[0045] The inventor has performed extensive research on a problem of WAT test failure, and finds that, after a top wafer 101 and a bottom wafer 102 is bonded, two adjacent pads 103 and 104 can connect to each other, that is, form a bridge, as shown in FIG. 1. The adjacent pads form the bridge, resulting in a short circuit of a test structure, further resulting in failure of the WAT test. Accordingly, the inventor puts forward the following solutions.

[0046] FIG. 2 is a schematic flowchart of one form of a test structure manufacturing method. FIG. 3 to FIG. 5 are schematic diagrams of stages of a test structure manufacturing method.

[0047] The following provides a detailed description of one form of a test structure manufacturing method with reference to FIG. 2 and FIG. 3 to FIG. 5.

[0048] As shown in FIG. 2, in step 202, a top wafer structure is provided.

[0049] FIG. 3 is a schematic diagram of one implementation of a top wafer structure. As shown in FIG. 3, the top wafer structure includes a top wafer 301 and multiple first pads 302 (two first pads are schematically shown in FIG. 3) that are spaced from each other at a bottom of the top wafer 301. Each first pad 302 may be in contact with a connective kit 303 of the top wafer 301. A material of the first pad 302 may be a semiconductor, such as germanium; or may be a metal, such as tin, aluminum, or copper.

[0050] It should be understood that, the connective kit 303 shown in FIG. 3 is merely schematic. In fact, the top wafer 301 may include different metal layers, and the different metal layers may be connected using a corresponding connective kit 303 (for example, a metal connective kit). In addition, a logic circuit, for example, a logic circuit including components such as an MOS component, may be formed in the top wafer 301.

[0051] In step 204, a bottom wafer structure is provided.

[0052] FIG. 4 is a schematic diagram of one implementation of a bottom wafer structure. As shown in FIG. 4, the bottom wafer structure includes a bottom wafer 401 and multiple second pads 402 that are spaced from each other at a top of the bottom wafer 401. Each second pad 402 may be in contact with a connective kit 403 in the bottom wafer 401. A side surface of at least one of two adjacent second pads 402 has an insulation layer 404. A material of the insulation layer 404 may include one or more of the followings: a silicon oxide (for example, SiO.sub.2), a silicon nitride (for example, SiN), or a silicon oxynitride (for example, SiON). A material of the second pad 402 may be a semiconductor, such as germanium; or may be a metal, such as tin, aluminum, or copper.

[0053] In a case, side surfaces of both two adjacent second pads 402 may have insulation layers 404, as shown in FIG. 4. In another case, a side surface of one of two adjacent second pads 402 has an insulation layer 404, but a side surface of the other second pad 402 may have no insulation layer 404.

[0054] In some implementations, an MEMS sensor, such as an MEMS inertial sensor, may be formed in the bottom wafer 401. In other implementations, an MEMS sensor may be formed in the top wafer 301.

[0055] In step 206, the multiple first pads 302 are bonded with the multiple second pads 402 in a eutectic bonding manner, to form multiple pads 501, to form a test structure shown in FIG. 5. Then, a WAT test is performed on the test structure.

[0056] During the bonding, each first pad 302 is bonded with a corresponding second pad 402, and the two pads form a pad 501 after the bonding. Preferably, the bonded pad 501 is an alloy pad. In some implementations, the pad 501 includes two metal elements. In other implementations, the pad 501 includes a metal element and a semiconductor element. In some implementations, a resistance of the bonded pad is less than that of the first pad 302 before the bonding, and is less than that of the second pad 402.

[0057] In the foregoing embodiments and implementations, because an insulation layer 404 is formed on a side surface of at least one of adjacent second pads 402, adjacent pads in the multiple pads 501 that are formed after the bonding may be prevented from being connected together.

[0058] In some implementations, an area of the first pad 302 accounting for the top wafer 301 is less than an area of the second pad 402 accounting for the bottom wafer 401, to make a bonding reaction occur as much as possible in a region in which the second pad 402 is located, and to prevent a pad material from overflowing from the top wafer 301 during the bonding, so as to better prevent the pads 501 that are formed after the bonding from being connected together.

[0059] The inventor finds that, the insulation layer 404 is formed, but the pad material may still overflow during the bonding, consequently, adjacent bonded pads 501 may still be connected together. Accordingly, the inventor also puts forward the following two improvement solutions.

[0060] FIG. 6A is a schematic diagram of another form of a bottom wafer structure. Compared with the bottom wafer structure shown in FIG. 4, a trench 412 (may also be referred to as a hollow) may be formed in a second pad 402 of the bottom wafer structure shown in FIG. 6A. In some implementations, the trench 412 may include multiple trenches whose extension directions are basically parallel. In other implementations, the trench 412 may include first trenches extending along a first direction and multiple second trenches extending along a second direction, and the first trenches and the second trenches may intersect. Forming of the trench 412 may provide space for the bonding process, thereby preventing a pad material from overflowing, so as to better prevent pads that are formed after bonding from being connected together.

[0061] It should be understood that, this application is not limited to the foregoing specific arrangement of the trench 412, provided that the second pad 402 has the trench 412 providing space for the bonding process.

[0062] In some implementations, the trench 412 may extend to a top of a bottom wafer 401, that is, the trench threads through the second pad 402. Alternatively, the trench may stop in the second pad 402, so that a bottom of the trench 412 is higher than the top of the bottom wafer 401, as shown in FIG. 6A. In some implementations, the bottom of the trench 412 is higher than the top of the bottom wafer 401, so that a connective kit 403 under the second pad 402 is prevented from being damaged when the trench 412 is formed.

[0063] FIG. 6B is a schematic diagram of yet another form of a bottom wafer structure. Compared with the bottom wafer structure shown in FIG. 6A, in the bottom wafer structure shown in FIG. 6B, a side wall of the trench 412 has an insulation layer 601. In some implementations, the insulation layer 601 may be formed only on a lower portion of the side wall of the trench 412. That is, the insulation layer 601 may not be on an upper portion of the side wall of the trench 412. The second pad 402 having the trench 412 may be regarded as including multiple strip (which may also be another shape, and the strip is used as an example herein) pads, and adjacent strip pads are separated by the trench 412. In a bonding process, because a top wafer and a bottom wafer may extrude each other, the strip pads may tilt, affecting contact between upper first pads and lower second pads, affecting a bonding effect. However, when the side wall of the trench 412 has the insulation layer 601, the insulation layer 601 has a support function, to prevent the strip pads from tilting, and improve the bonding effect.

[0064] FIG. 6C is a schematic top view of a second pad 401 having a trench 412. Herein, for brevity, only the trench 412 is shown, but an insulation layer 601 on a side wall of the trench 412 is not shown.

[0065] The following describes a forming manner of the bottom wafer structure shown in FIG. 6A according to FIG. 7A to FIG. 7E.

[0066] First, a bottom wafer 401 is provided, and a pad material layer 402A is formed on the bottom wafer 401, as shown in FIG. 7A. An MEMS sensor, a connective kit 403, and the like may be formed in the bottom wafer 401.

[0067] Then, the pad material layer 402A is patterned, to form multiple initial second pads 402B (that is, second pads in the prior art) in a pad region (that is, a region covering the connective kit 403), as shown in FIG. 7B. For example, the pad material layer 402A may be patterned using photoetching and etching process.

[0068] Next, insulation layers 404 are formed on side surfaces of the initial second pads 402B.

[0069] In an implementation, as shown in FIG. 7C, an insulation material layer 404A is deposited, and the insulation material layer 404A covers a surface of the bottom wafer 401 and surfaces and the side surfaces of the initial second pads 402B. Then, as shown in FIG. 7D, the insulation material layer 404A on the surface of the bottom wafer 401 and on the surfaces of the initial second pads 402B is removed by means of anisotropic etching, and the remaining insulation material 404A on the side surfaces of the initial second pads 402B are used as the insulation layers 404.

[0070] Then, the initial second pads 402B are etched, to form trenches 412, so as to form second pads 402, as shown in FIG. 7E. For example, a patterned mask layer, for example, a photoresist, is formed on the initial second pads 402B, to define a shape of the trenches; then, the initial second pads 402B are etched by using the mask layer as a mask, to form the trenches 412.

[0071] The bottom wafer structure shown in FIG. 6A may be formed using the foregoing process, then the top wafer structure shown in FIG. 3 may be bonded with the bottom wafer structure shown in FIG. 6A, to form a test structure similar to that in FIG. 5.

[0072] The following describes a manner for forming the bottom wafer structure shown in FIG. 6B according to FIG. 8A to FIG. 8D.

[0073] First, a bottom wafer 401 is provided, and a pad material layer 402A is formed on the bottom wafer 401, as shown in FIG. 8A.

[0074] Then, the pad material layer 402A is patterned, to form second pads 402 having trenches 412, as shown in FIG. 8B. If a bottom of the trenches 412 is higher than a top of the bottom wafer 402, the initial second pads 402B shown in FIG. 7B may be first formed in a similar manner, and then the initial second pads 402B are etched, to form the trenches 412. If the bottom of the trenches 412 is the top of the bottom wafer 402, the second pads having the trenches 412 may be formed by performing photoetching once.

[0075] Then, insulation layers 404 are formed on side surfaces of the second pads 402 and on side walls of the trenches 412.

[0076] In an implementation, as shown in FIG. 8C, an insulation material layer 404A is deposited on the structure shown in FIG. 8B, and the insulation material layer 404A covers a surface of the bottom wafer 401, surfaces and the side surfaces of the second pads 402, and the bottom and the side walls of the trenches 412. Then, as shown in FIG. 8D, the insulation material layer 404A on the surface of the bottom wafer 401 and on the surfaces of the second pads 402B is removed by means of anisotropic etching, the remaining insulation material 404A on the side surfaces of the second pads 402B are used as the insulation layers 404, and the remaining insulation material layer 404A on the side walls of the trenches 412 are used as insulation layers 601. It should be noted that, in an anisotropic etching process, the insulation material layer 404A on upper portions of the side walls of the trenches 412 may be removed, so that only the insulation material layer 404A on lower portions of the side walls of the trenches 412 are reserved. It should be understood that, the upper portions and the lower portions described herein are only opposite concepts, and have no fixed demarcation line.

[0077] The bottom wafer structure shown in FIG. 6B may be formed using the foregoing process, then the top wafer structure shown in FIG. 3 may be bonded with the bottom wafer structure shown in FIG. 6B, to form a test structure shown in FIG. 9.

[0078] FIG. 10A shows an example of a test result of an existing test structure. FIG. 10B shows an example of a test result of a test structure according to implementations of the present application. FIG. 10A and FIG. 10B show breakdown voltages between a source and a drain of an N-type transistor. It can be seen from FIG. 10A that, because adjacent pads after bonding are connected to each other, resulting in short circuit of the test structure, most of test results deviate from a normal breakdown voltage. However, it can be seen from FIG. 10B that, test results slightly float, and the test results are valid.

[0079] Based on the manufacturing methods in the foregoing different embodiments and implementations, this application also provides different test structures.

[0080] In one implementation, referring to FIG. 5, a test structure includes a top wafer 301, a bottom wafer 401 located under the top wafer 301, and multiple pads 501. The multiple pads 501 are configured to connect to the top wafer 301 and the bottom wafer 401. A side surface of at least one of two adjacent pads 501 has an insulation layer 404. In some implementations, the pad 501 is an alloy pad. For example, the pad 501 may include two metal elements. For another example, the pad 501 may include a metal element and a semiconductor element.

[0081] In some implementations, referring to FIG. 9, separated insulation layers 601 are embedded in a pad 501 whose side surface has an insulation layer 404. Preferably, a bottom of the insulation layers 601 embedded in the pad 501 is higher than a top of a bottom wafer 401.

[0082] Above, test structures and manufacturing methods therefor according to this application have been described in detail. To avoid obstructing the concepts of the present application, some details known in the art are not described. A person skilled in the art will fully understand, according to the foregoing descriptions, how to implement the technical solutions disclosed herein. In addition, the embodiments and implementations disclosed herein may be freely combined. A person skilled in the art will understand that modifications may be made to the foregoing embodiments and implementations without departing from the scope and the spirit of this application that are limited by the appended claims.