DIGITAL BIOPOTENTIAL ACQUISITION SYSTEM HAVING 8 CHANNELS

Abstract

A biocompatible recording system includes a number of input channels for acquiring electronic information from the neural system of a living being. The recording system includes a preamplifier and further amplifier stages. An input of a second amplifier stage is coupled to an output of the preamplifier. A low-pass filter having a capacitance multiplier is connected to the second amplifier stage. The preamplifier of the recording system is designed using P-MOS technology.

Claims

1. A biocompatible recording system for acquiring electronic information from the neural system of a living being, the recording system comprising: a first amplifier stage comprising a preamplifier; a second amplifier stage, wherein an input of the second amplifier stage is coupled to an output of the preamplifier; and a low-pass filter having a capacitance multiplier connected to the second amplifier stage.

2. The recording system according to claim 1, wherein the preamplifier uses P-MOS input transistors in the first amplifier stage.

3. The recording system according to claim 1, wherein the recording system can acquire at least two signals independently of one another with at least two recording channels.

4. The recording system according to claim 1, wherein the recording system has variable lower (fcL) and upper (fcU) corner frequencies by variation of predetermined signals.

5. The recording system according to claim 2, wherein the first amplifier stage comprises a fully-differential telescopic architecture.

6. The recording system according to claim 1 comprising a flip-flop-based parallel-serial converter that is integrated into the recording system.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0023] FIG. 1 is a block diagram of a recording system in accordance with the present disclosure;

[0024] FIGS. 2A and 2B are diagrams of an architecture in accordance with the present disclosure;

[0025] FIG. 3 is a graph of performance curves for predefined noise behavior;

[0026] FIG. 4 is a block diagram of a second stage in accordance with the present invention;

[0027] FIG. 5 is another block diagram of a second stage in accordance with the present invention;

[0028] FIG. 6 is a block diagram of a control current capacitance multiplier;

[0029] FIG. 7 is a block diagram of signal paths from amplifier outputs to serial digital outputs;

[0030] FIG. 8 is a schematic image of a chip with 8 bipolar input channels in accordance with the present disclosure;

[0031] FIG. 9 is a diagram of I/O pins of an LNA8 chip in accordance with the present disclosure;

[0032] FIG. 10A is a graph showing variation of lower cut-off frequency via VTune in accordance with the present disclosure;

[0033] FIG. 10B is a graph showing variation of upper cut-off frequency via control of the bas VGC+ of the capacitance multiplier in accordance with the present disclosure;

[0034] FIG. 11 is a first graph showing frequency versus magnitude in accordance with the present disclosure;

[0035] FIG. 12A is a second graph showing frequency versus magnitude in accordance with the present disclosure;

[0036] FIG. 12B is a third graph showing frequency versus magnitude in accordance with the present disclosure;

[0037] FIG. 12C is a graph showing frequency versus phase in accordance with the present disclosure;

[0038] FIG. 13 is a graph showing measured curves in comparison to schematic and analog extracted simulations;

[0039] FIG. 14 is a graph showing total integrated input noise for different amplifier configurations;

[0040] FIG. 15A is an image of three successive contractions of an exemplary biceps by EMG detection;

[0041] FIG. 15B is an image of three successive contractions of an exemplary biceps by ECG detection;

[0042] FIG. 16 shows a comparison of a low-noise amplifier (LNA) according to the present disclosure with other systems;

[0043] FIG. 17A are diagrams based on the source neural impulse and muscular impulse; and

[0044] FIG. 17B are diagrams based on image action potential and action current.

DETAILED DESCRIPTION

LNA Preamplifier

[0045] It is known that the first stage (preamplifier) is the most important stage in an amplifier chain, as it is the component which is most susceptible to noise. For this reason, a fully-differential telescopic architecture has been used.

[0046] The architecture shown in FIGS. 2a and 2b provides high gain and bandwidth in a single stage and theoretically an infinite common mode rejection ratio (CMRR) and infinite noise suppression (PSRR).

[0047] The equations of the amplifier channels are known, and rephrased for the g.sub.m/I.sub.D design methodology, the noise model is as follows:

[00001]$\begin{array}{cc}\stackrel{\_}{V_{n,\mathrm{in}}^z}=\frac{16.Math..Math.\mathrm{kT}?\left(?.Math..Math.f-1\right)}{3.Math.{\left(\frac{g_m}{I_D}\right)}_{1.2}}.Math.\left(1+\frac{{\left(\frac{g_m}{I_D}\right)}_{7.0}}{{\left(\frac{g_m}{I_D}\right)}_{1.2}}\right).Math.\frac{1}{I_D}+\frac{2.Math..Math.\ln .Math..Math.?.Math..Math.f}{C_{\mathrm{ox}}}.Math.\left(\frac{K_n}{{\left(\mathrm{WL}\right)}_{1.2}}+{\frac{K_p}{{\left(\mathrm{WL}\right)}_{7.8}}?\left[\frac{{\left(\frac{g_m}{I_D}\right)}_{7.0}}{{\left(\frac{g_m}{I_D}\right)}_{1.2}}\right]}^2\right)& \left(1\right)\end{array}$

[0048] And the transfer function:

[00002]$\begin{array}{cc}H?\left(s\right)=2.Math.\frac{C_{\mathrm{IN}}}{C_F}.Math.\frac{\frac{s}{2.Math..Math.?.Math..Math.f_{\mathrm{cL}}}}{\left(1?\begin{array}{c}s\\ 2.Math..Math.?.Math..Math.f_{\mathrm{cL}}\end{array}\right).Math.{\left(1?\begin{array}{c}s\\ 2.Math..Math.?.Math..Math.f_{\mathrm{cL}}\end{array}\right)}^{}}.Math..Math.\mathrm{with}& \left(2\right)\\ f_{\mathrm{cL}}=\frac{1}{2.Math..Math.?.Math..Math.R_F.Math.C_F};f_{\mathrm{cU}}=\frac{C_F}{C_{\mathrm{IN}}}.Math.\frac{g_{m.Math..Math.1,2}}{?.Math..Math.C_I}=\frac{C_F}{C_{\mathrm{IN}}}.Math.\frac{\sqrt{{?}_{1,2}}}{?.Math..Math.C_L}.Math.\sqrt{I_{\mathrm{SS}}}& \left(3\right)\end{array}$

[0049] Legend:

TABLE-US-00001 Kn Glitter noise constant NMOS 120 ? 10.sup.?24 V.sup.2F Kp Glitter noise constant PMOS 20 ? 10.sup.?24 V.sup.2F k Boltzmann's constant 1,3806 ? 10.sup.?23 m.sup.2kg/s.sup.2K (1) V.sup.2.sub.n, in Total input noise V.sub.RMS k Boltzmann's constant l T Temperature K gm Transconductance A/V ID Current level at drain terminal A (2) C.sub.IN Input capacity F C.sub.F Feedback capacity F f.sub.cL lower corner frequency Hz f.sub.cU upper corner frequency Hz (3) R.sub.F Feedback resistance ? ? MOSFET transistor current amplification A/V.sup.2 I.sub.SS Polarization current for FD telescope amplifier A

[0050] Using the PMOS transistors and the optimal point marked in FIG. 3, the variables shown in Table 1 below were determined:

TABLE-US-00002 TABLE 1 Variables of the PMOS FD telescope amplifier FD-telescopic Parameter Variables W [?m] L [?m] M.sub.1, 2 8000 1.5 M.sub.3, 4 1728 0.5 M.sub.5, 6 168 1 M.sub.7, 8 288 24 Load capacity 30.5 pF Bias current I.sub.ss 205 ?A Active surface 0.04 mm.sup.2 Layout surface 0.15 mm.sup.2 Channel surface 2028 ? 720 ?m.sup.2

Second Stage

[0051] The second stage shown in FIG. 4 is responsible for the conversion from FD (fully differential) to single-ended, with an input noise in an amount of 6 ?V.sub.RMS for a power consumption of 148 ?W (11 ?V.sub.RMS and 46 ?W in LP mode). Due to feedback, it delivers a gain of either 0 dB or 20 dB. The OTA consists of a single-ended 2-stage Miller amplifier.

[0052] In the field of electronics, the Miller effect is the increase in the equivalent input capacitance of an inverting voltage amplifier due to the amplification of the effect of the capacitance between the input and output terminals. The apparently increased input capacity due to the Miller effect results as follows:

C.sub.M=C(1+A.sub.v)

[0053] where ?A.sub.v is the gain and C is the feedback capacitance.

[0054] Although the term Miller effect usually refers to capacitances, any impedance connected between the input and another node showing gain can modify the amplifier input impedance with this effect.

Low-Pass Filter with Capacitance Multiplier

[0055] Since different applications require different upper corner frequencies fcu, a variable RC low-pass filter has been integrated.

[0056] In one reference, this variation was achieved by adjusting the LNA bias current Iss, creating a variation of the noise behavior. O. F. Cota, et al., In-vivo characterization of a 0.8-3 \muV RMS input-noise versatile CMOS pre-amplifier, Neural Engineering (NER), 2015 7th International IEEE/EMBS Conference on, 2015, S. 458-461. To avoid this unwanted coupling, a capacitance multiplier was proposed which uses the control current OTA from J. Ramirez-Angulo, et al., Gain programmable current mirrors based on current steering, Electronics Letters, vol. 42, no. 10, S. 559-560, 2006 and which is connected to the second stage as is described in J. A. Ruiz, et al., Three novel improved CMOS capacitance scaling schemes, in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, S. 1304-1307. The capacitance multiplication factor (from 50 pF to 5 nF) is set by the differential input V.sub.GC?, the bias current of 56 ?A and an area of 0.013 mm.sup.2.

MUX, Analog-to-Digital Converter and Serial Output

[0057] The chip uses the X-Fab 0.35 ?m library 10-bit SAR-ADC and integrates a user-defined flip-flop-based parallel-serial converter. The 16-bit little-endian output is combined as in J. Ramirez-Angulo, S. R. Garimella, A. J. L?pez-Martin, and R. G. Carvajal, Gain programmable current mirrors based on current steering, Electronics Letters, vol. 42, no. 10, S. 559-560, 2006, where S represents the start token bits (H L), bits C3-C0 represent the channel number and bits D9-D0 represent the ADC sample values.

Power Consumption

[0058] The power consumption of the chip is summarized in Table 2:

TABLE-US-00003 TABLE 2 2 St + Cap. mult. Total (sim) (*sim values) 1 St [mW] Bias. (mW) ADCs mW 29 ?A 0.765 2.03 1.19 0.495 4.49 29 ?A LP 1.23 (optional) 3.68 210 ?A 5.54 mW 2.03 1.19 9.26 210 ?A 1.23 (optional) 8.46 271 ?A 7.15 mW 2.03 1.19 10.87 271 ?A 1.23 (optional) 10.06

Result

[0059] The chip shown in FIG. 8 is manufactured using X-Fab 0.35 ?m technology. The amplifier I/O pins are summarized in Table 2. The system pins offer flexibility for the parameters: [0060] Enable function: continuous ISS variation, second stage low-power (LP) mode, capacitance multiplier, 20 dB gain [0061] Bias voltage: V.sub.REF.sub._.sub.ISS, V.sub.REF.sub._.sub.CMFB [0062] Frequency range variation: V.sub.GCP/N, V.sub.TUNE

[0063] Although the chip is designed for digital output, it contains test pins to support its characterization, such as the analog outputs of the preamplifier and the low-pass filter of channels 1 and 5.

[0064] Table 3, below, shows I/O pins of the LNA8 chip. Underlined pins represent outputs.

TABLE-US-00004 TABLE 3 Analog Digital (D, A)V.sub.DD 3 I.sub.SS(T1-T4) 4 (D, A)V.sub.SS 3 V_REF_ISS_EN V.sub.REF ISS LP EN VIN(N/P)(1-8) 16 RESET EN V.sub.REF CMFB GAIN_0dB_EN V.sub.GCP/N 2 CAP MULT EN V.sub.TUNE CLK V.sub.REFH CHSEL.sub.0-3 4 V.sub.REFL DSOUT(?) 2 Test (analog) V.sub.EXTCMFB V.sub.DDISS(1, 5) 2 V.sub.OUTN/P(1, 5) 2 V.sub.OUT1/5 2 Test (digital) RESET ADC Q1.sub.0-3 4 EOC1 SW1
The ADCs can be clocked with two serial digital outputs up to 1 MHz.

Frequency Response

[0065] The LNA8 recording system has variable corner frequencies fcU, fcL in each case by varying the potentials V.sub.TUNE and V.sub.GC?.

Noise Behavior

[0066] The spectral noise density of the amplifier was measured for different bias currents and bandwidth setting voltages.

[0067] The graphical representation in FIG. 13 shows the measured curves in comparison to the schematic and analog extracted simulations. FIG. 14 shows the total integrated input noise for different amplifier configurations. The curve shows a minimum noise of *(sim. value) 0.6 V.sub.RMS for I.sub.SS=250 ?A.

In Vivo Recording

[0068] The acquisition system has been tested with bioelectric in-vivo signals as shown in FIG. 15. The bioelectric signals were extracted directly from the serial digital outputs using SPI decoding. The SPI bus (Serial Peripheral Interface) is a synchronous, serial communication interface specification used for short-range communication. SPI devices can communicate with a single master in full duplex operation using a master-slave architecture. The master device generates the frame for reading and writing. A multitude of slave devices are supported by selection with individual slave select lines (SS).

[0069] FIG. 15A shows three successive contractions of an exemplary biceps EMG detection. FIG. 15B shows an ECG detection.

[0070] The foregoing description shows the implementation of a biopotential acquisition system with 8 channels.

[0071] Although the best noise efficiency factor is achieved by the design that uses BJT transistors, this has the disadvantage that a residual DC current of 20 nA remains, which can lead to electrode corrosion in the long run.

[0072] The capacitance multiplier fulfilled its function of providing a wide range for the upper cut-off frequency.

[0073] However, since it was dimensioned for minimum area and power consumption, the noise behavior could not be kept below 1 ?V.sub.RMS without a capacitance multiplier; the noise behavior can be maintained by software filtering.

[0074] Table 4 shows a comparison of the shown low-noise amplifier (LNA) with other systems.

TABLE-US-00005 TABLE 4 System Amplification/db Noise/?V.sub.RMS Power/Channel/?W fcL/Hz fcU/Hz CMRR/db NRF M. Yin and M. 40; 77 4.9 49 0.01-1k 700-10k 139 7.84 Ghovanloo J. Taylor and 80 0.291 2400 (5 V) DC .sup.5k 82 3.57 R. Rieger F. Zhang, 40 2.2 12 (IV) 0.3 10k 80 2.9 et al. [9] >100 1.9(10 kHz) 576 (1.8 V) DC 20k >99 12.9 Before O. F. 41-45 0.8-2.7 3.3-3300 0.2-10k 38-11k 78 8.9-15 Cota, et al. Present 39.3 or 1.94-0.69* 303-1200* 0.1-10k 200-20k 60.3; 74 3.52 (1. stage) Design 58.4 (sim val) (sim) 6.57 (2. stage)

[0075] Compared to the previous work in O. F. Cota, et al., the present design integrated the other blocks of the desired system.

[0076] The amplifier area has been reduced by a factor of four and an analog output.

Result

[0077] The invention shows the successful implementation and the testing of a versatile bioelectric signal acquisition chip with 8 channels. The amplified channels are selected from two analog multiplexers and are output by two SPI-compatible 16-bit data streams. The total integrated input noise can be reduced to *(sim. value) 0.6 ?V.sub.RMS for bandwidths between 1 Hz and 10 kHz. The acquisition system has been tested for ECG and EMG applications.