DEVICE AND METHOD FOR ELIMINATING ELECTROMAGNETIC INTERFERENCE

Abstract

This application relates to a device and a method for eliminating electromagnetic interference (EMI). The device for eliminating EMI includes: a timing control chip; and a phase-locked loop module, electrically connected to the timing control chip and including: a phase detection unit, configured to detect a frequency generated by a clock cycle to generate a frequency difference; a charge pump unit, configured to generate a regulation voltage; a voltage-controlled oscillator unit, configured to control an oscillation frequency when the regulation voltage is input; a plurality of frequency divider units, configured to generate a new output clock frequency by using an input clock frequency; and a selector unit, configured to select the appropriate frequency divider units, where the selector unit has another end electrically connected to needed power circuits.

Claims

1. A device for eliminating electromagnetic interference (EMI), comprising: a timing control chip; and a phase-locked loop module, electrically connected to the timing control chip and comprising: a phase detection unit, configured to detect a frequency generated by a clock cycle to generate a frequency difference; a charge pump unit, configured to generate a regulation voltage; a voltage-controlled oscillator unit, configured to control an oscillation frequency when the regulation voltage is input; a plurality of frequency divider units, configured to generate a new output clock frequency by using an input clock frequency; and a selector unit, configured to select the appropriate frequency divider units, wherein the selector unit has another end electrically connected to needed power circuits.

2. The device for eliminating EMI according to claim 1, wherein the timing control chip receives one piece of display data by using a front-end system.

3. The device for eliminating EMI according to claim 2, wherein after processing the display data, the timing control chip outputs a data signal and a clock cycle signal.

4. The device for eliminating EMI according to claim 1, wherein a formula of generating the new output clock frequency by the frequency divider units is: the new output clock frequency=1/N multiplied by the input clock frequency, wherein N is an integer.

5. The device for eliminating EMI according to claim 1, wherein the frequency divider units have at least one frequency dividing multiple.

6. The device for eliminating EMI according to claim 1, wherein the selector unit is electrically connected to at least four different power circuits.

7. The device for eliminating EMI according to claim 1, further comprising a power control chip, separately electrically connected to the phase-locked loop module and the timing control chip.

8. The device for eliminating EMI according to claim 7, wherein the power control chip is configured to control a power source to be supplied to the phase-locked loop module and the timing control chip.

9. A device for eliminating electromagnetic interference (EMI), comprising: a timing control chip; and a phase-locked loop module, electrically connected to the timing control chip and comprising: a phase detection unit, configured to detect a frequency generated by a clock cycle to generate a frequency difference; a charge pump unit, configured to generate a regulation voltage; a voltage-controlled oscillator unit, configured to control an oscillation frequency when the regulation voltage is input; a plurality of frequency divider units, configured to generate a new output clock frequency by using an input clock frequency; and a selector unit, configured to select the appropriate frequency divider units, wherein the selector unit has another end electrically connected to needed power circuits, wherein the frequency divider units have at least one frequency dividing multiple, and the selector unit is electrically connected to at least four different power circuits.

10. A method for eliminating electromagnetic interference (EMI), comprising steps of: receiving, by a timing control chip, one piece of display data, and outputting a data signal and a clock cycle signal after processing the display data; and electrically connecting, by a phase-locked loop module, to the timing control chip, comprising: detecting, by a phase detection unit, a frequency generated by a clock cycle to generate a frequency difference; generating, by a charge pump unit, a regulation voltage when the frequency difference is input; controlling, by a voltage-controlled oscillator unit, an oscillation frequency when the regulation voltage is input; generating, by a plurality of frequency divider units, a new output clock frequency by using an input clock frequency; and selecting, by a selector unit, the appropriate frequency divider units, wherein the selector unit has another end electrically connected to needed power circuits.

11. The method for eliminating EMI according to claim 10, wherein the timing control chip receives the display data by using a front-end system.

12. The method for eliminating EMI according to claim 10, wherein a formula of generating the new output clock frequency by the frequency divider units is: the new output clock frequency=1/N multiplied by the input clock frequency, wherein N is an integer.

13. The method for eliminating EMI according to claim 10, wherein the frequency divider units have at least one frequency dividing multiple.

14. The method for eliminating EMI according to claim 10, wherein the selector unit is electrically connected to at least four different power circuits.

15. The method for eliminating EMI according to claim 10, wherein a power control chip is separately electrically connected to the phase-locked loop module and the timing control chip.

16. The method for eliminating EMI according to claim 15, wherein the power control chip is configured to control a power source to be supplied to the phase-locked loop module and the timing control chip.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1a is a schematic diagram of an exemplary power chip control architecture;

[0019] FIG. 1b is a schematic diagram of another exemplary power chip control architecture;

[0020] FIG. 2 is a block diagram of a device for eliminating EMI according to an embodiment of this application;

[0021] FIG. 3 is a block diagram of a phase-locked loop module according to an embodiment of this application; and

[0022] FIG. 4 is a flowchart of a phase-locked loop module according to an embodiment of this application.

DETAILED DESCRIPTION

[0023] The following embodiments are described with reference to the accompanying drawings, used to exemplify specific embodiments for implementation of this application. Terms about directions mentioned in this application, such as on, below, front, back, left, right, in, out, and side surface merely refer to directions in the accompanying drawings. Therefore, the used terms about directions are used to describe and understand this application, and are not intended to limit this application.

[0024] In the embodiments of this application, to help explain the method of this application, it is assumed to perform the method of this application by using a device for eliminating EMI. However, it should be understood that the device and/or the method may change and do not need to be mutually associated and work completely according to the following descriptions. These changes all fall within the scope of the current embodiments. It can be understood that in some embodiments, the processing method of this application may be implemented in a device for eliminating EMI, for example, by running a drive chip. It should be emphasized that unless otherwise stated, the foregoing method of this application does not need to be performed according to a definite sequence shown in the figure. Moreover, a plurality of similar blocks may be performed in parallel, instead of being performed according to a sequence. Therefore, elements in the foregoing methods of this application are referred to as blocks rather than steps in this specification. It should further be understood that, the foregoing method may also be implemented on variations of a device for eliminating EMI. It may be further understood that the method of this application may be implemented in a processing system. However, the foregoing method may also be implemented in a similar system that has similar components with the foregoing system but is disposed in a configuration different from that of the foregoing system.

[0025] The accompanying drawings and the description are considered to be essentially exemplary, rather than limitative. In the figures, modules with similar structures are represented by using the same reference number. In addition, for understanding and ease of description, the size and the thickness of each component shown in the accompanying drawings are arbitrarily shown, but this application is not limited thereto.

[0026] In the accompanying drawings, for clarity, thicknesses of a layer, a film, a panel, an area, and the like are enlarged. In the accompanying drawings, for understanding and ease of description, thicknesses of some layers and areas are enlarged. It should be understood that when a component such as a layer, a film, an area, or a base is described to be on another component, the component may be directly on the another component, or there may be an intermediate component.

[0027] In addition, throughout this specification, unless otherwise explicitly described to have an opposite meaning, the word include is understood as including the component, but not excluding any other component. In addition, throughout this specification, on means that one is located above or below a target component and does not necessarily mean that one is located on the top based on a gravity direction.

[0028] To further describe the technical means used in this application to achieve the application objective and effects thereof, specific implementations, structures, features, and effects of a device and a method for eliminating EMI that are provided according to this application are described in detail below with reference to the drawings and preferred embodiments.

[0029] FIG. 1a is a schematic diagram of an exemplary power chip control architecture; FIG. 1b is a schematic diagram of another exemplary power chip control architecture. Referring to FIG. 1a and FIG. 1b, an integrated power chip 100 includes a plurality of power sources of 3.3 V, 15.6 V, 33 V, and 6 V. The plurality of power sources shares a same input clock cycle (CLK) (a frequency of a CLK shown in FIG. 1b is Fs). In this way, radiation energy of the plurality of power sources on a frequency channel number of the input clock cycle CLK is centralized, and consequently EMI radiation exceeds a given standard.

[0030] FIG. 2 is a block diagram of a device for eliminating EMI according to an embodiment of this application; FIG. 3 is a block diagram of a phase-locked loop module according to an embodiment of this application. Referring to FIG. 2 and FIG. 3, in an embodiment of this application, a device 200 for eliminating EMI includes: a timing control chip 205; and a phase-locked loop module 300, electrically connected to the timing control chip 205 and including: a phase detection unit 310, configured to detect a frequency generated by a clock cycle to generate a frequency difference; a charge pump unit 320, configured to generate a regulation voltage; a voltage-controlled oscillator unit 330, configured to control an oscillation frequency when the regulation voltage is input; a plurality of frequency divider units 350, 351, 352, and 353, configured to generate a new output clock frequency by using an input clock frequency; and a selector unit 340, configured to select the appropriate frequency divider units 350, 351, 352, and 353, where the selector unit has another end electrically connected to needed power circuits.

[0031] Referring to FIG. 2 and FIG. 3, in an embodiment, the timing control chip 205 receives one piece of display data by using a front-end system 202.

[0032] Referring to FIG. 2 and FIG. 3, in an embodiment, after processing the display data, the timing control chip 205 outputs a data signal and a clock cycle signal.

[0033] Referring to FIG. 2 and FIG. 3, in an embodiment, a formula of generating the new output clock frequency by the frequency divider units 350 is: the new output clock frequency (f)=1/N multiplied by the input clock frequency (Fs), where N is an integer.

[0034] Referring to FIG. 2 and FIG. 3, in an embodiment, the frequency divider units 350, 351, 352, and 353 have at least one frequency dividing multiple.

[0035] Referring to FIG. 2 and FIG. 3, in an embodiment, the device further includes a power control chip (not shown in the figure), separately electrically connected to the phase-locked loop module 300 and the timing control chip 205 and configured to control a power source to be supplied to the phase-locked loop module 300 and the timing control chip 205.

[0036] Referring to FIG. 2 and FIG. 3, in an embodiment, a device 200 for eliminating EMI includes: a timing control chip 205; and a phase-locked loop module 300, electrically connected to the timing control chip 205 and including: a phase detection unit 310, configured to detect a frequency generated by a clock cycle to generate a frequency difference; a charge pump unit 320, configured to generate a regulation voltage; a voltage-controlled oscillator unit 330, configured to control an oscillation frequency when the regulation voltage is input; a plurality of frequency divider units 350, 351, 352, and 353, configured to generate a new output clock frequency by using an input clock frequency; and a selector unit 340, configured to select the appropriate frequency divider units 350, 351, 352, and 353, where the selector unit has another end electrically connected to needed power circuits, where the frequency divider units 350, 351, 352, and 353 have at least one frequency dividing multiple, and the selector unit 340 is electrically connected to at least four different power circuits.

[0037] Referring to FIG. 2 and FIG. 3, in an embodiment, four frequency dividing multiples are respectively M, N, X, and Y, and to share a same phase-locked loop module, a selector needs to be used for time division to perform different selections. If a frequency dividing multiple needed by a 3.3 V power circuit is M, and a frequency dividing multiple needed by a 6 V circuit is N, the selector unit 340 controls to select to connect to the 1/M frequency divider unit 350 at a first moment, and an output of a clock frequency (CLK_S) connects to a clock circuit of a 3.3 V power source. Then, at a next moment, the selector unit 340 connects to the 1/N frequency divider unit 351, and an output of the clock frequency (CLK_S) connects to a clock circuit of a 6 V power source. Sequential and cyclical connections are performed in this way, so that time-division multiplexing of the same phase-locked loop module 300 is implemented.

[0038] FIG. 4 is a flowchart of a phase-locked loop module according to an embodiment of this application. Referring to FIG. 2, FIG. 3, and FIG. 4, in an embodiment of this application, a method for eliminating EMI includes: receiving, by a timing control chip 205, one piece of display data, and outputting a data signal and a clock cycle signal after processing the display data; and electrically connecting, by a phase-locked loop module 300, to the timing control chip 205, including: detecting, by a phase detection unit 310, a frequency generated by a clock cycle to generate a frequency difference; generating, by a charge pump unit 320, a regulation voltage when the frequency difference is input; controlling, by a voltage-controlled oscillator unit 330, an oscillation frequency when the regulation voltage is input; generating, by a plurality of frequency divider units 350, 351, 352, and 353, a new output clock frequency by using an input clock frequency; and selecting, by a selector unit 340, the appropriate frequency divider units 350, 351, 352, and 353, where the selector unit has another end electrically connected to needed power circuits.

[0039] Referring to FIG. 2 and FIG. 3, in an embodiment, in the method, the frequency divider units 350, 351, 352, and 353 have at least one frequency dividing multiple.

[0040] Referring to FIG. 2 and FIG. 3, in an embodiment, in the method, a power control chip (not shown in the figure) is further included and separately electrically connected to the phase-locked loop module 300 and the timing control chip 205 and is configured to control a power source to be supplied to the phase-locked loop module 300 and the timing control chip 205.

[0041] Referring to FIG. 3 and FIG. 4, in block S410, a timing control chip receives one piece of display data, and outputs a data signal and a clock cycle signal after processing the display data.

[0042] Referring to FIG. 3 and FIG. 4, in block S420, a phase-locked loop module electrically connects to the timing control chip.

[0043] Referring to FIG. 3 and FIG. 4, in block S430, a phase detection unit detects a frequency generated by a clock cycle to generate a frequency difference.

[0044] Referring to FIG. 3 and FIG. 4, in block S440, a charge pump unit generates a regulation voltage when the frequency difference is input.

[0045] Referring to FIG. 3 and FIG. 4, in block S450, a voltage-controlled oscillator unit controls an oscillation frequency when the regulation voltage is input.

[0046] Referring to FIG. 3 and FIG. 4, in block S460, a plurality of frequency divider units generates a new output clock frequency by using an input clock frequency.

[0047] Referring to FIG. 3 and FIG. 4, in block S470, a selector unit selects the appropriate frequency divider units, where the selector unit has another end electrically connected to needed power circuits.

[0048] In this application, a plurality of different switching frequencies is generated by using a signal frequency of a system output end to drive a power chip, and radiated interference is reduced by decentralizing the switching frequencies. Therefore, a problem of severe radiation of EMI of a power circuit is alleviated.

[0049] The wordings such as in some embodiments and in various embodiments are repeatedly used. The wordings usually refer to different embodiments, but they may also refer to a same embodiment. The words, such as comprise, have, and include, are synonyms, unless other meanings are indicated in the context thereof.

[0050] Descriptions above are merely specific embodiments of this application, and are not intended to limit this application. Although this application has been disclosed above in forms of specific embodiments, the embodiments are not intended to limit this application. A person skilled in the art can make some equivalent variations, alterations or modifications to the above disclosed technical content without departing from the scope of the technical solutions of the above disclosed technical content to obtain equivalent embodiments. Any simple alteration, equivalent change or modification made to the foregoing embodiments according to the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the scope of the technical solutions of this application.