PROGRAMMABLE GAIN AMPLIFIER

Abstract

A programmable gain amplifier may include: (a) a differential amplifier having first and second input terminals and first and second output terminals, the differential amplifier providing an output signal of the programmable gain amplifier across the first and second output terminals of the differential amplifier; (b) a first set of one or more resistors coupling the first output terminal of the differential amplifier to the first input terminal of the differential amplifier; (c) a second set of one or more resistors coupling the first input terminal of the differential amplifier to a first input terminal of the programmable gain amplifier; and (d) a first set of one or more switches each connected in parallel with one or more resistors in the first or second set of resistors. The first set of switches may include two or more individually programmable switches. Each of the switches may be implemented by an input-signal independent switch disclosed herein.

Claims

1. A programmable gain amplifier receiving an input signal across a first input terminal and a second input terminal and providing an output signal, comprising: a differential amplifier having first and second input terminals and first and second output terminals, the differential amplifier providing the output signal across the first and second output terminals of the differential amplifier; a first set of one or more resistors coupling the first output terminal of the differential amplifier to the first input terminal of the differential amplifier; a second set of one or more resistors coupling the first input terminal of the differential amplifier to the first input terminal of the programmable gain amplifier; and a first set of one or more switches each connected in parallel with one or more resistors in the first or second set of resistors, wherein the first set of switches comprise two or more individually programmable switches, in which a first switch is connected in parallel with one or more resistors in the first set of resistors and a second switch is connected in parallel with one or more resistors in the second set of resistors.

2. The programmable gain amplifier of claim 1, further comprising: a third set of one or more resistors, substantially the same as the first set of resistors, coupling the second output terminal of the differential amplifier to the second input terminal of the differential amplifier; a fourth set of resistors, substantially the same as the second set of resistors, coupling the second input terminal of the differential amplifier to the second terminal of the programmable gain amplifier; and a second set of one or more switches each connected in parallel with one or more resistors in the third or fourth set of resistors.

3-4. (canceled)

5. The programmable gain amplifier of claim 1, wherein the ratio of a resistance of the first switch to a resistance of the second switch substantially equals to a gain of the programmable gain amplifier when the first and the second switches are both closed.

6. The programmable gain amplifier of claim 5, wherein the first and second switches have a ratio of their relative sizes substantially equal to the gain.

7. The programmable gain amplifier of claim 1 wherein each switch in the first set of switches is input signal-independent.

8. The programmable gain amplifier of claim 7, wherein each input-signal independent switch has an input terminal and an output terminal, wherein the input signal-independent switch comprises: a transmission gate provided between the input and output terminals of the input signal-independent switch, the transmission gate having a control gate; first and second pass gates, each pass gate having a first terminal and a second terminal, wherein the first terminal of the first pass gate and the first terminal of the second pass gate are both coupled to the control gate of the transmission gate, and wherein the second terminal of the second pass gate is coupled to a ground reference; a level switching circuit; and a unity-gain amplifier serially connected with the level switching circuit, the unity-gain amplifier and the level switching circuit coupling to the input terminal of the input signal-independent switch to the second terminal of the first pass gate.

9. The programmable gain amplifier of claim 7, wherein the level switching circuit provides a bias voltage which is greater than a threshold voltage of the transmission gate.

10. An input signal-independent switch having an input terminal and an output terminal, comprising: a transmission gate provided between the input and output terminals of the input signal-independent switch, the transmission gate having a control gate; first and second pass gates, each pass gate having a first terminal and a second terminal, wherein the first terminal of the first pass gate and the first terminal of the second pass gate are both coupled to the control gate of the transmission gate, and wherein the second terminal of the second pass gate is coupled to a ground reference; a level switching circuit, which provides a bias voltage which is greater than a threshold voltage of the transmission gate; and a unity-gain amplifier serially connected with the level switching circuit, the unity-gain amplifier and the level switching circuit coupling to the input terminal of the input signal-independent switch to the second terminal of the first pass gate.

11. (canceled)

12. The input signal-independent switch of claim 10, wherein the level switching circuit comprises a current source and a resistor of a predetermined resistance.

13. The input signal-independent switch of claim 12, wherein the resistor is implemented by a conducting MOS transistor.

14-17. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1(a) shows convention programmable gain amplifier (PGA) 100.

[0012] FIG. 1(b) shows conventional PGA 150.

[0013] FIG. 2 shows PGA 200, in accordance with one embodiment of the present invention.

[0014] FIG. 3 shows PGA 300, in accordance with one embodiment of the present invention.

[0015] FIG. 4 shows input signal-independent switch 400 which may be used to implement any of the switches in FIGS. 2 and 3, in accordance with one embodiment of the present invention.

[0016] FIG. 5 shows input signal-independent switch 500 which is one implementation of signal-independent switch 400 of FIG. 4, in accordance with one embodiment of the present invention.

[0017] To simplify the detailed description and to allow cross-reference among the figures, like elements in the figures are assigned like reference numerals.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] FIG. 2 shows PGA 200, according to embodiment of the present invention. As shown in FIG. 2, PGA 200 receives differential input voltage V.sub.1 between input terminals 205a and 205b and provides differential output voltage V.sub.2 between output terminals 204a and 204b. In PGA 200, a first set of serially-connected resistors 201-1a, 201-2a, . . . 202-Na, where N is an integer, are provided between input terminal 205a and the non-inverting input terminal of differential amplifier 206. A second set of serially-connected resistors 203-1a, 203-2a, . . . , 203-Ma, where M is an integer, are provided between output terminal 204a and the non-inverting input terminal of differential amplifier 206. Likewise, on the inverting input terminal side of differential amplifier 206, a third set of serially-connected resistors 201-1b, 201-2b, . . . , 202-Nb are provided between input terminal 205b and the inverting input terminal of differential amplifier 206, and a fourth set of serially-connected resistors 203-1b, 203-2b, . . . , 203-Mb are provided between output terminal 204b and the inverting input terminal of differential amplifier 206. In addition, a number of individually controlled switches are provided. These switches, when closed, provide current paths that are in parallel with corresponding groups of resistors.

[0019] As shown in FIG. 2, switches 202-1a, 202-2a, . . . , 202-Na are each provided to provide parallel current paths to a group of one or more resistors. Specifically, switch 202-1a provides a current path parallel to resistor 201-1a, switch 202-2a provides a current path that is parallel to serially connected resistors 201-1a and 201-2a, . . . , and switch 202-Na provides a current path that is parallel to serially connected resistors 201-1a, 201-2a, . . . , 201-Na. Similarly, (i) switch 202-1b provides a current path that is parallel to resistor 201-1b, switch 202-2b provides a current path that is parallel to serially connected resistors 201-1b and 201-Nb, . . . , and switch 202-Nb provides a current path that is parallel to serially connected resistors 201-1b, 201-2b, . . . , 201-Nb; (ii) switch 204-1a provides a current path that is parallel to resistor 203-1a, switch 204-2a provides a current path that is parallel to serially connected resistors 203-1a and 203-2a, . . . , and switch 204-Ma provides a current path that is parallel to serially connected resistors 203-1a, 203-2a, . . . , 203-Ma; and (iii) switch 204-1b provides a current path that is parallel to resistor 203-1b, switch 204-2b provides a current path that is parallel to serially connected resistors 203-1b and 203-2b, . . . , and switch 204-Mb provides a current path that is parallel to serially connected resistors 203-1b, 203-2b, . . . , 203-Mb. By closing selected switches, different resistance values may be achieved for different gain values.

[0020] In FIG. 2, the first set of resistors 201-1a, 201-2a, . . . , 201-Na may each have the same resistance value as its counterpart in the third set of resistors 201-1b, 201-2b, . . . , 201-Nb. Similarly, the second set of resistors 203-1a, 203-2a, . . . , 203-Ma may each have the same resistance value as its counterpart in the fourth set of resistors 203-1b, 203-2b, . . . , 203-Mb. Under that arrangement, when switches 202-na, 202-nb, 204-ka and 204-kb are closed, 1nN and 1kM, for relatively small switch resistances, the gain is given by:

[00003]$\frac{V_2}{V_1}=\frac{{}_{j=k}^M.Math.R_{\mathrm{jG}}+R_{\mathrm{SG}}}{{}_{i=n}^N.Math.R_i+R_S}$

where R.sub.jG is the resistance of resistor 203-ja or resistor 203-jb, R.sub.i is the resistance of resistor 201-ia or resistor 201-ib, R.sub.S is the resistance of any of switches 202-1a, 202-2a, . . . , 202-Na or switches 202-1b, 202-2b, . . . , 202-Nb, and R.sub.SG is the resistance of any of switches 204-1a, 204-2a, . . . , 204-Ma or switches 204-1b, 204-2b, . . . , 204-Mb. (The relatively small switch resistance assumption corresponds to R.sub.S<<.sub.i=1.sup.n-1R.sub.i and R.sub.SG<<.sub.j=1.sup.k-1R.sub.jG.)

[0021] If the resistance ratio between the corresponding closed switches are selected to be close to the expected gain G

[00004]$\left(i.e.,\frac{R_{\mathrm{SG}}}{R_S}\frac{{}_{j=k}^M.Math.R_{\mathrm{jG}}}{{}_{i=n}^N.Math.R_i}G\right),$

the resulting gain becomes independent of the resistance values of the switches. In the case that the switches are implemented by MOS transistors, the resistance value ratio may be achieved by selecting suitable sizes between the corresponding switches. That is, for example, for switches implemented using MOS transistors of the same channel lengths,

[00005]$\frac{R_{\mathrm{SG}}}{R_S}G$

may be achieved by selecting switch 204-ka to have a channel width (W) that is G times wider than the channel width of switch 202-na.

[0022] When the switch resistances at least comparable to the resistors shunted (i.e., the conditions R.sub.S<<.sub.i=1.sup.n-1R.sub.i and R.sub.SG<<.sub.j=1.sup.k-1R.sub.jG do not hold), the gain would be given by

[00006]$\frac{V_2}{V_1}=\frac{{}_{j=k}^M.Math.R_{\mathrm{jG}}+R_{\mathrm{SG}}^{}}{{}_{i=n}^N.Math.R_i+R_S^{}},$

where R.sub.SG and R.sub.S are, respectively, the resistance value of the parallel circuit formed by switch 204-(n1)a and resistors 203-1a, . . . , 203-(n1)a and the resistance value of the parallel circuit formed by switch 202-ka and resistors 203-1a, . . . , 203-(k1)a:

[00007]$R_{\mathrm{SG}}^{}=\frac{R_{\mathrm{SG}}\left({}_{j=k}^M.Math.R_{\mathrm{jG}}\right)}{R_{\mathrm{SG}}+{}_{j=k}^M.Math.R_{\mathrm{jG}}}$$R_S^{}=\frac{R_S\left({}_{i=n}^N.Math.R_i\right)}{R_S+{}_{i=k}^N.Math.R_i}$

[0023] Again suitable relating sizing of the switches, e.g.,

[00008]$\frac{R_{\mathrm{SG}}^{}}{R_S^{}}G,$

allows me gam of PGA 100 to become independent of switch resistance.

[0024] FIG. 3 shows PGA 300, in accordance with one embodiment of the present invention. As shown in FIG. 3, PGA 300 receives differential input voltage V.sub.1 across input terminals 306a and 306b and provides differential output voltage V.sub.2 across output terminals 307a and 307b. PGA 300 includes differential amplifiers 301a and 301b, first and second resistors 302a and 302b, a first set of serially-connected resistors 303-21a, 303-2a, . . . , 303-Na and a second set of serially connected 303-1b, 303-2b, . . . , 303-Nb. Resistors 302a and 302b. shown in FIG. 3 as each having a resistance R.sub.2, may each be provided a parallel current path by a corresponding one of switches 304a and 304b. In one embodiment, the two set of serially-connected resistors are provided such that each resistor in one set has a counterpart resistor of equal resistance in the other set. Further, resistors 303-1a, 303-2a, . . . , 303-Na may each be provided a parallel current path by a corresponding one of switches 305-1a, 305-2a, . . . , 303-Na. Likewise, resistors 303-1b, 303-2b, . . . , 303-Nb may each be provided a parallel current path by a corresponding one of switches 305-1b, 305-2b, . . . , 303-Nb. In FIG. 3, the total resistance of the serially-connected sets of resistors is R.sub.1.

[0025] The gain of PGA 500 is set by providing parallel current paths to selected resistors (i.e., by closing the selected corresponding switches). Thus, for a relatively small switch resistance, the gain is given by:

[00009]$\frac{V_2}{V_1}=1+\frac{2.Math.R_2}{{}_{j.Math..Math.\mathrm{open}}.Math.R_j}$

where R.sub.j is the resistance of resistor 303-ja or resistor 303-jb, where the sum is over all resistors that are not provided parallel current paths. In this regard, the relatively small switch resistance means that the resistance R.sub.Sj of closed switch 304-ja or switch 304-jb is much less than the corresponding resistance of resistor 303-ja or resistor 303-jb. However, if the assumption of relative small switch resistance does not hold (i.e., the resistance R.sub.Sj of closed switch 304-ja or switch 304-jb is not much less than the corresponding resistance of resistor 303-ja or resistor 303-jb), then the gain is given by:

[00010]$\frac{V_2}{V_1}=1+\frac{2.Math.R_2}{{}_{j.Math..Math.\mathrm{closed}}.Math.R_{\mathrm{Sj}}^{}+{}_{\mathrm{open}}.Math.R_j}$

where R.sub.Sj is the resistance of the parallel circuit that includes closed switch 305-ja or 305-jb and resistor 303-ja or 303-jb.

[0026] As discussed above, the switches in FIGS. 2 and 3 may be implemented as pass gates (or transmission gates) using MOS transistors. Note that the resistance (RDS-on) of a conducting pass gate (i.e., a closed MOS transistor switch) is given by:

[00011]${\mathrm{RDS}}_{\mathrm{on}}=\frac{1}{.Math.\frac{W}{L}.Math.\left(V_{\mathrm{GS}}-V_T\right)}$

where is a proportionality constant, W and L are respectively the channel width and the channel length of the MOS transistor, V.sub.GS and V.sub.T are respectively the gate-to-source voltage and the threshold voltage of the MOS transistor. In a pass gate configuration, V.sub.GS=V.sub.GV.sub.IN where V.sub.G is the voltage at the gate electrode and V.sub.IN is the input voltage to the pass gate. Therefore, when implementing the switches in FIGS. 2 and 3 by pass gates, their resistance values would depend on input signal V.sub.IN, which may not desirable in many applications. The present invention provides a switch that has an input signal-independent resistance value.

[0027] FIG. 4 shows input signal-independent switch 400 which may be used to implement any of the switches in FIGS. 2 and 3, in accordance with one embodiment of the present invention. As shown in FIG. 4, switch 400 includes amplifier 401 in a unity-gain configuration, which provides input signal V.sub.IN at terminal 405 to output terminal 407 of amplifier 401. Level shifting circuit 402 (represented by voltage source 402 in FIG. 4) adds additional voltage V.sub.bias to the voltage at terminal 407. Switch 400 includes switches 403 and 404, which may each be implemented by a pass gate. Switch 403 is closed when switch 404 is open, and vice versa. When switch 404 is closed, the common ground voltage is provided to the gate electrode of MOS transistor 509, thereby blocking input signal V.sub.IN from reaching output terminal 406. In such condition, input signal-independent switch 400 serves an open switch.

[0028] Alternatively, when switch 403 is conducting (i.e., switch 403 is closed), the output voltage of level-shifting circuit 402 (minus a voltage drop across switch 403) is provided to the gate terminal of MOS transistor 409 (i.e., V.sub.G=V.sub.1N+V.sub.bias). Additional voltage V.sub.bias is selected to be greater than the threshold voltage of MOS transistor 409, so that, regardless of the value V.sub.IN, MOS transistor 409 is conducting. Thus, when the switch 403 is conducting, input signal-independent switch 400 serves as a closed switch. In this configuration, the effective resistance RDS.sub.ON of switch 400 is given by:

[00012]${\mathrm{RDS}}_{\mathrm{on}}=\frac{1}{.Math.\frac{W}{L}.Math.\left(V_{\mathrm{GS}}-V_T\right)}=\frac{1}{.Math.\frac{W}{L}.Math.\left(V_{\mathrm{IN}}+V_{\mathrm{bias}}-V_{\mathrm{IN}}-V_T\right)}=\frac{1}{.Math.\frac{W}{L}.Math.\left(V_{\mathrm{bias}}-V_T\right)}$

[0029] Accordingly, input signal-independent switch 400 has an on resistance value that is independent of the input voltage.

[0030] FIG. 5 shows input signal-independent switch 500 which is one implementation of signal-independent switch 400 of FIG. 4, in accordance with one embodiment of the present invention. In FIG. 5, level switching circuit 402 is implemented by current source 501 and resistor 502. Resistor 502 may be implemented by the on-resistance (RDS-on) of a suitably-biased conducting MOS resistor of a predetermined size.

[0031] The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Various modifications and variations within the scope of the present invention are possible. The present invention is set forth in the accompanying claims.