Visual display unit for processing a double input signal

Abstract

An electroluminescent visual display unit having: a matrix of electroluminescent pixels formed from pixels arranged on a substrate, in a matrix arrangement in lines and columns, each pixel being formed by an elementary emitting zone; a first control block to control a graphic and/or alphanumeric data stream that can be displayed on the matrix of pixels; a second control block to control a video data stream that can be displayed on the matrix of pixels; and a unit for generating a reference voltage, the device being characterized in that: each elementary emitting zone is connected to a static memory, addressed by the first control block, and to a dynamic memory, addressed by the second control block; the first and second control blocks for displaying data alternately or simultaneously on the same matrix of pixels.

Claims

1. An electroluminescent display unit comprising: a matrix of electroluminescent pixels formed from a plurality of pixels arranged on a substrate, according to a matrix arrangement in lines and columns, each pixel being formed by at least one elementary emitting zone each elementary emitting zone being connected to a static memory and a dynamic memory; a first control block configured to control a graphic and/or alphanumeric data stream that can be displayed on said matrix of pixels; a second control block configured to control a video data stream that can be displayed on said matrix of pixels, said video data stream being refreshed periodically, wherein second control block and said refresh of said video data stream are controlled by a clock; a unit for generating a reference voltage, knowing that said data stream may be static and reprogramed as required, or refreshed periodically with a refresh frequency independent from same of said video data stream, wherein each elementary emitting zone is connected to a static memory, addressed by said first control block, and to a dynamic memory, addressed by said second control block; wherein said first and second control blocks are configured to be able to display data alternately or simultaneously on the same matrix of pixels; wherein each elementary emitting zone is connected to a static memory intended for graphic and/or alphanumeric data; and wherein said static memory controls a gate of a transistor, said transistor defining a current in an organic light-emitting diode (OLED) element using a reference voltage.

2. The unit according to claim 1, wherein said first and second control blocks are configured to be able to display on the matrix of pixels only the video data stream, or only the graphic and/or alphanumeric data stream, or even to overlay said graphic and/or alphanumeric data stream on said video data stream.

3. The unit according to claim 1, wherein said dynamic memory to which each elementary emitting zone is connected is a capacity.

4. The unit according to claim 1, wherein said first control block is configured to allow a refreshing of an image by sending new data only when a content of said static memory changes following a saving of new data in said static memory.

5. The unit according to claim 1, wherein said first control block is configured to send: towards an addressing table that controls the addressing of the static memories of the matrix of electroluminescent pixels: a graphic and/or alphanumeric data signal, a horizontal addressing signal; towards a line driving element an addressing signal that controls the addressing of the lines of the electroluminescent display unit, for the display of said graphic and/or alphanumeric data on said matrix of electroluminescent pixels.

6. The unit according to claim 1, wherein said second control block is configured to send: a video data stream towards a horizontal shift register that controls the addressing of the columns of the matrix of electroluminescent pixels, a control signal towards a line driving element that controls the addressing of the lines of the matrix of electroluminescent pixels, for the display of said video data stream on said matrix of electroluminescent pixels.

7. The unit according to claim 1, wherein said first and second control blocks are configured so that said first block has a number of bits of emission intensity levels higher than same of said second control block.

8. The unit according to claim 1, wherein said first control block is configured on at least eight bits of emission intensity levels, and/or said second control block is configured on two to six bits of emission intensity levels.

9. The unit according to claim 1, wherein said first control block has a refresh rate higher than same of said second control block.

10. The unit according to claim 1, wherein said first control block has a refresh rate higher than or equal to 25 Hz, and/or in that said second control block includes a memory unit for storing said graphic and/or alphanumeric data for a static display.

11. The unit according to claim 10, wherein said first control block has a refresh rate higher than or equal to 60 Hz.

12. The unit according to claim 10, wherein said first control block has a refresh rate of at least 90 Hz.

13. The unit according to claim 1, wherein said second control block has a refresh rate between 0 Hz and 10 Hz.

14. The unit according to claim 13, wherein said second control block has a refresh rate between 0.1 Hz and 1 Hz.

15. The unit according to claim 1, wherein each elementary emitting zone is connected to a plurality of static memories.

16. The unit according to claim 1, wherein said static memory is of a static random access memory (SRAM), or a register type.

Description

DESCRIPTION OF THE FIGURES

(1) The invention will be described hereafter, with reference to the appended drawings, given only by way of non-limiting examples, wherein:

(2) FIG. 1 is a general view of the architecture of the display element illustrating an installation for the display of a video stream and/or of graphic data.

(3) FIG. 2a is a general view of the architecture of the display element illustrating an installation for the display of a video stream.

(4) FIG. 2b is a general view of the architecture of the display element illustrating an installation for the display of graphic data.

(5) FIG. 3 is a representation of the wiring diagram of a sub-pixel for the first embodiment.

(6) FIG. 4 is a representation of the wiring diagram of a sub-pixel for the second embodiment.

(7) FIG. 5 is a representation of the wiring diagram of a sub-pixel for the third embodiment.

(8) FIG. 6 is a timing chart of control signals of the emission time applied to inputs S1 to S4 of the pixel circuits.

(9) FIG. 7 is a representation of the wiring diagram of a sub-pixel having an alternative embodiment.

(10) The following numerical references are used in the present description

(11) TABLE-US-00001 1 Installation 2 First control according to the block invention 3 Second control block 4 Reference voltage (management of the generation unit video stream) 31 Video stream 32 Command signal 33 Sequencer 34 Horizontal shift register 35 Digital comparator 36 Sampling and 37 Vertical shift maintenance register circuit 38 Matrix of pixels 41 Counter module 42 Look-up table 43 Current source 44 Reference voltage 45 Signal from 41 generator 47 Reference voltage output from 44 121 Serial data bus 122 Decoder module 123 Signal processor 131 Data signal 132 Horizontal 133 Horizontal addressing table addressing signal 134 Vertical addressing signal 137 Vertical addressing 145 PWM signal table generator 146 Control signals 147 Reference voltages 200 Electric circuit of 205 Transistor a sub-pixel 210 Capacitor 215, 220 Transistor 235, 240, Transistor 245, 250 270 Dynamic portion of 255, 260 Static memory the circuit 200 (SRAM or register) 280 Static portion of the circuit 200 300 Installation 290 Sub-pixel according to the invention 310 Capacitor 305 Transistor 325 OLED element 315, 320 Transistor 355, 360 Static memory (SRAM 345, 350 Transistor cell or register) 370 Dynamic portion of the circuit 200 380 Static portion of 390 Sub-pixel the circuit 300 400 Installation 405, 415 Transistors according to the invention 410 Capacitor 420, 435 Transistor 425 OLED element Transistor 470 Dynamic portion of 440, 445 the circuit 400 450, 455, 460 480 Static portion of 441, 446, Static memory the circuit 400 451, 456 (SRAM or register) 490 Sub-pixel 500 Installation 505 Static memory according to the (SRAM or register) invention

DETAILED DESCRIPTION

(12) FIG. 1 relates to two different display modes that are implemented on a single matrix of electroluminescent elementary emitting zones, which bears the reference 38 in FIG. 1. In particular, it may concern a matrix of pixels of OLED type, and the present description refers to this case, knowing that the present invention also applies to a matrix of electroluminescent pixels using inorganic semiconductors or light-emitting diodes (LED). For a matrix of pixels of a monochrome electroluminescent screen, each elementary emitting zone in general corresponds to a pixel; for a color screen each pixel breaks down into a plurality of individual addressing sub-pixels, and said sub-pixels then correspond to elementary emitting zones.

(13) FIG. 1 describes a general view of the architecture of an installation 1 according to the invention that is provided with two separate image channels, namely a channel referred to as video (with an incoming stream of digital data) and a channel of data referred to as graphic (with an incoming stream of digital data). Said two channels are connected in the pixel only; each of the video and graphic channels have their own addressing system and a distinct wiring at the elementary emitting zone. Said architecture is designed to control each elementary emitting zone (i.e. each OLED sub-pixel) in steady current, but same may also be applied to a voltage control, by means of minor modifications (not shown in the figures). In the video channel, for each elementary emitting zone the incoming digital video signal is converted into an analog signal corresponding to the gray levels thanks to a system that comprises a counter, a current source, a reference voltage generator, and optionally a correction table, associated with comparators at the columns. The analog video signal thus obtained is temporarily stored in a dynamic memory associated with the elementary emitting zone. The graphic data channel addresses a direct-access digital live memory matrix of SRAM type via a writing procedure (and optionally also reading) for said type of memory.

(14) More specifically, the video block of the unit comprises a counter (for example eight bits) and a comparator at the end of each column that compares the values of the counter with the video data. At the same time, the counter supplies a system of weighted current sources (namely a reference voltage generator). When the values of the counter and of the video data are equal, the reference voltage of the generator is firstly transferred into the buffer memory of the column, and subsequently during the following cycle into the elementary emitting zone, via the column. Between the counter and the reference voltage generator, there may be a conversion table for applying a non-linear correction (gamma factor); in this case it may be useful to have a greater number of bits in the reference voltage generator.

(15) The reference voltage generator generates a voltage that introduces into the elementary emitting zone a current proportional to the value applied to the input.

(16) FIG. 2a shows the circuit of the video channel for the display of a video stream 31 on the matrix of electroluminescent pixels 38. This figures shows a first block known as control block 2 that will not be used in said display mode and whereof the operation will be explained below in relation with the second display mode. A second block 3 makes it possible to manage the video stream 31 up to the display thereof on the matrix of pixels 38. Said video stream 31, which is a digital data stream, is sent towards a horizontal shift register demultiplexer 34 then towards a digital comparator 35 (that generates an analog data stream) then towards a sampling and maintenance circuit 36 and finally towards the vertical gates of the matrix of pixels 38. In said second block 3, a control signal 32 is sent to a sequencer 33 that makes it possible to supply a line driving element 37 (typically a vertical shift register or a demultiplexer) that gives the orders on the horizontal lines of the matrix of pixels 38.

(17) A reference voltage generation unit 4 generates the reference voltage. Same comprises a counter module with eight bits 41 that sends a signal 45 to a Look-Up Table 42 (known under the acronym “LUT”), optional but recommended, which makes non-linear encoding possible. The value coming from the look-up table 42 is transmitted towards a reference voltage generator 44 coded on ten bits. Said latter comprises another input for providing a current source 43 weighted on ten bits. The output reference voltage 47 of the voltage generator 44 supplies the sampling and maintenance circuit 36 of the second control block 3.

(18) The operation related to FIG. 1 is based on a digital video data stream 31 that is converted by a digital comparator assembly 35, counter 41, look-up table 42 (optional) and reference voltage generator 44 into an analog signal at the end of each column and transmitted to the matrix of pixels 38. Said stream type requires rapid processing for an instantaneous display. The video stream 31 is broken down by the demultiplexer 34 in order to address to each pixel of the matrix of pixels 38 the information to be displayed. The sequencer 33 transmits to the vertical shift register 37 the order for displaying the information on each pixel. Said order is based on a control signal 32 that may be of the type: Pixel Clock (PCLK): the pixel clock changes on each pixel. Horizontal synchronization (HSYNC): This is a special signal that indicates that a line of the frame is transmitted. Vertical synchronization (VSYNC): Said signal is transmitted after the transfer of the entire frame. Said signal is often a means for indicating that an entire frame is transmitted.

(19) FIG. 2b is a general view of the architecture illustrating an installation 1 for displaying graphic data on said matrix of electroluminescent pixels 38. Said architecture comprises a first control block 2, mentioned above, which comprises a serial data bus 121 transmitted towards a module 122 capable of decoding the signals and of sending same towards a signal processor 123 for decoding the signals and for sending same towards the static memories of the matrix of pixels 38, in a known manner and used in the memory circuits. Said signal processor 137 is a control unit that generates the signal of the lines and columns for the first control block 2. This may concern a signal generator or a microcontroller or also, for more complex systems, a microprocessor.

(20) Here, we describe, for a particular embodiment, the display of said graphic and/or alphanumeric data 131 on the matrix of electroluminescent pixels 38. The first control block 2 sends the graphic and/or alphanumeric data signal 131 towards the addressing table 132 of the second control block 3. The addressing table 132 is a horizontal addressing table that controls the addressing of the columns of the matrix of electroluminescent pixels 38; same receives the horizontal addressing signal 133. The second control block 3 moreover comprises a line driving element 137 (vertical addressing table) that receives the vertical addressing signal 134 that controls the addressing of the lines of the electroluminescent display unit 38. The matrix of pixels 38 moreover receives a reference voltage coming from a unit 4 referred to as the reference voltage generation unit. Said last unit 4 comprises a reference voltage generator 44, a current source module 43 and, optionally, a Pulse Width Modulation referred to as PWM signal generator 145.

(21) The operation related to FIG. 2b results in a digital processing in a slow display process and implementing at the pixel a SRAM type memory. The information is broken down in the first control block 2, all of the information, data 131 and addressing 133,134, makes it possible to display the graphic data on the matrix of pixels 38. The reference voltages 147 (here V.sub.ref, V.sub.ref1 and V.sub.ref2) are generated by a reference voltage generator 44. Same define the value of the current or of the output voltage of the transistors whereof same drive the gate, and therefore of the current or of the voltage on the matrix of pixels 38. The reference voltages are therefore common to the matrix of electroluminescent pixels and give continuous signals in order to define the gray levels. Specifically, said voltages make it possible at each pixel to maintain the supply and the comparison on the values saved in the memory.

(22) FIGS. 1, 2a and 2b correspond to implementation modes for a dynamic or static display that are distinguished by the management thereof of the data streams thus by the refresh frequency of the information displayed on the matrix of pixels. The architecture of the unit according to the invention brings together said two functions on the same matrix of pixels 38.

(23) The architecture of the matrix of pixels 38 comprises a plurality of pixels aligned horizontally and vertically. In this embodiment, each pixel comprises four sub-pixels as elementary emitting zones; said sub-pixels may mainly be the red, the green and the blue, whereas the fourth sub-pixel may be a complement in white or any other color. Obviously, only three sub-pixels per pixel may be provided for, or even it may be provided for that each pixel is formed from only one elementary emitting zone.

(24) As indicated above, each elementary electroluminescent emitting zone has two independent memories: a static memory, intended for graphic data, and a dynamic memory, intended for data from the video stream. FIGS. 3, 4, 5 and 7 show embodiments of circuits at an elementary electroluminescent emitting zone, whereof the structure and the operation, in particular in relation with the static or dynamic type memory units, will be explained in greater detail below.

(25) FIG. 3 shows the wiring diagram 200 of only one elementary emitting zone 290 (that may be a sub-pixel) according to a first embodiment. The circuit comprises three portions, one for the dynamic portion 270, another for the static portion 280, and the display on the sub-pixel 290.

(26) The dynamic portion 270 of the circuit comprises the arrival of the analog video stream 31 and of a selection voltage 47 from the sequencer 33 on the gate of a transistor SW1 205. The cathode of the transistor 205 supplies a capacitor 210 as well as the gate of a transistor T.sub.ANA1 215. The anode of the transistor T.sub.ANA1 215 is connected to a voltage V.sub.ANA. The cathode of the transistor T.sub.ANA1 215 is connected to the display sub-pixel 290. Said sub-pixel consists of a transistor SW2 220 connected to an OLED element 225. The transistor SW2 220 is itself also optional and makes it possible for example to modulate the emission of the OLED element 225.

(27) The static portion 280 of the circuit (circled in FIG. 3 by a dotted line), intended for the display of graphic data, consists of a transistor T.sub.ANA2 235 in series with a transistor SW3 245 in parallel with a transistor T.sub.ANA3 240, said latter in series with a transistor SW4 250. The anodes of T.sub.ANA2 235 and T.sub.ANA3 240 are connected to the anode of T.sub.ANA1 215 and the cathodes of SW3 245 and SW4 250 are connected to the cathode of SW2 220 or of T.sub.ANA1 215 (when SW2 is optional). Each of the gates of T.sub.ANA2 235 and T.sub.ANA3 240 is connected to the reference voltage V.sub.ref 147. Each of the gates of the two transistors SW3 245 and SW4 250 is controlled by a SRAM cell type memory function 255,260. The memory cell is typically of six transistors type. On the diagram, only the BL (“Bit line”) and WL (“Word Line”) inputs, which are respectively supplied by the line addressing signal 134 (vertical addressing signal) and the data line 131, are used. The programming of the memory is carried out by establishing a digital signal, ‘0’ or ‘1’ on the BL column and the opposite digital signal thereof ‘1’ or ‘0’ on the BLB (“Bit Line Bar”) column of each SRAM cell. Subsequently, a pulsed signal, in general positive, on the WL (“Word Line”) signal comes to save the BL and BLB signals in the memory of the SRAM type cell.

(28) The circuit according to FIG. 3 may be used in three different ways. The first usage is the video mode, which essentially involves the dynamic portion 270, that is to say the memory is set at level 0 everywhere in the matrix, and data is transmitted by the video interface only; in other words the pixel is only controlled by the video data channel. A video stream 31 supplies the anode of SW1 205. The transistor becomes conducting only when the voltage V.sub.select permits same to switch on the display sub-pixel 290. The capacitor CS 210 is optional but highly recommended: same makes it possible to limit the overload as well as the maintenance of the voltage during a time lapse on the supply to the terminals of T.sub.ANA1 215; thus same acts as dynamic memory. This will only occur in the case where said capacitor 210 may be operationally substituted by the carrying capacity of the transistor T.sub.ANA1 215, in particular in the case where the refresh frequency of the video stream is sufficiently high. The static portion 280 not being supplied in said video operating mode, no current circulates in said portion.

(29) The second usage is the graphic mode that essentially involves the static portion 280. The memory function of the SRAM cells 245,250 makes it possible to maintain open or closed the transistors SW3 245 and SW4 250. The controlled openings of SW3 245 and SW4 250 enable the passage of the reference voltage V.sub.ref 147 up to the OLED element 225. The assembly of T.sub.ANA2 235 and T.sub.ANA3 240 in parallel has the function of analog to digital converter on two bits. The converter enables four possible modes as follows:

(30) Mode 00: When the two transistors SW3 245 and SW4 250 are not conducting, the current transiting in the circuit is null, as mentioned previously in the pure dynamic mode.

(31) Mode 01: the transistor SW4 250 is conducting, the relative current is sent to the unit for displaying the sub-pixel 290.

(32) Mode 10: the transistor SW3 245 is conducting, the relative current is sent to the unit for displaying the sub-pixel 290.

(33) Mode 11: the transistors SW3 245 and SW4 250 are conducting, the relative current is sent to the unit for displaying the sub-pixel 290.

(34) The third usage is a mixed mode referred to as overlay: both a video signal by the dynamic channel 270 and a graphic signal by the static portion 280 are applied. The current in the OLED therefore corresponds to the overlay of both signals; the display of the sub-pixel 290 is controlled by the converter formed by T.sub.ANA2 235 in series with SW3 245 and T.sub.ANA3 240 in series with SW4 250 as well as T.sub.ANA1 215.

(35) The diagram shown in FIG. 3 proposes an advantageous embodiment of a display with four levels (two bits) for the graphic portion by using two SRAM type memory cells 255,260; same may comprise additional memory cells (for example 3, 4 or 5 SRAM cells) that will increase the capacity of the analog to digital converter in number of bits and therefore of possible modes.

(36) The architecture shown above is designed to supply the OLED 225 with steady current, however, same may also be applied to a voltage supply by means of minor modifications.

(37) FIG. 4 describes a second embodiment 300 of the arrangement at one of the sub-pixels. The circuit comprises three portions, a first for the dynamic portion 370, a second for the static portion 380, and a third for the display on the sub-pixel 390. The dynamic portion 370 comprises the arrival of the analog video signal 31 on the anode and of a line selection voltage 47 on the gate of a transistor SW1 305. The cathode of the transistor 305 supplies a capacitor 310 (acting as dynamic memory) as well as the gate of another transistor T.sub.ANA 315. The anode of the transistor T.sub.ANA1 315 is connected to a voltage V.sub.ana. The cathode of the transistor T.sub.ANA1 315 is connected to the sub-pixel 390 display. Said latter comprises a transistor SW2 320 (optional) connected to an assembly comprising the OLED element 325.

(38) The static portion 380 (circled in FIG. 4 with a dotted line) consists of two transistors SW3 345 and SW4 350 that are connected by the cathode thereof to same of the transistor SW1 305. The anode of said two transistors is connected each respectively to a reference voltage 147 V.sub.ref1 and V.sub.ref2. Each of the gates of the two transistors SW3 and SW4 is controlled by a memory function of SRAM cell 355,360 type. The memory cell is of 6 transistors or more type. In FIGS. 3, 4, 5 and 7 the BL (“Bit Line”) and WL (“Word Line”) inputs are respectively supplied by the line address 134 and the data line 131.

(39) The output of a SRAM cell 355,360 makes it possible to make the respective transistors 345 and 350 conducting, a predetermined voltage V.sub.ref is applied to the gate of the transistor T.sub.ANA 315 that is the current source for the OLED; there is no need for specific current sources, but it is necessary to provide one SRAM cell per level (and not per bit as in the first embodiment). This is shown in the following table for the case of four current sources: the reference voltages V.sub.ref1 and V.sub.ref2, when the transistors SW3 345 and SW4 350 are conducting, are on the transistor T.sub.ANA:

(40) TABLE-US-00002 level SRAM1 SRAM2 SRAM3 SRAM4 V.sub.gate (T.sub.ANA) 0 0 0 0 0 Video data 1 1 0 0 0 V.sub.Ref1 2 0 1 0 0 V.sub.Ref2 3 0 0 1 0 V.sub.Ref3 4 0 0 0 1 V.sub.Ref4

(41) The circuit according to FIG. 4 may be used in three different ways. According to a first use mode only the dynamic portion 370 of the circuit is used. A video stream 31 supplies the anode of SW1 305. The transistor becomes conducting only when the voltage V.sub.select permits same to switch on the display portion 390. The capacitor CS 310 makes it possible to maintain the voltage during a time lapse on the supply of the gate of T.sub.ANA1 315. The static portion 380 not being supplied, no voltage circulates in said portion. According to a second use mode only the static portion 380 of the circuit is used. The memory function of the SRAM cells 345,350 makes it possible to maintain open or closed the transistors SW3 345 and SW4 350.

(42) According to the number of memory cells present in the circuit, the display portion 390 reacts to the various voltages applied on T.sub.ANA 315, as indicated for example in the table above.

(43) In this use mode, the voltage state of the gate of the transistor T.sub.ANA is not necessarily known and it may be in a case of high impedance, in which case the transistor remains blocked. In order to overcome this problem, the applicant proposes to use a voltage V.sub.select in order to initialize the transistor T.sub.ANA. For this in the case of a graphic mode only, the voltage V.sub.select is not controlled by the sequencer 33 but comes from the reference voltage generation unit 4.

(44) The signal of the voltage V.sub.select makes it possible to reinitialize the transistor T.sub.ANA before each write in the memory cells.

(45) The third use mode is a mixed mode referred to as overlay, which involves both the static portion 280 and the dynamic portion 270 of the circuit. The display of the sub-pixel 290 is controlled by the converter formed by T.sub.ANA 315. In this case, the display portion 390 allows both the video signal 31 and the stream coming from the various memory cells 355,360 to pass through.

(46) As indicated above, here circuits are described wherein the display of the sub-pixels 290 is controlled by the current, but the circuits may be controlled in voltage by means of minor modifications.

(47) FIG. 5 describes the third embodiment 400 of the arrangement of the circuit at one of the sub-pixels, for a particular case with four bits of gray levels. The circuit comprises three portions, a first portion 470 for the dynamic display, a second portion 480 for the static display, and a third for the display on the sub-pixel 490. The dynamic portion 470 comprises the arrival of the analog video signal 31 on the anode of a transistor SW2 405 and of a line selection voltage 47 on the gate of the transistor SW2 405. The cathode of the transistor 405 supplies a capacitor 410 (acting as dynamic memory) as well as the gate of a transistor T.sub.ANA 415. The anode of the transistor T.sub.ANA 415 is connected to a voltage V.sub.ANA. The cathode of the transistor T.sub.ANA 415 is connected to the sub-pixel 490 display. Said latter consists of a transistor SW2 420 connected to the OLED element 425. The static portion 480 (circled in FIG. 5 with a dotted line) consists of a transistor SW1 435 that is connected by the cathode thereof to the gate of the transistor T.sub.ANA415. The anode of the transistor SW1 435 is connected to a reference voltage V.sub.ref 147. The cathode of the transistor SW1 435 is controlled by five signals coming from the anode of transistors 440, 445, 450, 455, 460 arranged in parallel.

(48) In this embodiment and by way of example comprising four bits of gray levels, the four control signals 146, S1, S2, S3, S4 control the gates of the four transistors 440, 445, 450, 455 that make it possible to transmit data coming from the cell memories 441, 446, 451, 456 respectively arranged on the anode thereof towards the gate of SW1 435. The fifth transistor 460 is connected by the cathode thereof to the anode of SW1 435 and comprises an analog supply V.sub.ANA on the anode thereof and a signal V.sub.reset on the gate thereof. The memory cell may be of type with six transistors or more. The sub-pixel 425 of the display portion 480 operates with only one level of luminance, therefore it is by controlling the emission time of said latter that the gray levels are produced.

(49) The circuit according to FIG. 5 may be used in three different ways. According to a first use mode only the dynamic portion 470 of the circuit is used. A video stream 31 supplies the anode of SW2 405. The transistor becomes conducting only when the voltage V.sub.select (coming from the module 33) permits same to switch on the display portion 490. The capacitor CS 410 makes it possible to maintain the voltage during a time lapse on the supply to the terminal of T.sub.ANA 415. The static portion 480 transmits the signals S1, S2, S3 and S4 with a logic level at 1, and the level of the memory cells therefore has no effect on the voltage of the sampling capacity of the capacitor CS 410 and therefore on the video signal 31.

(50) According to a second use mode only the static portion 480 of the circuit is used. The writing in the memory cells 441, 446, 451, 456 is carried out completely randomly. In order to prevent any effect of visible flicker at the display portion 490, the refresh frequency of the signal must be higher than 85 Hz or lower than 12 ms. It is preferable to use an even higher frequency, around 120 Hz, in order to limit the interferences concerning the writing time and emission of the memory cells. In this use mode, the voltage state of the gate of the transistor T.sub.ANA is not necessarily known and it may be a case of high impedance, in which case the transistor remains blocked. In order to overcome this problem, the applicant proposes to use a voltage V.sub.select in order to initialize the transistor T.sub.ANA. For this in the case of a graphic mode only, the voltage V.sub.select is not controlled by the sequencer 33 but comes from the reference voltage 147 generator 44.

(51) The signal of the voltage V.sub.select makes it possible to reinitialize the transistor T.sub.ANA before each write in the memory cells.

(52) The third use mode is a mixed mode referred to as overlay, which involves both the static portion 480 and the dynamic portion 470 of the circuit. The dynamic portion 270 sends the video signal 31 on the sampling capacity CS 410. The voltage level on the capacity may be forced by the data coming from the memory cells 441, 446, 451, 456 that will force the display of the static portion 480 on the video stream 31 of the dynamic portion 470. The voltage V.sub.select takes the features of the signal of the sequencer 33 through the vertical shift register 37.

(53) FIG. 6 describes a timing chart of control signals 146 of the emission time applied to inputs S1 to S4 of the pixel circuits to block the transistor T.sub.ANA between 2 conductions. Said timing chart is shown by way of example. Same comprises four bits of gray levels modulated by the four control signals 146, S1, S2, S3, S4. The timing chart describes the control signals S1, S2, S3, S4 by bit of gray level. The emission time generated by S1 corresponds to the first gray level, S2 to the second bit of gray level up to S4. The maximum luminance is reached if S1, S2, S3 and S4 are at 1. A means can be added to vary the luminance via the T/Td ratio; the gray levels remain at 1. The control signals 146 that control S1, S2, S3, S4 are generated by the reference voltage generation unit 4 and more particularly by the pulse width modulation (abbreviated PWM) type signal generator 145.

(54) FIG. 6 also shows the signal of the voltage V.sub.select. Said modulated signal indeed makes it possible to reinitialize the gate of T.sub.ANA before each writing in the memory cells. This signal applies to the last two embodiments.

(55) The diagram shown proposes an advantageous embodiment, however, it may consist of additional memory cells in order to increase the number of gray levels.

(56) FIG. 7 shows a variant 500 of the first embodiment but able to be given in three embodiments. Said variant consists in adding a memory cell 505 connected to the gate of SW2 in each of the embodiments. Regardless of the polarization mode of the OLED, in voltage or in current, and regardless of the embodiment implementing SRAM type memories, said memory cell makes it possible to switch off the video data of the pixel to only leave the graphic channel on the pixel. This modification makes it easier to implement the overlay mode. All of the embodiments make use of reference voltages or intensities 47 that are ideally generated by the reference voltage generation unit 4. It is possible to generate said reference intensities or voltages locally via supply or analog/digital converter voltages. Said choice involves integrating on each assembly of sub-pixels electrical elements for constructing said reference voltages.

(57) All of the embodiments use OLED current driving. For voltage driving, all of the transistors shown of the PMOS type must be replaced by NMOS transistors.

(58) The voltage V.sub.ANA is typically in the order of 1.0 V to 3.3 V (for example 1.8 Volt), the voltage V.sub.cath is typically in the order of −2 V to −9 V (for example −8 Volt).

(59) When the screen is configured to display graphic data at the same time as video data, the graphic data may have either the priority (in the embodiment shown in FIG. 4) or overlay (in the embodiments shown in FIGS. 3, 5 and 7); in said last case the currents in the OLED diode are added together.

(60) More specifically, in the embodiment described in relation with FIG. 4, during the writing of the pixel by the signal V.sub.select, the reference voltages V.sub.ref1 and V.sub.ref2 connected to the graphic data by the transistors SW3 and SW4 are balanced with the voltage 305 controlled by the block 36. After the writing, the transistor SW1 is open and therefore the graphic value is written on the capacity CS and therefore takes the priority over the video signal. It follows that in said operating mode the voltages V.sub.ref1 and V.sub.ref2 are likely to vary, which may, in some cases, lead to a visible effect on the graphic display. Said effect may be minimized if the impedance of the block 37 is much lower than same of the block 36, because in this case the driving by the voltages V.sub.ref1 and V.sub.ref2 takes precedence over the driving by the video voltages 305.