Synaptic resistors for concurrent parallel signal processing, memory and learning with high speed and energy efficiency

Abstract

Synaptic resistors (synstors), and their method of manufacture and integration into exemplary circuits are provided. Synstors are configured to emulate the analog signal processing, learning, and memory functions of synapses. Circuits incorporating synstors are capable of performing signal processing and learning concurrently in parallel analog mode with speed, energy efficiency, and functions superior to computers.

Claims

1. A synstor, capable of providing analog signal processing, memory and learning functions of synapse, comprising: an input electrode and an output electrode; a semiconducting channel connected between the input and output electrodes; at least one dielectric layer disposed adjacent to the semiconducting channel, the dielectric layer disposed adjacent to at least one side of the channel; a reference electrode disposed adjacent to the dielectric layer; and a charge storage material disposed within a portion of the dielectric layer; wherein at least a portion of the dielectric layer is disposed between the charge storage material and the semiconducting channel such that a voltage difference between the channel and the charge storage material must have a magnitude above a threshold value to drive charge through the at least one dielectric layer to the charge storage material to alter a net charge within the charge storage material in an analog mode; wherein a combination of the input and output electrodes and the semiconducting channel between form at least one resistor, and the combination of the semiconducting channel, the dielectric layer, the charge storage material, and the reference electrode form at least one capacitor; wherein the synstor is configured to apply a zero or a constant voltage to the reference electrode, and when no voltage signals are applied on the input and output electrodes, a standby zero voltage or a standby constant voltage is applied on the input and output electrodes; and wherein the synstor is further configured such that at least one set of voltage signals may be applied on the input and output electrodes with respect to the standby voltage such that: when a set of input voltage signals is applied on the input electrode and wherein no voltage signal is applied on the output electrode, the set of input voltage signals induce an output current on the output electrode through the at least one resistor and charges the at least one capacitor such that, after the set of input voltage signals end, the charge in the at least one capacitor is discharged and induces an output current on the output electrode, and wherein the output current may last after the set of input voltage signals ends, when a set of voltage signals is applied on the input electrode and wherein a set of voltage signals with a same or similar amplitude as the set of the input voltage signals is applied to the output electrode simultaneously, the magnitude of the voltage difference between the channel and the charge storage material produced thereby is above the threshold value, charge is driven through the portion of the dielectric layer disposed between the channel and the charge storage material to modify the net charge within the charge storage material and a conductance of the synstor in an analog mode for learning, when a set of voltage signals is applied to one of either the input or the output electrode and wherein no voltage signal or a set of voltage signals with an opposite polarity is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input or the output electrode, the magnitude of the voltage difference between the channel and the charge storage material produced thereby falls below the threshold value such that charge is not driven through the portion of the dielectric layer disposed between the channel and the charge storage material such that the net charge in the charge storage material remains unchanged and the conductance of the synstor remains unchanged for learning, and when a set of voltage signals is applied to one of either the input or the output electrode with respect to the standby voltage and wherein no voltage signal or a set of voltage signals with the opposite polarity is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input or the output electrode, or when no external voltages is applied to either the input or the output or the reference electrode, the conductance of the synstor remains unchanged as memory.

2. The synstor of claim 1, the voltage signals applied to the input and output electrodes can be voltage pulses with fixed amplitudes and temporal durations for signal processing and learning.

3. The synstor of claim 1, wherein the set of the input voltage signals induces a dynamic output current for signal processing, and the dynamic output current is a convolution of a kernel function and a product of the set of input voltage signals and the synstor conductance.

4. The synstor of claim 1, wherein a change rate of the conductance of the synstor is equal to a product of a conductance modification coefficient, the input voltage signal, and the output voltage signal.

5. The synstor of claim 1, wherein the input and output electrodes and the semiconducting channel form a contact with a contact resistance, which is comparable with or larger than the resistance of the channel.

6. The synstor of claim 1, wherein the semiconducting channel forms Schottky barriers with the input and output electrodes, and wherein the input and output electrodes and the channel form a contact with a contact resistance which is comparable with or larger than the resistance of the channel.

7. The synstor of claim 1, wherein the channel is dimensioned to have a length between the input and output electrodes longer than the length of the reference electrode.

8. The synstor of claim 1, wherein the reference electrode extends beyond at least one edge of the portion of the dielectric layer containing the charge storage material.

9. The synstor of claim 1, wherein a thickness of the dielectric layer between the charge storage material and the channel is less than the thickness of the dielectric layer between the charge storage material and the reference electrode.

10. The synstor of claim 1, wherein the semiconducting channel comprises a semiconducting material selected from the group consisting of carbon nanotube, Si, graphene, Ge, SiC, ZnO, InO, InP, TiO.sub.2, Cu.sub.2O, GaN, GaAs, MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, GaSe, GaTe, FeTe, polymers, molecules, and combinations thereof.

11. The synstor of claim 1, wherein the semiconducting channel has a channel length between about 5-10.sup.6 nm, a channel width between about 5-10.sup.6 nm, and a channel thickness between about 0.1-10.sup.5 nm.

12. The synstor of claim 1, wherein the input, output and reference electrodes comprise a conducting or semiconducting material selected from the group consisting of Ti, Al, Au, Ni, Pt, Cu, carbon nanotube, Si, graphene, Ge, SiC, ZnO, InO, InP, TiO.sub.2, Cu.sub.2O, GaN, GaAs, MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, GaSe, GaTe, FeTe, polymers, and combinations thereof.

13. The synstor of claim 1, wherein the dielectric layers comprises an insulative material selected from the group consisting of HfO.sub.2, Al.sub.2O.sub.3, SiO.sub.2, Si.sub.3N.sub.4, Si, C, Ge, SiC, ZnO, InO, InP, TiO.sub.2, Cu.sub.2O, GaN, GaAs, polymers, molecules, and combinations thereof.

14. The synstor of claim 1, wherein the dielectric layers have a dielectric length between about 5-10.sup.6 nm, a dielectric width between about 5-10.sup.6 nm, and a dielectric thickness between about 0.2-10.sup.3 nm.

15. The synstor of claim 1, wherein the charge storage material is selected from the group consisting of molecules, nanoparticles, semiconductor quantum dots, dopants, implanted ions, defects, vacancies, impurities, semiconducting materials, dielectric materials, and metals.

16. The synstor of claim 1, wherein the charge storage material is within a volume with a length between about 5-10.sup.6 nm, a width between about 5-10.sup.6 nm, and a thickness between about 0.1-10.sup.3 nm.

17. The synstor of claim 1, wherein: the semiconducting channel extends laterally beyond at least one edge of the portion of the dielectric layer containing the charge storage material; the semiconducting channel extends laterally beyond at least one edge of the reference electrode; and the reference electrode extends laterally beyond at least one edge of the portion of the dielectric layer containing the charge storage material; and a thickness of the dielectric layer between the charge storage material and the channel is less than the thickness of the dielectric layer between the charge storage material and the reference electrode.

18. A synstor capable of providing analog signal processing, memory and learning functions of biological synapse, comprising: a body connected with an input electrode, an output electrode, and a reference electrode; wherein the synstor is configured to apply a zero or a constant voltage to the reference electrode, and when no sets of voltage signals are applied on the input and output electrodes, a standby zero voltage or a standby constant voltage is applied on the input and output electrodes; and wherein the synstor is configured such that sets of voltage signals may be applied on the input and output electrodes with respect to the standby voltage such that: when a set of input voltage signals is applied on the input electrode with respect to the standby voltage and wherein no voltage signal is applied on the output electrode, the set of the input voltage signals induces a dynamic output current on the output electrode for signal processing, when a set of voltage signals is applied on the input electrode and wherein a set of voltage signals with at least one same or similar amplitude as the set of the input voltage signals is applied to the output electrode simultaneously, a conductance of the synstor is changed in analog mode; when a set of voltage signals is applied to one of either the input or the output electrode and wherein no voltage signal or a set of voltage signals with an opposite polarity is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input or the output electrode, the conductance of the synstor remains unchanged for learning, and when a set of voltage signals is applied to one of either the input or the output electrode with respect to the standby voltage and wherein no voltage signal or a set of voltage signals with the opposite polarity is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input or the output electrode, or when no external voltages is applied to either the input or the output or the reference electrode, the conductance of the synstor remains unchanged as memory.

19. The synstor of claim 18, wherein the dynamic output current is a convolution of a kernel function and a product of the input voltage signals and the synstor conductance.

20. The synstor of claim 18, wherein a change rate of the conductance of the synstor is a product of a conductance modification coefficient, the input voltage signal, and the output voltage signal.

21. A synaptic circuit capable of providing analog signal processing, memory and learning functions comprising: a plurality of synstors, each in turn comprising a body connected with an input electrode, an output electrode, and a reference electrode; wherein each synstor is configured to apply a zero or a constant voltage to the reference electrode, and when no sets of voltage signals are applied on the input and output electrodes, a standby zero voltage or a standby constant voltage is applied on the input and output electrodes; and wherein each synstor is configured such that sets of voltage signals may be applied on the input and output electrodes with respect to the standby voltage, thereof such that: when a set of input voltage signals is applied on the input electrode with respect to the standby voltage and wherein no voltage signal is applied on the output electrode, the set of the input voltage signals induces a dynamic output current on the output electrode for signal processing, when a set of voltage signals is applied on the input electrode and wherein a set of voltage signals with at least one same or similar amplitude as the set of the input voltage signals is applied to the output electrode simultaneously, a conductance of the synstor is changed in analog mode; when a set of voltage signals is applied to one of either the input or the output electrode and wherein no voltage signal or a set of voltage signals with an opposite polarity is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input or the output electrode, the conductance of the synstor remains unchanged for learning, and when a set of voltage signals is applied to one of either the input or the output electrode with respect to the standby voltage and wherein no voltage signal or a set of voltage signals with the opposite polarity is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input or the output electrode, or when no external voltages is applied to either the input or the output or the reference electrode, the conductance of the synstor remains unchanged as memory; and wherein each of the plurality of synstors is a component of a circuit comprising an M×N network of said synstors connected with M input electrodes and N output electrodes such that each input electrode is connected with multiple output electrodes by one or more synstors such that a set of voltage signals applied on the M input electrodes induces dynamic output currents via synstors flowing to the N output electrodes in analog parallel mode for signal processing, wherein the dynamic output currents on the N output electrodes define a current vector which is equal to a convolution of kernel functions and a product of a synstor conductance matrix and the vector of the input voltage signals on the M input electrodes; wherein the circuit is configured such that when a set of voltage signals is applied on the M input electrodes and a set of voltage signals is applied on the N output electrodes, concurrently the synstor conductance matrix is modified in an analog parallel mode for learning, wherein a modification rate of the synstor conductance matrix is proportional to an outer product between the vectors of input and output voltage signals; and wherein concurrently, the circuit is configured to process the voltage signals on the input electrodes and is modified by the voltage signals on the input and output electrodes.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

(1) These and other features and advantages of the present invention will be better understood by reference to the following detailed description when considered in conjunction with the accompanying data and figures, wherein:

(2) FIG. 1A provides a schematic of the operation of a conventional computer based on the Turing Model according to the prior art.

(3) FIG. 1B provides a schematic of the operations of a neural circuit in the brain and a circuit incorporating synstors according to embodiments of this disclosure.

(4) FIG. 2 provides a schematic diagram of basic elements in a synstor of this disclosure.

(5) FIG. 3A provides a schematic diagram of a synstor structure with reference electrode and charge storage materials on one side of the channel according to embodiments of this disclosure.

(6) FIG. 3B provides a schematic diagram of a different synstor structure with reference electrode and charge storage materials on multiple sides of the channel according to embodiments of this disclosure.

(7) FIGS. 4A and 4B provide schematic diagrams of synstor structures with critical dimensions according to embodiments of this disclosure.

(8) FIG. 5 provides a schematic of an M×N circuit of synstors connected with M rows of input electrodes and N columns of output electrodes according to embodiments of this disclosure, where V.sub.i.sup.m denotes the amplitude of a voltage signal on the m.sup.th input electrode, and V.sub.o.sup.n denotes the amplitude of a voltage signal on the n.sup.th output electrode.

(9) FIG. 6 provides a 3D schematic illustration of the structure of a synstor with a carbon nanotube (CNT) channel according to embodiments of the disclosure.

(10) FIG. 7 provides a schematic of a method of fabricating a CNT synstor according to embodiments of this disclosure.

(11) FIGS. 8A to 8B show that a series of voltage pulses (bottom solid lines) with an amplitude V.sub.i=−1.75 V with a pulse width of (A) 10 ns and (B) 15 ns were applied on the input electrode of a CNT synstor, and induced the change of currents, ΔI(t), on the output electrode of the CNT synstor. The experimentally measured currents, ΔI(t), (top solid lines) are fitted by theoretical model (top dashed lines).

(12) FIG. 9A provides schematics showing a CNT-based synstor structure according to embodiments of the disclosure, where: (Left) is a scheme showing the cross-sectional structure of a CNT-based synstor structure according to embodiments of the disclosure composed of a TiO.sub.2 charge storage layer embedded in a HfO.sub.2 dielectric layer, an electrically grounded Al reference electrode, and a semiconducting CNT network channel connected with an Al input electrode and an Al output electrode, and (Right) is a scheme showing a cross-sectional structure of a synstor along a CNT.

(13) FIGS. 9B to 9G show electronic energy-band structures (Left) along the Al input electrode, the CNT channel, and the Al output electrode, and (Right) along CNT channel, the HfO.sub.2 dielectric layer, the TiO.sub.2 charge storage layer, the HfO.sub.2 dielectric layer, and the Al reference electrode under conditions where: (B) shows V.sub.i=V.sub.o=0, (C) shows V.sub.i=V.sub.o=−1.75 V, (D) shows V.sub.i=V.sub.o=1.75 V, (E) shows V.sub.i=−1.75 V and V.sub.o=1.75 V, (F) shows V.sub.i=−1.75 V and V.sub.o=0, and (G) shows V.sub.i=1.75 V and V.sub.o=0 (note: CNT energy-band diagrams with no charge (middle lines), negative charge (top lines), and positive charge (bottom lines) stored in the TiO.sub.2 layer are also shown in FIGS. 9F and 9G). E.sub.f.sup.i, E.sub.f.sup.o, E.sub.f.sup.r, and E.sub.f.sup.TiO.sup.2 denote the Fermi energies of the Al input, output, reference electrodes, and TiO.sub.2 charge storage layer, respectively, the electronic charge is represented by “e”, E.sub.c and E.sub.v denote the edges of the CNT conduction and valence bands, respectively, electrons injected into or depleted from the TiO.sub.2 layer are illustrated as the filled green circles, holes in CNTs, TiO.sub.2, or transported laterally along CNTs are illustrated as the open blue circles, the purple dot-dashed lines represent the Fermi energy of the TiO.sub.2 charge storage layer, and the black dot-dashed lines represent the Fermi energies of the CNT network and the Al input and output electrodes).

(14) FIG. 10A provides a simulated data plot of the differences between the average Fermi energies of the CNT channel, E.sub.f.sup.CNT, and the TiO.sub.2 charge storage layer, E.sub.f.sup.TiO.sup.2, in a CNT synstor according to embodiments of the disclosure under various combinations of V.sub.i voltage signals on its input electrode and V.sub.o voltage signals on its output electrode.

(15) FIG. 10B provides a the change of the charge density, Δρ.sub.s, in the TiO.sub.2 layer of a CNT-based synstor according to embodiments of the disclosure induced by various V.sub.i and V.sub.o voltage signals, where Δρ.sub.s was measured by capacitance-voltage test and plotted versus the amplitudes of the V.sub.i and V.sub.o voltages. Δρ.sub.s data are fitted (solid lines) by theoretical model (EQ. 6 in the following) with Δρ.sub.s=k.sub.ρ.sup.+[V.sub.a−V.sub.t.sup.+] (solid lines) under V.sub.i=V.sub.o> V.sub.t.sup.+>0 and Δρ.sub.s=k.sub.ρ.sup.−[V.sub.a−V.sub.t.sup.−] under V.sub.i=V.sub.o<V.sub.t.sup.−<0 with k.sub.ρ.sup.+=−145 nF/cm.sup.2, k.sub.ρ.sup.−=−106 nF/cm.sup.2, V.sub.t.sup.+=0.92 V, and V.sub.t.sup.−=−0.85 V.

(16) FIG. 11A provides data plots showing percentage changes of the CNT-based synstor conductance, Δw/w.sub.0, induced by 50 pairs of various 5 ms-wide V.sub.i and V.sub.o pulses plotted versus pulse amplitude, where the Δw/w.sub.0 data are fitted (solid lines) by theoretical model (EQ. 7 in the following).

(17) FIG. 11B provides data plots showing the percentage changes of CNT-based synstor conductance according to embodiments of the disclosure, where Δw/w.sub.0, induced by various 10 ns-wide V.sub.i and V.sub.o pulses with V.sub.i=V.sub.o=−1.75 V (upward triangles), V.sub.i=V.sub.o=1.75 V (downward triangles), V.sub.i=V.sub.o=0, V.sub.i=0 and V.sub.o=−1.75 V, V.sub.i=0 and V.sub.o=1.75 V, V.sub.i=1.75 V and V.sub.o=0, and V.sub.i=−1.75 V and V.sub.o=0 plotted versus the applied pulse numbers, n, where the Δw/w.sub.o data are fitted (solid lines) by theoretical model (EQ. 7 in the following).

(18) FIG. 11C provides data plots showing the conductance of a CNT-based synstor changes in modification cycles, where in each cycle, the percentage changes of the conductance, Δw.sub.H/w.sub.mid=(w.sub.H−w.sub.mid)/w.sub.mid and Δw.sub.L/w.sub.mid=(w.sub.L−w.sub.mid)/w.sub.mid are shown as upward and downward triangles, respectively, versus the number of modification cycles, with a mid-range conductance w.sub.mid=(w.sub.H+w.sub.L).sup.2.

(19) FIG. 11D provides a data plot showing results of tests on conductance of CNT-based synstors according to embodiments of the disclosure modified to their high DC conductance values, w.sub.H, by applying 50 pairs of 5 ms-wide V.sub.i and V.sub.o pulses on their input and output electrodes with V.sub.i=V.sub.o=−1.75 V, and modified to their low DC conductance values, w.sub.L, by applying 50 pairs of 5 ms-wide V.sub.i and V.sub.o pulses with V.sub.i=V.sub.o=1.75 V, where the distributions of w.sub.H (grey) and w.sub.L (black) of the synstors are plotted (note the synstors can be modified to an arbitrary analog conductance within the range of 0.2 nS≤w≤1 nS).

(20) FIG. 11E provides data plots of conductance of CNT-based synstors according to embodiments of the disclosure after the synstors were modified to different initial analog conductances by applying pairs of 5 ms-wide V.sub.i and V.sub.o voltage pulses on its input and output electrodes simultaneously with V.sub.i=V.sub.o=−1.75 V or V.sub.i=V.sub.o=1.75 V, where w is shown as a function of time on a logarithmic scale, and the experimental data (dots) are fitted and extrapolated (solid lines).

(21) FIGS. 12A to 12F provide: (A) a scheme showing the cross-sectional structure of a CNT-based synstor according to embodiments of the disclosure composed of a 200 nm-wide p-type semiconducting CNT network channel formed contacts with an Al input electrode, and an Al output electrode, and energy-band structures along the Al input electrode, the 200 nm-wide CNT network channel, and the Al output electrode, under the conditions of: (B) V.sub.i=V.sub.o=−1.75 V, (C) V.sub.i=V.sub.o=1.75 V, (D) V.sub.i=−1.75 V and V.sub.o=1.75 V, (E) V.sub.i=1.75 V and V.sub.o=0, and (F) V.sub.i=−1.75 V and V.sub.o=0.

(22) FIGS. 12G to 12L provide: (G) a scheme showing the cross-sectional structure of a CNT-based synstor according to embodiments of the disclosure composed of a 40 nm-wide p-type semiconducting CNT network channel formed contacts with an Al input electrode, and an Al output electrode. Energy-band structures along the Al input electrode, the 40 nm-wide CNT network, and the Al output electrode, under the conditions of: (H) V.sub.i=V.sub.o=−0.5 V, (I) V.sub.i=V.sub.o=0.5 V, (J) V.sub.i=−0.5 V and V.sub.o=0.5 V, (K) V=0.5 V and V.sub.o=0, and (L) V=−0.5 V and V.sub.o=0.

(23) FIG. 13A provides simulated data plots of the differences between the average Fermi energies of the CNT network, E.sub.f.sup.CNT, and the TiO.sub.2 charge storage layer, E.sub.f.sup.TiO.sup.2, in a synstor according to embodiments of the disclosure with a 200 nm-wide CNT networks under various combinations of V.sub.i voltages on its input electrode, V.sub.o voltages on its output electrode, and an electrically grounded reference electrode.

(24) FIG. 13B provides simulated data plots of the changes of net charge density, Δρ, in the TiO.sub.2 charge storage layer induced by various V.sub.i and V.sub.o voltages applied on a CNT-based synstor according to embodiments of the disclosure with a 200 nm-wide CNT networks.

(25) FIG. 13C provides simulated data plots of the differences between the average Fermi energies of the CNT network, E.sub.f.sup.CNT, and the TiO.sub.2 charge storage layer, E.sub.f.sup.TiO.sup.2, in a synstor according to embodiments of the disclosure with a 40 nm-wide CNT networks under various combinations of V.sub.i voltages on its input electrode, V.sub.o voltages on its output electrode, and an electrically grounded reference electrode.

(26) FIG. 13D provides simulated data plots of the changes of net charge density, Δρ, in the TiO.sub.2 charge storage layer induced by various V.sub.i and V.sub.o voltages applied on a CNT-based synstor according to embodiments of the disclosure with a 40 nm-wide CNT networks.

(27) FIG. 14A provides a schematic of a 4×2 crossbar circuit composed of 72 synstors according to embodiments of the disclosure connected with two horizontal input electrodes and two vertical output electrodes, where each output electrode is connected to an integrate-and-fire “neuron” circuit, N.sub.1 or N.sub.2, and where the speech signals of “yes” and “no” words are converted to sets of voltage pulses, V.sub.i.sup.1, V.sub.i.sup.2, V.sub.i.sup.3, and V.sub.i.sup.4, input to the 1.sup.st, 2.sup.nd, 3.sup.rd, and 4.sup.th electrodes to trigger currents, I.sup.1 and I.sup.2, on the 1.sup.st and 2.sup.nd output electrodes via the synstors, which in turn trigger back-propagating voltage pulses, V.sub.o.sup.1 and V.sub.o.sup.2, on the 1.sup.st and 2.sup.nd output electrodes and forward-propagating voltage pulses, V.sub.f.sup.1 and V.sub.f.sup.2, from the 1.sup.st and 2.sup.nd “neurons”.

(28) FIG. 14B provides an optical image of a synstor circuit chip according to embodiments of the disclosure with input electrodes connected with their contact pads (labeled by V.sub.i.sup.1, V.sub.i.sup.2, V.sub.i.sup.3, and V.sub.i.sup.4), output electrodes (labeled by V.sub.o.sup.1 and V.sub.o.sup.2, and I.sup.1 and I.sup.2), reference electrodes (labeled by “Ref”), and CNT networks connected by the serpentine input and output electrodes.

(29) FIG. 14C provides a plot of the firing rates of +1.75 V 10 ns-wide voltage pulses (V.sub.i.sup.1+, V.sub.i.sup.1−, V.sub.i.sup.2+, V.sub.i.sup.2−, V.sub.i.sup.3+, V.sub.i.sup.3−, V.sub.i.sup.4+, and V.sub.i.sup.4−) on the four input electrodes according to embodiments of the disclosure.

(30) FIG. 14D provides a plot of the firing rates of +1.75 V 10 ns-wide back-propagating voltage pulses (V.sub.o.sup.1+, V.sub.o.sup.1−, V.sub.o.sup.2+, and V.sub.o.sup.2−) on the two output electrodes according to embodiments of the disclosure.

(31) FIG. 14E provides a plot of the 1.0 V output pulses generated from the two “neurons” (V.sub.f.sup.1 and V.sub.f.sup.2) versus time according to embodiments of the disclosure.

(32) FIG. 14F provides a plot of the output of the circuit of FIG. 14A where a “no” word triggers 1.75 V V.sub.i.sup.2+ and V.sub.i.sup.4+ pulses on the 2.sup.nd and 4.sup.th input electrodes and a 1.75 V V.sub.o.sup.2+ pulse on the 2.sup.nd output electrode concurrently, which decrease w.sup.22 and w.sup.42 conductances of the synstors connected with the electrodes, −1.75 V V.sub.i.sup.1− and V.sub.i.sup.3− pulses on the 1.sup.st and 3.sup.rd input electrodes, and a −1.75 V V.sub.o.sup.1− pulse on the 1.sup.st output electrode concurrently, which increase w.sup.11 and w.sup.31, and a “yes” word triggers 1.75 V V.sub.i.sup.1+ and V.sub.i.sup.3+ pulses on the 1.sup.st and 3.sup.rd input electrodes, a 1.75 V V.sub.o.sup.1+ on the 1.sup.st output electrode concurrently, which decrease w.sup.11 and w.sup.31, and −1.75 V V.sub.i.sup.2− and V.sub.i.sup.4− pulses on the 2.sup.nd and 4.sup.th input electrodes, and a −1.75 V V.sub.i.sup.2− pulse on the 2.sup.nd output electrode concurrently, which increase w.sup.22 and w.sup.42 (note: the dashed lines represent the moments when the paired pulses are triggered).

(33) FIG. 15 provides a plot of the energy efficiencies of the Summit supercomputer, Nvidia Volta V100 graphics processing unit (GPU), Google tensor processing unit (TPU), UMass/HP memristor circuits (signal processing only, training and learning algorithm computation excluded), IBM phase change memory (PCM) circuit (training only, learning algorithm computation excluded), the human brain, 4×2 crossbar synstor circuit (solid line) according to embodiments of the disclosure (diamond), and projected 4×2 crossbar synstor circuit according to embodiments of the disclosure are displayed versus the average conductance of the Si transistors, memristors, PCM, and synstors in the circuits in the unit of nano siemens (nS) (note: the thermodynamic limit of the computing energy efficiency in digital computing circuits is shown by the dashed line).

(34) FIG. 16A provides a plot of the natural logarithm of the thermodynamic error rate, p.sub.e, in a 4×2 crossbar synstor circuit according to embodiments of the disclosure, a projected 2 k×2 k crossbar synstor circuit according to embodiments of the disclosure circuit, a transistor-based computing circuit, the Summit supercomputer, Nvidia Volta V100 GPU, and Google TPU are displayed versus the conductance of the synstors and transistors (note: the thermodynamic limit is shown as a red dashed line at p.sub.e=0.5).

(35) FIG. 16B provides a plot of the latency of the Summit supercomputer, Nvidia Volta V100 GPU, Google TPU, the human brain, a 4×2 crossbar synstor circuit according to embodiments of the disclosure (diamond), and a projected 2 k×2 k crossbar synstor circuit according to embodiments of the disclosure, displayed versus the conductance of the synpatic resistors, transistors, and synapses.

(36) FIG. 17 provides a plot of the power consumptions, computing speeds, and energy efficiencies of the Summit supercomputer, Nvidia Volta V100 GPU, Google TPU, UMass/HP memristor circuits (signal processing only, training and learning algorithm computation excluded), IBM phase change memory (PCM) circuit (training only, learning algorithm computation excluded), the human brain, a 4×2 crossbar synstor circuit according to embodiments of the disclosure, and a projected 2 k×2 k and 100×2 k×2 k crossbar synstor circuits according to embodiments of the disclosure.

DETAILED DISCLOSURE

(37) The embodiments of the invention described herein are not intended to be exhaustive or to limit the invention to precise forms disclosed. Rather, the embodiments selected for description have been chosen to enable one skilled in the art to practice the invention. All structural and functional equivalents to the elements of the disclosed embodiments that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims.

Overview of Embodiments

(38) As previously discussed, a computer based on the Turing model has separate logic and memory units. As shown in FIG. 1A, based on the Turing model, digital computers execute signal processing and learning algorithms in serial mode by physically separated logic and memory transistors, and the computing energy is predominantly consumed by data memory and signal transmissions between memory and logic units, referred to as the “von Neumann bottleneck.” If an M-dimensional signals includes M independent variables, each variable has K different possible values (K=2 in digital computers), and the signal contains K.sup.M different configurations. Therefore, the memory capacity, time, and energy consumption needed for the computer to transmit, process, and learn from the signals with K.sup.M different configurations in the serial computing mode shown in FIG. 1A increases with M exponentially, referred to as the “curse of dimensionality”.

(39) Digital transistors have been developed to compose circuits with parallel computing architectures and distributed memories, such as graphics processing units (GPUs) from Nvidia, tensor processing units (TPUs) from Google, field-programmable gate arrays (FPGAs) from Intel, and the TrueNorth neuromorphic circuit from IBM, to improve their speed and energy efficiencies to the range of 10.sup.10-10.sup.11 FLOPS/W (floating point operations per second per watt) by increasing parallelism and reducing global data transmission. However, their energy efficiencies are fundamentally limited by the energy consumptions on memory (˜10.sup.−15 J/bit) and signal transitions (˜10−11 J/bit) in digital computing circuits. When transistors approach the limitations of their minimal sizes near the end of Moore's law, the energy efficiencies of transistor-based computing circuits are asymptotically saturated.

(40) By contrast, the brain circumvents these bottleneck problems by processing signals in parallel via trillions of synapses, and modifying the synapses concurrently in a parallel learning process. The analog signal processing, learning, and memory functions are integrated in each single synapse. For signal processing, when a set of input voltage pulse signals in a presynaptic neuron is processed by a synapse, wherein no voltage signal in the postsynaptic neuron, the input voltage signals induces a dynamic current via the synapse in the postsynaptic neuron. The postsynaptic current can be expressed as:
I(t)=κ{circle around (*)}(wV.sub.i)  (EQ. 1)
where V.sub.i(t) denotes the voltage pulse signals on the presynaptic neuron, w(t) denotes the synaptic conductance (weight), κ(t) represents a kernel dynamic function, and κ{circle around (*)}(wV.sub.i) represents the convolution of κ(t) and w(t) V.sub.i(t). The synapse is also modified by the sets of voltage pulse signals triggered simultaneously in the presynaptic and postsynaptic neurons for learning. The modification rate of the synaptic conductance, w, can be expressed as
{dot over (w)}=αV.sub.iV.sub.o  (EQ. 2)
where V.sub.i denotes the voltage signals in the presynaptic neuron, V.sub.o denotes the voltage signals in the postsynaptic neuron, and a denotes the conductance modification coefficient. w is modified when the voltage pulse signals V.sub.i(t)≈V.sub.o(t) with the learning coefficient α>0 in Hebbian learning, and α<0 in anti-Hebbian learning. α is a function of the timing difference, Δt, between V.sub.i(t) and V.sub.o(t+Δt) voltage pulse signals in the learning based on synaptic spike-timing-dependent plasticity (STDP). EQ. 2 also represents a universal correlative learning algorithm in machine learning. When a set of voltage pulse signals is triggered in the presynaptic or postsynaptic neurons, and wherein no voltage pulse signals is triggered in the presynaptic or postsynaptic neurons, the synaptic conductance is not changed for learning. Based on EQ. 2, when V.sub.i V.sub.o>0 (i.e. V.sub.i(t)≈V.sub.o(t)), then {dot over (w)}≠0; when V.sub.i V.sub.o=0 (e.g. V.sub.i≠0 and V.sub.o=0; or V.sub.o≠0 and V.sub.i=0; or V.sub.i=V.sub.o=0), then {dot over (w)}=0, w remains unchanged as nonvolatile memory. By integrating the analog convolutional processing (EQ. 1), correlative learning (EQ. 2), a neural network in the brain can concurrently process and learn from signals. For signal processing, a set of voltage pulse signals, V.sub.i.sup.m(t), in the m.sup.th presynaptic neuron is processed by synapses connected with the m.sup.th presynaptic and n.sup.th postsynaptic neurons, and induces a collective current, I.sup.n, in the n.sup.th postsynaptic neuron. The current induces voltage pulse signals, V.sub.o.sup.n(t), in the n.sup.th postsynaptic neuron. When the voltage pulse signal is fired in the n.sup.th postsynaptic neuron (V.sub.o.sup.n≠0), the output current I.sup.n=0 in the n.sup.th postsynaptic neuron. I.sup.n can be expressed as,

(41) $\begin{array}{cc}{I}^n\left(t\right)=\{\begin{array}{cc}\underset{m}{.Math.}{\kappa }^{nm}\left(w^{nm}{V}_i^m\right)& \mathrm{when}{V}_o^n=0\\ 0& \mathrm{when}{V}_o^n\ne 0\end{array}& \left(\mathrm{EQ}.3\right)\end{array}$
where w.sup.nm denotes the conductance of the synstor(s), κ.sup.nm(t) denotes a temporal kernel function, and κ.sup.nm ®{circle around (*)}(w.sup.nmV.sub.i.sup.m) represents the temporal convolution between w.sup.nmV.sub.i.sup.m and V.sub.i.sup.m(t). The conductance matrix of the synapses, [W.sup.nm].sub.N,M in the neuronal network is also modified concurrently by the sets of voltage signals in the input and output electrodes for learning,
{dot over (w)}.sup.nm=αV.sub.i.sup.mV.sub.o.sup.n  (EQ. 4)

(42) The brain processes (EQ. 3) and learns (EQ. 4) from “big data” concurrently in analog parallel mode with an estimated speed of ˜10.sup.16 FLOPS comparable to the fastest supercomputer, Summit (˜10.sup.17 FLOPS), but the brain consumes a power of ˜20 W, much less than the power of the supercomputer (˜10.sup.7 W), and the brain is much more energy-efficient (˜10.sup.15 FLOPS/W) than the supercomputer (˜10.sup.10 FLOPS/W). In summary, by integrating the analog convolutional processing (EQ. 1), correlative learning (EQ. 2), and nonvolatile memory functions in a single synapse, the brain circumvents the fundamental limitations such as physically separated memory units, data transmission between memory and logic units in computers as shown in FIG. 1A, and concurrently executes the signal processing (EQ. 3) and learning (EQ. 4) in the brain in analog parallel mode, as shown in FIG. 1B, with an energy-efficient more than five orders of magnitudes higher than that of the computers.

(43) The circuits of the existing electronic devices, such as transistors, memristors, and phase change memory (PCM) devices, cannot execute the signal processing (EQ. 1) and correlative learning (EQ. 2) algorithms concurrently in parallel mode, which limits their speeds and energy efficiencies for processing and learning from “big data”. The devices in their circuits still need to be modified in serial learning processes by the signals from peripheral memory, signal processing, and/or control circuits, which limits the speeds and energy efficiencies of their circuits for learning (≤10.sup.11 FLOPS/W).

(44) To address the said limitations and inefficiencies of the circuits of existing electronic devices, embodiments are directed to circuits of synstors that capable of facilitating concurrent parallel signal processing and learning with high speed and energy efficiency, as shown schematically in FIG. 1B.

(45) As illustrated in FIG. 2, a synstor (1) comprises an input electrode (2), an output electrode (3), and a reference electrode (4) connected with a body (5) of the device. Although the body of the synstor device is shown as a single monolithic structure, it will be understood that it may be comprised of multiple layers or structures that combine to accomplish the proscribed function of the structure within the device.

(46) Such a synstor has analog signal processing, memory and learning functions of biological synapse. The synstor is configured to apply a zero or a constant voltage to the reference electrode (4). When no voltage signals are applied on the input (2) and output (3) electrodes, a standby zero voltage or a standby constant voltage is applied on the input and output electrodes. Sets of voltage signals are applied on the input and output electrodes with respect to the standby voltage. The voltage signals can be voltage pulses with fixed amplitudes and temporal durations for signal processing and learning.

(47) According to embodiments a synstor is configured for signal processing when a set of input voltage signals is applied on the input electrode (2), wherein no voltage signal is applied on the output electrode (3), the set of the input voltage signals induces a dynamic output current on the output electrode (3). The output current can be expressed as,
I(t)=K{circle around (*)}(wV.sub.i)  (EQ. 1)
where V.sub.i denotes the voltage signals on the input electrode, w(t) denotes the synstor conductance, κ(t) represents a kernel function, and κ{circle around (*)}(wV.sub.i) represents the convolution of κ(t) and w(t) V.sub.i(t).

(48) When a set of voltage signals is applied to the input electrode (2), wherein a set of voltage signals with the same or similar amplitudes as the voltage signals is applied to the output electrode (3) simultaneously, the conductance of the synstor is changed in analog mode for learning; when a set of voltage signals is applied to one of either the input (2) or the output electrode (3), and wherein no voltage signals or a set of voltage signals with different polarities is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input (2) or the output electrode (3), the conductance of the synstor is not changed for learning. The change rate of the conductance of the synstor, w, can be expressed as,
{dot over (w)}=αV.sub.iV.sub.o  (EQ. 2)
where V.sub.i denotes the voltage signals on the input electrode, V.sub.o denotes the voltage signals on the output electrode, and α denotes the conductance modification coefficient. When V.sub.i V.sub.o>0, then α≠0 and {dot over (w)}≠0; when V.sub.i V.sub.o≤0, then α=0 and {dot over (w)}=0.

(49) When a set of voltage signals is applied to one of either the input (2) or the output electrode (3), and wherein no voltage signals or a set of voltage signals with different polarities is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input (2) or the output electrode (3), or when no external voltages are applied to either the input or the output or the reference electrode the conductance of the synstor remains unchanged as memory, i.e. {dot over (w)}=0, under V.sub.i V.sub.o≤0.

(50) According to many embodiments, such synstor devices may have a structure as illustrated in FIGS. 3A and 3B. As shown in FIG. 3A, in many embodiments the synstor device (10) generally comprises a semiconducting channel (12) that is connected to an input (14) and an output (16) electrodes. The synstor device also comprises a dielectric layer (18) disposed adjacent the channel. The device also comprises a charge storage material (20) buried within the dielectric layer (18), and a reference electrode (24) disposed adjacent to the dielectric layer (18). As shown in FIG. 3B, the synstor device may also comprise a dielectric layer (18) disposed adjacent the channel (12) and contacted with the multiple sides of the channel (12). The device may also comprise a charge storage material (20) buried within the dielectric layer (18), and a reference electrode (24) buried within the dielectric layer (18) around the multiple sides of the channel (12). The synstor has a transistor-like structure, but its reference electrode is always grounded, and it does not need a programmed gate voltage to control the current between the input and output electrodes like a transistor. Although each of the structures of the synstor device is shown as a single monolithic structure, it will be understood that each may be comprised of multiple layers or structures that combine to accomplish the proscribed function of the structure within the device.

(51) Although FIGS. 3A and 3B are schematic and not to be taken as a “to-scale” drawing of a synstor according to embodiments, it will be understood that relative dimensions of certain elements of the synstor are contemplated as being part of the current disclosure. In many embodiments, as shown in FIGS. 3A and 3B, at least a portion of the dielectric layer (18) is sandwiched between the charge storage material (20) and the semiconducting channel (12) such that the dielectric layer (18) ensures that when the magnitude of the voltage difference between the channel (12) and the charge storage material (20) is smaller than a threshold value, the voltage difference is insufficient to drive charge through the dielectric layer (18) to modify the charge storage material (20) such that the net charge within the charge storage material (18) remains unchanged after the voltage difference is applied; when the magnitude of the voltage difference between the channel (12) and the charge storage material (20) is larger than a threshold value, the voltage difference is sufficient to drive charge through the dielectric layer (18) to modify the charge storage material (20) such that the charge within the charge storage material (20) is changed before and after the voltage difference is applied. For the same reasons, in various embodiments, as shown in FIG. 4A and FIG. 4B, the thickness (32) of the dielectric layer (18) between the charge storage material (20) and the semiconducting channel (12) is adjusted to its optimized value.

(52) In many embodiments, at least a portion of the dielectric layer (18) is disposed between the charge storage material (20) and the reference electrode (24) such that the dielectric layer (18) ensures that the voltage differences between the charge storage material (20) and the reference electrode (24) are insufficient to drive charge through the dielectric layer (18). For the same reason, in various embodiments, as shown in FIGS. 4A and 4B, the thickness (34) of the dielectric layer (18) between the charge storage material (20) and the reference electrode (24) is adjusted to its optimized value. For the same reasons, in various embodiments, as shown in FIGS. 4A and 4B, the thickness (34) of the dielectric layer (18) between the charge storage material (20) and the reference electrode (24) may be larger than the thickness (32) of the dielectric layer (18) between the charge storage material (20) and the semiconducting channel (12).

(53) The combination of the input electrode (14), the semiconducting channel (12), and the output electrode (16) form a resistor. The combination of the semiconducting channel (12), the dielectric layer (18), the charge storage material (20) forms a capacitor. The charge storage material (20), the dielectric layer (18), and the reference electrode (24) form a capacitor. The two capacitors are connected in series to form a capacitor between the semiconducting channel (12) and the reference electrode (24).

(54) The synstor is configured to apply a zero or a constant voltage to the reference electrode (24). When no voltage signals are applied on the input (14) and output (16) electrodes, a standby zero voltage or a standby constant voltage is applied on the input and output electrodes. Sets of voltage signals are applied on the input and output electrodes with respect to the standby voltage. The voltage signals can be voltage pulses with fixed amplitudes and temporal durations for signal processing and learning.

(55) According to embodiments a synstor is configured such that during signal processing when a set of input voltage signals is applied on the input electrode (14), wherein no voltage signal is applied on the output electrode (16), a synstor processes a set of voltage signals on its input electrode (14) by inducing an output current on the output electrode through the resistors, and charging the capacitor between the semiconducting channel (12) and the reference electrode (24) during the voltage signals, and discharging the capacitor after the voltage signals, and triggering a dynamic current on the output electrode (16). The output current can be expressed as
I(t)=κ{circle around (*)}(wV.sub.i)  (EQ. 1)
where V.sub.i denotes the voltage signals on the input electrode, w(t) denotes the synstor conductance, κ(t) represents a kernel function, and κ{circle around (*)}(wV.sub.i) represents the convolution of κ(t) and w(t) V.sub.i(t).

(56) According to embodiments a synstor is configured such that during learning when a set of voltage signals is applied to the input electrode (14), wherein a set of voltage signals with the same or similar amplitudes as the voltage signals is applied to the output electrode (16) simultaneously, the sets of the voltage signals generates a voltage difference between the channel (12) and the charge storage material (20) across the dielectric layer (18), which has an magnitude larger than the threshold value and is sufficient to drive charge through the dielectric layer (18) to modify the charge storage material (20), such that the net charge within the charge storage material (18) is changed. In such embodiments, the change of the net charge within the charge storage material (18) induces the change of the carrier concentration in the semiconducting channel, such that the conductance of the synstor is changed in analog mode for learning. When a set of voltage signals is applied to one of either the input or the output electrode and wherein no voltage signal or a set of voltage signals with the opposite polarity is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input or the output electrode, the set of the voltage signals only generates a voltage difference between the channel (12) and the charge storage material (20) across the dielectric layer (18), which has an magnitude smaller than the threshold value and is insufficient to drive charge through the dielectric layer (18) to modify the charge storage material (20). In such embodiments, the net charge within the charge storage material (18) remains unchanged, and the conductance of the synstor is not changed for learning. When no voltage signals is applied to either the input (14) or the output electrode (16), the voltage difference between the channel (12) and the charge storage material (20) across the dielectric layer (18) has an magnitude smaller than the threshold value and is insufficient to drive charge through the dielectric layer (18) to modify the charge storage material (20). In such embodiments, the net charge within the charge storage material (18) remains unchanged, and the conductance of the synstor is not changed for learning. The change rate of the conductance of the synstor, w, can be expressed as
{dot over (w)}=αV.sub.iV.sub.o  (EQ. 2)
where V.sub.i denotes the voltage signals on the input electrode, V.sub.o denotes the voltage signals on the output electrode, and α denotes the conductance modification coefficient. When V.sub.i V.sub.o>0, then α≠0 and {dot over (w)}≠0; when V.sub.i V.sub.o≤0, then α=0 and {dot over (w)}=0.

(57) When a set of voltage signals is applied to one of either the input or the output electrode and wherein no voltage signal or a set of voltage signals with the opposite polarity is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input or the output electrode, or when no external voltages is applied to either the input or the output or the reference electrode for the same reason, the conductance of the synstor remains unchanged as memory, i.e. {dot over (w)}=0, under V.sub.i V.sub.o<0.

(58) In many embodiments, the input/output electrodes (14/16) and the channel (12) form a contact with a contact resistance which is comparable with or larger than the resistance of the channel (12) such that when a set of voltage signals is applied to one of either the input (14) or the output electrode (16), and wherein no voltage signals or a set of voltage signals with different polarities is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input (14) or the output electrode (16), the voltage drops across the contact region(s) between the input/output electrode (14/16) and the channel (12), and the lateral spaces beyond the charge storage material (20). In such embodiments, the voltage difference between the channel (12) and the charge storage material (20) across the dielectric layers (18) induced by the voltage signal(s) has an magnitude smaller than the threshold value and is insufficient to drive charge through the dielectric layer (18) to modify the charge storage material (20), such that the net charge within the charge storage material (18) and the conductance of the synstor remains unchanged for memory and learning.

(59) In many other embodiments, the input/output electrodes (14/16) form Schottky barriers with the channel (12) such that when a set of voltage signals is applied to one of either the input (14) or the output electrode (16), and wherein no voltage signals or a set of voltage signals with different polarities is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input (14) or the output electrode (16), the voltage mainly drops across the contact region between the input/output electrode and the channel, and the lateral spaces beyond the charge storage material (20). Again, in such embodiments, the voltage difference between the channel (12) and the charge storage material (20) across the dielectric layers (18) induced by the voltage signal(s) has an magnitude smaller than the threshold value and is insufficient to drive charge through the dielectric layer (18) to modify the charge storage material (20), such that the net charge within the charge storage material (18) and the conductance of the synstor remains unchanged for memory and learning.

(60) As shown in FIGS. 4A and 4B, in various embodiments the channel (22) is dimensioned to have the channel length (26) be longer than the length (28) of the charge storage material (20) such that when a set of voltage signals is applied to one of either the input (14) or the output electrode (16), and wherein no voltage signals or a set of voltage signals with different polarities is applied to the other of either the input or output electrode simultaneously, the voltage drop occurs prior to the spatial occurrence of the charge storage material to ensure that the voltage difference between the channel (12) and the charge storage material (20) has an magnitude smaller than the threshold value and is insufficient to drive charge through the dielectric layer (18) to modify the charge storage material (20) and the synstor conductance. For the same reasons, in various embodiments, the length (30) of the reference electrode (24) is also configured to be longer than or equal to the length (28) of the charge storage material (20). For the same reasons, in many embodiments, the length (26) of the channel is longer than the length (30) of the reference electrode (24). To modify the carriers in the channel (12) by the charge storage material (20), in many embodiments, the width (not shown) of the charge storage material is wider than or equal to the width (not shown) of the channel. For the same reasons, in many embodiments, the width (not shown) of the reference electrode is wider than or equal to the width (not shown) of the charge storage material (20). A further discussion of the operation of synstors in accordance with many embodiments is further described below.

(61) Turning to the materials used in the construction of the various structures, various embodiments the channel (12) in the synstor device may comprise a semiconducting material selected from but not limited to carbon nanotube, Si, graphene, Ge, SiC, ZnO, InO, InP, TiO.sub.2, Cu.sub.2O, GaN, GaAs, MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, GaSe, GaTe, FeTe, polymers, and molecules, etc. In many embodiments, the channel length (26) may range between about 5-10.sup.6 nm, the channel width may range between about 5-10.sup.6 nm, and the channel thickness may range between about 0.1-10.sup.5 nm.

(62) In various embodiments the input (14) and output (16) electrodes in the synstor device may comprise metals, such as, for example, Ti, Al, Au, Ni, Pt, Cu, etc. or semiconductor such as selected from but not limited to carbon nanotube, Si, graphene, Ge, SiC, ZnO, InO, InP, TiO.sub.2, Cu.sub.2O, GaN, GaAs, MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, GaSe, GaTe, FeTe, and polymers, etc.

(63) I.sup.n various embodiments the dielectric layers (18) in the synstor device may comprise insulative materials selected from but not limited to HfO.sub.2, Al.sub.2O.sub.3, SiO.sub.2, Si.sub.3N.sub.4, Si, C, Ge, SiC, ZnO, InO, InP, TiO.sub.2, Cu.sub.2O, GaN, GaAs, etc. or polymers, and molecules. In many embodiments, the length of the dielectric layer may range between about 5-10.sup.6 nm, the width of the first dielectric layer may range between about 5-10.sup.6 nm. In many embodiments, the thickness (32) of the dielectric layer (18) between the charge storage material (20) and the semiconducting channel (12) may range between about 0.2-10.sup.2 nm. In many embodiments, the thickness (34) of the dielectric layer (18) between the charge storage material (20) and the reference electrode (24) may range between about 0.5-10.sup.3 nm.

(64) In various embodiments, the charge storage material (22) may comprise continuous or distributed charge storage materials buried within the dielectric layer (18). In many embodiments the charge storage materials may comprise molecules such as C60, nanoparticles such as Au nanoparticles, semiconductor quantum dots, impurities such as, for example, dopants and implanted ions inside the material, and defects inside the material, such as, for example, vacancies, impurity, semiconducting films selected from but not limited to Si, C, Ge, SiC, ZnO, InO, InP, TiO.sub.2, Cu.sub.2O, GaN, GaAs, dielectric materials selected from but not limited to TiO.sub.2, SiO.sub.2, Si.sub.3N.sub.4, HfO.sub.2, Al.sub.2O.sub.3, or metals selected from but not limited to Ti, Al, Au, Ni, Pt, Cu, etc. I.sup.n many embodiments, the dimensions of the charge storage material may range between about 0.2-10.sup.2 nm.

(65) In various embodiments the reference electrode (24) in the synstor device may comprise metals selected from but not limited to Ti, Al, Au, Ni, Pt, Cu, or semiconducting materials selected from but not limited to carbon nanotube, Si, graphene, Ge, SiC, ZnO, InO, InP, TiO.sub.2, Cu.sub.2O, GaN, GaAs, MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, GaSe, GaTe, FeTe, and polymers, etc.

(66) Although specific materials and combinations of materials are described above, it will be understood that any suitable combination of such materials may be used where appropriate such that the overall functions of the synstor device is preserved.

(67) As discussed above, the synstor device according to embodiments is configured to provide analog signal processing, memory, and learning functions in a single device. Additional advantages may include, but are not limited to, the following: The synstor device integrates the elementary signal processing, learning, and memory functions of a biological synapse. When a set of input voltage signals is applied on the input electrode, wherein no voltage signal is applied on the output electrode, the input voltage signals can trigger dynamic currents on its output electrode from the synstor device to emulate the various dynamic properties of a synapse (as discussed with respect to EQ. 1) such as an excitatory post-synaptic current (EPSC) or an inhibitory post-synaptic current (IPSC). When a set of voltage signals is applied to the input electrode, wherein a set of voltage signals with the same or similar amplitudes as the voltage signals is applied to the output electrode simultaneously, the conductance of the synstor are changed in analog mode for learning; otherwise, when a set of voltage signals is applied to one of either the input or the output electrode, and wherein no voltage signals or a set of voltage signals with different polarities is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input or the output electrode, the conductance of the synstor is not changed for learning. The conductance of the synstor device can be modified to analog values like a biological synapse (as discussed with respect to EQ. 2). The device's analog configuration function enables the synstor device to have an analog “learning” capability. When a set of voltage signals is applied to one of either the input or the output electrode, and wherein no voltage signals or a set of voltage signals with different polarities is applied to the other of either the input or output electrode simultaneously, or when no voltage signals is applied to either the input or the output electrode, or when no external voltages is applied to either the input or the output or the reference electrode, the charge concentrations in the charge storage layer and device conductance will remain unchanged as memory. The synstor device can be operated as a signal processing, learning, and memory devices in one. The device consumes very low energy during operation. The power consumption of a synstor (and its circuit) decreases with decreasing synstor conductance, therefore the power consumption of the device (and its circuit) can be reduced by decreasing synstor conductance. The synstor device consumes only a small fraction of energy of the existing electronic devices. The device can be fabricated based on the fabrication technology of nanoscale transistor and semiconductor materials. The size of the device can be reduced to extremely small, and its size is only a small fraction of the biological synapse. The small size, low-power-consumption device can be used as the basic element to fabricate circuits with the concurrent signal processing and learning functions of the brain.
Embodiments of Synstor Circuits

(68) Although the above discussion has focused on the architecture, materials and function of synstor devices according to certain embodiments, various other embodiments are directed to the integration of synstors in circuits. In many embodiments, as illustrated in FIG. 5, synstors can form an M×N circuit with M input electrodes (54) and N output electrodes (56). In such a circuit, input electrodes are connected with output electrodes by a synstor or multiple synstors (58).

(69) Using a circuit in accordance with such embodiments circumvents the bottleneck problems of conventional computers by processing voltage signals in parallel, and modifying the conductances of the synstors concurrently in a parallel learning process. As shown in FIG. 5, for signal processing, a set of voltage signals, V.sub.i.sup.m(t), in the m.sup.th input electrode is processed by a synstor (or synstors) connected with the m.sup.th input and n.sup.th output electrodes, and induces a current in the n.sup.th output electrode, I.sup.nm=κ.sub.nm {circle around (*)}(w.sup.nmV.sub.i.sup.m) (EQ. 1), where w.sup.nm denotes the conductance of the synstor(s), κ.sup.nm(t) denotes a temporal kernel function, and κ.sup.nm {circle around (*)}(w.sup.nmV.sub.i.sup.m) represents the temporal convolution between w.sup.nmV.sub.i.sup.m and V.sub.i.sup.m(t). For signal processing, a set of voltage signals in input electrodes induces a collective current I.sup.n=Σ.sub.mI.sup.nm via synstors in the n.sup.th output electrode, and the current induces voltage signals, V.sub.o.sup.n(t), in the n.sup.th output electrode (e.g. from external “integrate-and-fire” circuits). When the voltage signal is fired in the output electrode (V.sub.o.sup.n≠0), the output current I.sup.n=0. Thus I.sup.n can be expressed as,

(70) $\begin{array}{cc}{I}^n\left(t\right)=\{\begin{array}{cc}\underset{m}{.Math.}{\kappa }^{nm}\left(w^{nm}{V}_i^m\right)& \mathrm{when}{V}_o^n=0\\ 0& \mathrm{when}{V}_o^n\ne 0\end{array}& \left(\mathrm{EQ}.3\right)\end{array}$
The synstor conductance matrix, [w.sup.nm].sup.N,M is also modified concurrently by the spatiotemporal sets of voltage signals in the input and output electrodes for learning,
{dot over (w)}.sup.nm=αV.sub.i.sup.mV.sub.o.sup.n  (EQ. 4)
where α denotes the conductance modification coefficient. By integrating the analog convolutional processing (EQ. 1), correlative learning (EQ. 2), and nonvolatile memory functions in a single synstor, the synstor circuit in accordance with embodiments concurrently executes the signal processing (EQ. 3) and correlative learning (EQ. 4) algorithms in a circuit in analog parallel mode.

(71) Synstor circuits in accordance with embodiments may be advantageous in various ways, which include but are not limited to the following: The synstor circuits can concurrently process and learn from signals in analog parallel mode. The synstor circuit can execute real-time learning when the circuit is processing signals. The synstor circuit circumvents the fundamental limitations such as physically separated memory units, data transmission between memory and logic units, execution of signal processing and learning algorithms in serial mode in computers. The time for a synstor circuit to process and learn from large-dimensional signals in the parallel mode does not increase with signal dimensions (M and N). The speed for the circuit to process and learn from large-dimensional signals increases with the circuit dimension (M and N). The synstor circuit circumvents the power consumptions for separated memory and signal transmission between the memory and logic circuits in computers. The power consumption of the synstor circuit can be further improved by decreasing synstor conductance. The memory capacity of the nonlinear synstor circuit increases with signal/circuit dimensions. The speed and energy efficiency of synstor circuits for processing and learning from “big data” can be much higher than existing electronic circuits. By shrinking synstors to nanoscale, synstor circuits can be scaled up for real-time learning from “big data” with speed, power consumption, memory capacity, and learning capability superior to computers and existing electronic circuits. By integrating synstor circuits with nonlinear “integrate-and-fire” circuits, the circuits can be applied to in-situ and real-time learning to self-program circuit in dynamic environments.

Exemplary Embodiments

(72) Although the description herein contains many details, these should not be construed as limiting the scope of the disclosure but as merely providing illustrations of some of the presently preferred embodiments. Therefore, it will be appreciated that the scope of the disclosure fully encompasses other embodiments, which may become obvious to those skilled in the art.

(73) Exemplary Synstor

(74) An exemplary carbon nanotube (CNT) synstor is shown in FIG. 6. The synstor (10) has an input electrode (14), an output electrode (16), a semiconducting channel (12), a charge storage layer (20) embedded in a dielectric layer (18), and a reference electrode (24). In an exemplary embodiment the synstor is composed of a 20 μm-wide p-type semiconducting CNT network as the channel (12) which forms Schottky contacts with the Al input (14) and output (16) electrodes. The CNT networks are fabricated on a 6.5 nm-thick HfO.sub.2 dielectric layer (18) on a 2.5 nm-thick and 10 μm-wide TiO.sub.2 charge storage layer (24) on a 22 nm-thick HfO.sub.2 dielectric layer (18) on a 50 nm-thick and 10 μm-wide Al reference electrode (24). There is a 5 μm lateral space between the TiO.sub.2 charge storage layer/Al reference electrode and Al input/output electrodes.

(75) Methods of Fabrication

(76) In various exemplary embodiments of methods to fabricate CNT synstors, as shown In FIG. 7, an Al film was deposited on a SiO.sub.2 film on a Si wafer by e-beam evaporation and patterned by photolithography and chemical etching to produce a 10 μm wide reference electrode. A 22 nm thick HfO.sub.2 film and a 2.5 nm thick TiO.sub.2 film were deposited by atomic layer deposition (ALD). The TiO.sub.2 film was patterned by photolithography and reactive ion etching (RIE) to make a 10 μm charge storage layer aligned to the Al reference electrode, and capped by a 6.5 nm thick HfO.sub.2 film by ALD. A network of randomly oriented CNTs was deposited from a 99.9% pure semiconducting single-wall CNT solution by immersion coating, and capped by an Al film deposited by e-beam evaporation. The Al film was patterned by photolithography and chemical etching to produce an input and an output electrode. The chip surface was coated with a monolayer poly (L-lysine) film by immersing the chip in a poly(L-lysine) (PLL) solution. A percolating carbon nanotube (CNT) network was then deposited by immersing the PLL-coated chip into an aqueous CNT solution. 50 nm thick Al input and output electrodes were fabricated by the same process used for the Al reference electrode, as described previously, and the CNT network was connected with the Al input and output electrodes. The CNTs were doped to p-type by adsorbing O.sub.2 acceptors from the atmosphere, capped by a Parylene-C polymer film, and patterned by photolithography with a SU-8 photoresist and O.sub.2 RIE.

(77) Operation and Testing Methods

(78) The reference electrodes of the exemplary CNT synstors were always electrically grounded during the tests. When no voltage signals are applied on the input and output electrodes of the synstors, the input and output electrodes are also electrically grounded. Current-voltage (I-V) characteristics were measured by a Keithley 4200 semiconductor parameter analyzer. The electrical voltage signals (V.sub.i and V.sub.o) applied to the input and output electrodes of the devices and circuits were generated by a field programmable gate array (FPGA), computer-controlled modules (National Instruments), and a Tektronix AFG3152C waveform/function generator. Currents flowing through synstors were measured by a semiconductor parameter analyzer, computer-controlled circuit modules (National Instruments), and oscilloscope (Tektronix). The DC conductance of the devices was derived from the currents measured by applying negative voltage signals with a duration of 5 ms and a magnitude equal to the voltages applied for learning. Testing protocols were programmed (NI LabVIEW) and implemented in an embedded field-programmable gate array (FPGA, Xilinx), a microcontroller, and a reconfigurable I/O interface (NI CompactRIO).

(79) The exemplary devices and circuits were simulated by Technology Computer-Aided Design (TCAD) simulator (Sentaurus Device, Synopsys). The simulator performed numerical simulations of device physics based on partial differential equations of electrostatics, quantum mechanics, and carrier transport under a set of boundary conditions defined by device structures, and electronic properties and band diagrams were extracted from the simulations. Transient and quasi-stationary simulations were conducted under different voltage biases on the Al input/output electrodes with respect to the grounded reference electrodes. The electric properties and power consumptions of the circuits were also analyzed by the simulations.

(80) Exemplary Physical Models and Testing Results of Signal Processing in Synstor Embodiments

(81) In exemplary embodiments a voltage pulse with an amplitude of V.sub.a and a duration of t.sub.d applied on the input electrode of a synstor at the moment t=t.sub.n charges the capacitor between the CNT network and Al reference electrode, C.sub.CNT/Al, and induces a change of the current through the CNT network toward the grounded output electrode of the synstor, ΔI(t)≈w V.sub.p[1−e.sup.−β.sup.p.sup.(t−t.sup.n.sup.)], where w denotes the DC conductance of the synstor, and β.sub.p denotes a parameter related to C.sub.CNT/Al and the resistance to charge the CNT network. After the pulse ends at t=t.sub.o+t.sub.d, the capacitor is gradually discharged with a current flowing mainly toward the output electrode, I(t)≈I(t.sub.n+t.sub.d)e.sup.−β.sup.d.sup.(t−t.sup.n.sup.−n.sup.d.sup.), where β.sub.d denotes a parameter related to C.sub.CNT/Al and the resistance to discharge the CNT network. A series of voltage pulses trigger a current from the synstor, I(t)=κ{circle around (*)}(wV.sub.i), where κ{circle around (*)}(wV.sub.i) represents the temporal convolution between κ(t) and wV.sub.i(t), V.sub.i(t)=Σ.sub.n V.sub.aδ(t−t.sub.n), and the kernel function,

(82) $\begin{array}{cc}\kappa \left(t\right)=\{\begin{array}{cc}1-e^{-{\beta }_{p}t}& \mathrm{when}t\le t_d\\ \left(1-e^{-{\beta }_p{t}_d}\right)e^{-{\beta }_{d}t}& \mathrm{when}t>t_d\end{array}& \left(\mathrm{EQ}.5\right)\end{array}$

(83) In some exemplary embodiments, the currents triggered by periodic voltage pulses with an amplitude V.sub.a=−1.75 V, a period of 30 ns, and different durations (8-20 ns) were measured versus time (as discussed below in relation to FIGS. 8A and 8B). The currents were fitted by EQs. 1 and EQ. 5 with β.sub.p=0.67 MHz when t.sub.d=10 ns; β.sub.p=0.47 MHz when t.sub.d=15 ns. When the pulse duration increased, β.sub.p decreased. The CNT resistor connected with the input electrode to charge the capacitor has a much larger Schottky barrier and resistance than the CNT resistor connected with the output electrode to discharge the capacitor, leading to longer charging than discharging times, thus β.sub.p<<β.sub.d. β.sub.p and β.sub.d could be modified by adjusting the resistance and capacitance values in accordance with embodiments.

(84) Exemplary Physical Models and Testing Results of Learning and Memory in Synstor Embodiments

(85) In various exemplary embodiments, as shown in the simulated electronic band structures in FIG. 9C (or FIG. 9D), a pair of negative (or positive) V.sub.i and V.sub.o voltage signals on the input and output electrodes of a CNT synstor with V.sub.i=V.sub.o=−1.75 V (or V.sub.i=V.sub.o=1.75 V) increases (or decreases) the Fermi energy of the CNT network, and induces a difference of +1.66 eV (or −1.59 eV) between the CNT and TiO.sub.2 Fermi energies (FIG. 10A), which injects electrons into (or depletes electrons from) the TiO.sub.2 charge-storage layer by electronic hopping through the HfO.sub.2 dielectric barrier layer. The changes of the charge density in the TiO.sub.2 layer, Δρ.sub.s, induced by the paired V.sub.i and V.sub.o voltages with V.sub.i=V.sub.o were measured by capacitance-voltage tests on a CNT synstor, and plotted as a function of V.sub.i and V.sub.o in FIG. 10B. When the synstor experienced V.sub.i and V.sub.o voltages with V.sub.i=V.sub.o≥0.92 V and V.sub.i=V.sub.o<−0.85 V, Δρ.sub.s increased versus V.sub.i, V.sub.o. When the synstor experienced V.sub.i and V.sub.o voltages with 0.92 V≥V.sub.i=V.sub.o≥−0.85 V, the external voltage signals did not drive a significant amount of electrons to overcome the potential barrier in the HfO.sub.2 layer, therefore, no significant charge modification in the charge storage layer was observed (Δρ.sub.s≈0) (FIG. 10B). When the synstor experienced V.sub.i and V.sub.o voltages with V.sub.i=V.sub.o≥0.92 V and V.sub.i=V.sub.o≤−0.85 V, the negative (or positive) charges in the storage layer attract (repel) the holes in the p-type semiconducting CNT network (FIG. 11A), and increase (or decrease) the device conductance w exponentially versus the magnitudes of V.sub.i and V.sub.o voltages. When a series of paired V.sub.i and V.sub.o pulses with V.sub.i=V.sub.o were applied, p.sub.s was also modified by the external potential as a function of the number of the applied voltage pulses, n. p.sub.s also gradually builds up an internal potential against the external potential, resulting in Δw(n)/w.sub.0 to change as a logarithm function of n (FIG. 11B). The Fermi energies of the p-type CNT, Al, and TiO.sub.2 materials are approximately equal (with differences less than 0.2 eV), resulting in the symmetric Fermi energy differences, and similar charge and conductance modification rates by the positive and negative voltages with the equal magnitude. When a series of paired V.sub.i and V.sub.o voltage pulses with the same amplitudes (i.e. V.sub.i=V.sub.o) were applied on the CNT synstor simultaneously, w was modified by following the learning algorithm {dot over (w)}=α V.sub.i.Math.V.sub.o(EQ. 2).

(86) In various exemplary embodiments, as shown in the simulated electronic band structures in FIGS. 9E to 9G, when V.sub.i and V.sub.o voltages with V.sub.i.Math.V.sub.o≤0 were applied on a CNT synstor, its electronic band structures were also simulated under the conditions of (1) V.sub.i=−1.75 V and V.sub.o=1.75 V (FIG. 9E), (2) V.sub.i=−1.75 V and V.sub.o=0 (FIG. 9F), (3) V.sub.i=1.75 V and V.sub.o=0 (FIG. 9G), and (4) V.sub.i=0 and V.sub.o=0 (FIG. 9B). Under these V.sub.i and V.sub.o voltages, the positive V.sub.i or V.sub.o voltage mainly drops across the reverse-biased Schottky contact between the Al electrode and p-type CNTs, and the negative V.sub.i or V.sub.o voltage mainly drops across the hole-depletion region on the lateral space beyond the TiO.sub.2 charge storage layer/Al reference electrode, which leads to small differences (≤0.23 eV) between the Fermi energies of the CNT network and the recessed TiO.sub.2 layer (FIG. 10A). The changes of the charge density in the TiO.sub.2 layer, Δρ.sub.s, induced by the V.sub.i and V.sub.o voltages under −2 V≤V.sub.i≤2 V and V.sub.o=0 were measured by capacitance-voltage tests on a CNT synstor, and plotted as a function of V.sub.i and V.sub.o in FIG. 10B. When the synstor experienced V.sub.i and V.sub.o voltages with V.sub.i≠0 and V.sub.o=0, the observed charge density changes, |Δρ.sub.s|<25 nF/cm.sup.2, which are less than 15% of the charge density changes induced by the paired pulses with the same magnitude (FIG. 10B). The conductance of the CNT synstors were tested under V.sub.i.Math.V.sub.o≤0 by applying 50 pairs of various 5 ms-wide V.sub.i and V.sub.o pulses under the conditions: (1) −2 V<V.sub.i<2 V and V.sub.o=0; (2) −2 V<V.sub.o<2 V and V.sub.i=0; and (3) −2 V<V.sub.i=−V.sub.o<2 V. It was observed that w remained unchanged under these conditions (FIG. 11A), which indicates that the synstor has a nonvolatile memory of w (i.e. {dot over (w)}≈0 (EQ. 2) under V.sub.i.Math.V.sub.o<0. When a series of 10 ns-wide V.sub.i and V.sub.o pulses with V.sub.i=0 or V.sub.o=0 were applied on the CNT synstor, the average percentage changes of the conductances, |Δw/w.sub.0|≤3.3% (FIG. 11B). The experimental tests indicated that when the CNT synstor experienced V.sub.i and V.sub.o pulses under the condition V.sub.i.Math.V.sub.o<0, the V.sub.i or V.sub.o potential was below the threshold values to modify the charge stored in the TiO.sub.2 layer, thus {dot over (w)}=0 (EQ. 2) for learning and nonvolatile memory.

(87) In various exemplary embodiments, V.sub.i and V.sub.o voltages with an amplitude V.sub.i=V.sub.o applied on the input and output electrodes of a synstor induce a voltage, V.sub.CNT/TiO2, on the capacitor between the CNT network and TiO.sub.2 charge-storage layer, which in turn modify the charge density, ρ.sub.s, in the charge storage layer by electronic hopping through the HfO.sub.2 layer (as discussed below in relation to FIGS. 9A-9G and FIGS. 10A-10B). In such embodiments, the ρ.sub.s modification rate is equal to the current density of electronic hopping through the HfO.sub.2 layer,

(88) $d{\rho }_s/\mathrm{dt}=\exp \left[\frac{q\left(\theta \sqrt{.Math.V_{CNT/TiO2}.Math.}-{\varphi }_B\right)}{k_{B}T}\right],$
where q denotes the charge of an electron, k.sub.B denotes the Boltzmann constant, T denotes temperature, ϕ.sub.B denotes the potential barrier for electrons to diffuse in the HfO.sub.2 barrier layer, θ denotes a parameter related to the thickness of the HfO.sub.2 layer, and represents a parameter equal to current density under |V.sub.CNT/TiO2|=(ϕ.sub.B/θ).sup.2. I.sup.n exemplary CNT synstors, CNT/HfO.sub.2/TiO.sub.2/HfO.sub.2/Al layers in the synstor are composed of two capacitors connected in series with the CNT/HfO.sub.2/TiO.sub.2 and TiO.sub.2/HfO.sub.2/Al sandwich structures and corresponding capacitance c.sub.CNT/TiO2 and c.sub.TiO2/Al, and V.sub.CNT/TiO2=V.sub.i/ν−ρ.sub.s/(νc.sub.TiO2/Al) with ν=(C.sub.CNT/TiO2+c.sub.TiO2/Al)/c.sub.TiO2/Al. After substituting V.sub.CNT/TiO2 in dρ.sub.s/dt,

(89) $d{\rho }_s/\mathrm{dt}=\exp \left[\frac{q\theta (\sqrt{V_i-{\rho }_s/c_{TiO2/Al}}-\sqrt{V_t^{+}-{\rho }_s^0/c_{TiO2/Al}}}{\sqrt{v}{k}_{B}T}\right]$
under V.sub.i=V.sub.o> V.sub.t.sup.+>0;

(90) $d{\rho }_s/\mathrm{dt}=\exp \left[\frac{q\theta \left(\sqrt{-V_i+{\rho }_s/c_{TiO2/Al}}-\sqrt{.Math.V_t^{-}-{\rho }_s^0/c_{TiO2/Al}.Math.}\right)}{\sqrt{v}{k}_{B}T}\right]$
under V.sub.i=V.sub.o<V.sub.a.sup.t−<0, where V.sub.t.sup.+=ν(ϕ.sub.B/θ).sup.2+ρ.sub.s.sup.0/c.sub.TiO2/Al>0, V.sub.t.sup.−=−ν(ϕ.sub.B/θ).sup.2+ρ.sub.s.sup.0/C.sub.TiO2/Al<0, and ρ.sub.s.sup.0 as ρ.sub.s before the voltage V.sub.a is applied. When V.sub.t.sup.−<V.sub.i=V.sub.o<V.sub.t.sup.+, the external voltage V.sub.i drives an insignificant amount of electrons to overcome the potential barrier in the HfO.sub.2 layer, and |dρ.sub.s/dt|<||≈0. When V.sub.i=V.sub.o> V.sub.t.sup.+ or <V.sub.t.sup.−, the external voltage drives electrons through the potential barrier to modify ρ.sub.s, and ρ.sub.s also gradually builds up an internal potential against the external potential. When ρ.sub.s is modified to balance the external potential with V.sub.i−ρ.sub.s/c.sub.TiO2/Al≈V.sub.t.sup.+−ρ.sub.s.sup.0/c.sub.TiO2/Al or V.sub.i−ρ.sub.s/C.sub.TiO2/Al≈V.sub.t.sup.−−ρ.sub.s.sup.0/c.sub.TiO2/Al, dρ.sub.s/dt=≈0 and ρ.sub.s reaches its saturation values with ρ.sub.s≈ρ.sub.s.sup.0+C.sub.TiO2/Al[V.sub.i−V.sub.t.sup.+] or ρ.sub.s≈ρ.sub.s.sup.0+C.sub.TiO2/Al[V.sub.i−V.sub.t.sup.−]. In the capacitance-voltage test, after a synstor experiences multiple voltage pulses with V.sub.i=V.sub.o on its input and output electrodes, the modification of the charge densities in the synstor,

(91) $\begin{array}{cc}\Delta {\rho }_s\approx \{\begin{array}{cc}{c}_{\mathrm{TiO}2/\mathrm{Al}}\left[V_i-V_t^{+}\right]& \mathrm{when}{V}_i=V_o>V_t^{+}>0\\ 0& \mathrm{when}{V}_a^{t-}<V_i=V_o<V_t^{+}\\ c_{TiO2/Al}\left[V_i-V_t^{-}\right]& \mathrm{when}{V}_i=V_o<V_t^{-}<0\end{array}& \left(\mathrm{EQ}.6\right)\end{array}$
where Δρ.sub.s=ρ.sub.s−ρ.sub.s.sup.0. The experimental observed Δρ.sub.s data (FIG. 10B) are fitted well by EQ. 6 with Δρ.sub.s=k.sub.ρ.sup.+[V.sub.a−V.sub.t.sup.+] under V.sub.i=V.sub.o> V.sub.t.sup.+>0 and Δρ.sub.s=k.sub.ρ.sup.−[V.sub.a−V.sub.t.sup.−] under V=V.sub.o<V.sub.t.sup.−<0 with k.sub.p.sup.+=−145 nF/cm.sup.2, k.sub.ρ.sup.−=−106 nF/cm.sup.2, V.sub.t.sup.+=0.92V, and V.sub.t.sup.−=−0.85 V.

(92) Multiple V.sub.i and V.sub.o voltage pulses with an amplitude V.sub.i=V.sub.o=V.sub.a applied on the input and output electrodes of an exemplary synstor also can modify ρ.sub.s, and the change of ρ.sub.s, Δρ.sub.s induces the change of the Fermi level of the CNT network, which in turn causes the change of device conductance (as discussed in reference to FIG. 11A, below),

(93) $w\approx w_0\exp \left(\frac{q\Delta V_{\mathrm{CNT}}^f}{k_{B}T}\right),\mathrm{and}\Delta w=w-w_0=w_0\left[\exp \left(\frac{q\Delta V_{\mathrm{CNT}}^f}{k_{B}T}\right)-1\right],$
where w.sub.0 denotes the initial device DC conductance before the charge modification, and qΔV.sub.CNT.sup.f denotes the change of the CNT Fermi level induced by Δρ.sub.s. ΔV.sub.CNT.sup.f increases monotonically with −Δρ.sub.s in the p-type CNTs, and its linear approximation gives ΔV.sub.CNT.sup.f≈−ε.sub.ρ.sup.+Δρ.sub.s when Δρ.sub.s>0 and ΔV.sub.CNT.sup.f≈−ε.sub.ρ.sup.−Δρ.sub.s when Δρ.sub.s<0, where ε.sub.ρ.sup.+ and ε.sub.ρ.sup.− denote constants related to the device structure, capacitance, CNT doping concentration. After substituting ΔV.sub.CNT.sup.f in Δw by Δρ.sub.s in EQ. 6,

(94) $\begin{array}{cc}\frac{\Delta w}{w_0}\approx \{\begin{array}{cc}{e}^{-{\beta }_v^{+}\left(V_i-V_t^{+}\right)}-1& \mathrm{when}{V}_i=V_o\ge V_t^{+}>0\\ 0& \mathrm{when}{V}_a^{t-}<V_i=V_o<V_t^{+}\\ e^{-{\beta }_v^{-}\left(V_i-V_t^{-}\right)}-1& \mathrm{when}{V}_i=V_o\le V_t^{-}<0\end{array}& \left(\mathrm{EQ}.7\right)\end{array}$
where β.sub.v.sup.+=qε.sub.ρ.sup.+c.sub.TiO2/Al/k.sub.BT and β.sub.v.sup.−=qε.sub.ρ.sup.−c.sub.TiO2/Al/k.sub.BT. The experimental data, Δw/w.sub.0, (FIG. 11A) were fitted by EQ. 7, Δw/w.sub.0=e.sup.β.sup.v.sup.+.sup.(V.sup.i.sup.−V.sup.t.sup.+.sup.)−1 with β.sub.v.sup.+=4.06/V and V.sub.t.sup.+=1.05 V under V.sub.i=V.sub.o> V.sub.t.sup.+; and Δw/w.sub.0=e.sup.−β.sup.v.sup.−.sup.(V.sup.i.sup.−V.sup.t.sup.−.sup.)−1 with β.sub.v.sup.−=3.69/V and V.sub.t.sup.−=−0.81 V under V.sub.i=V.sub.o<V.sub.t.sup.−; Δw≈0 under V.sub.t.sup.+> V.sub.i=V.sub.o> V.sub.t.sup.−.

(95) When a series of V.sub.i and V.sub.o voltage pulses with V.sub.i=V.sub.o are applied, ρ.sub.s is modified by the pulses as a function of the number of the applied pulses, n (as discussed below in relation to FIG. 11B, below). The modification rate,

(96) 0$\frac{d{\rho }_s}{dn}=t_d\frac{d{\rho }_s}{dt}=t_d\exp \left[\frac{q\left(\theta \sqrt{.Math.V_i-{\rho }_s/c_{TiO2/Al}.Math.}-\sqrt{v}{\varphi }_B\right)}{\sqrt{v}{k}_{B}T}\right]$
with t.sub.d as the pulse duration. The solution of the differential equation gives

(97) ${\rho }_s\left(n\right)\approx {\eta }^{+}\mathrm{Ln}\left(\frac{n}{n_0^{+}}+1\right)+{\rho }_s^0$
with

(98) ${\eta }^{+}=2\sqrt{v}kT{c}_{\mathrm{TiO}2/\mathrm{Al}}\sqrt{V_i-{\rho }_s^0/c_{TiO2/Al}}/\left(q\theta \right),\mathrm{and}{n}_0^{+}={\eta }^{+}\exp \left[\frac{q{\varphi }_B}{k_{B}T}\right]/\left(t_d\right)\mathrm{under}{V}_a\ge V_t^{+}>0.{\rho }_s\left(n\right)\approx -{\eta }^{-}\mathrm{Ln}\left(\frac{n}{n_0^{-}}+1\right)+{\rho }_s^0\mathrm{with}{\eta }^{-}=2\sqrt{v}kT{c}_{\mathrm{TiO}2/\mathrm{Al}}\sqrt{-V_i+{\rho }_s^0/c_{TiO2/Al}}/\left(q\theta \right)\mathrm{and}{n}_0^{-}={\eta }^{-}\exp \left[\frac{q{\varphi }_B}{k_{B}T}\right]/\left(t_d\right)\mathrm{under}{V}_a\le V_t^{-}<0.{\mathrm{\Delta \rho }}_s\left(n\right)={\rho }_s\left(n\right)-{\rho }_s^0$
induces the shift of the CNT Fermi energy qΔV.sub.CNT.sup.f(n), which in turn induces

(99) $\Delta w\left(n\right)=w_0\left[\exp \left(\frac{q\Delta V_{\mathrm{CNT}}^f\left(n\right)}{k_{B}T}\right)-1\right]\approx \frac{w_{0}q\Delta V_{CNT}^f\left(n\right)}{k_{B}T}=\frac{w_{0}q{\epsilon }_{\rho }^{\pm }}{k_{B}T}\Delta {\rho }_s\left(n\right)=\frac{w_0{\eta }^{\pm }q{\epsilon }_{\rho }^{\pm }}{k_{B}T}\mathrm{Ln}\left(\frac{n}{n_0^{\pm }}+1\right).$
Therefore,

(100) $\begin{array}{cc}\frac{\Delta w\left(n\right)}{w_0}\approx \{\begin{array}{cc}{\kappa }^{+}\mathrm{Ln}\left(\frac{n}{n_0^{+}}+1\right)& \mathrm{when}{V}_i=V_o\ge V_t^{+}>0\\ 0& \mathrm{when}{V}_a^{t-}<V_i=V_o<V_t^{+}\\ {\kappa }^{-}\mathrm{Ln}\left(\frac{n}{n_0^{-}}+1\right)& \mathrm{when}{V}_i=V_o\le V_t^{-}<0\end{array}& \left(\mathrm{EQ}.8\right)\end{array}$
where

(101) ${\kappa }^{+}=\frac{q{\eta }^{+}{\epsilon }_{\rho }^{+}}{k_{B}T}\mathrm{and}{\kappa }^{-}=\frac{q{\eta }^{-}{\epsilon }_{\rho }^{-}}{k_{B}T}.$
The experimental data, Δw(n)/w.sub.0, (FIG. 11B) were fitted well by EQ. 8,

(102) $\Delta w\left(n\right)/w_0=k_n^{+}\mathrm{Ln}\left(\frac{n}{n_0^{+}}+1\right)\mathrm{with}{k}_n^{+}=7.5\mathrm{and}{n}_0^{+}=1.7\times 10^3\mathrm{for}{V}_i=V_o=1.75V;\mathrm{and}\mathrm{by}\Delta w\left(n\right)/w_0=k_n^{-}\mathrm{Ln}\left(\frac{n}{n_0^{-}}+1\right)\mathrm{with}{k}_n^{-}=15.3\mathrm{and}{n}_0^{-}=1.76\times 10^5\mathrm{for}{V}_i=V_o=-1.75V.$

(103) Synstors were modified to its high and low conductance values, w.sub.H and w.sub.L, by applying 50 pairs of 5 ms-wide V.sub.i and V.sub.o pulses with V.sub.i=V.sub.o=−1.75 V and V.sub.i=V.sub.o=1.75 V alternatively in 2930 modification cycles, and no deterioration of device conductance modification was observed (FIG. 11C).

(104) 108 synstors on a chip were modified to w.sub.H and w.sub.L respectively, and the distributions of w.sub.H and w.sub.L values are shown in FIG. 11D. The average w.sub.H value, w.sub.H1.9 nS, and the standard deviation of w.sub.H, σ.sub.H=0.44 nS. w.sub.L<0.2 nS, which is the limit of the measurement module.

(105) After synstors were modified to different analog conductances, w.sub.0, the nonvolatile memory of the synstors was examined by measuring their conductances versus time over 1.75×10.sup.5 s at room temperature. Within the test period, the average percentage changes of the conductances |Δw/w.sub.0|≈3%, and the extrapolations of the experimental data indicate their long-term (˜10 years) nonvolatile analog memory (FIG. 11E).

(106) Simulations of Nanoscale Synstors

(107) Nanoscale synstors have been simulated by Technology Computer-Aided Design (TCAD) simulator (Sentaurus Device, Synopsys). The cross-sectional structure of a simulated synstor composed of a 200 nm-wide p-type semiconducting CNT network channel formed contacts with an Al input and an Al output electrodes is shown in FIG. 12A. The CNT network is on a 2.5 nm-thick HfO.sub.2 dielectric layer on a 1.0 nm-thick TiO.sub.2 charge storage layer on a 4.5 nm-thick HfO.sub.2 dielectric layer on an Al reference electrode. There is a 50 nm lateral space between the Al reference electrode/TiO.sub.2 charge storage layer and the Al input and output electrodes, and the TiO.sub.2 charge storage layer is also laterally recessed with respect to the Al reference electrode by 20 nm at both ends. The simulated electronic band diagrams along the Al input electrode/CNT/Al output electrode under various V.sub.i, the voltage on the input electrode, and V.sub.o, the voltage on the output electrode are shown in FIGS. 12B to 12F.

(108) When a pair of negative V.sub.i and V.sub.o pulses with V.sub.i=V.sub.o=−1.75 V are applied on the input and output electrodes of the 200 nm CNT synstor simultaneously, the negative voltage on the CNT network with respect to the Al reference electrode inverts the p-type CNTs above the Al reference electrode to n-type CNTs, and moves the edge of the CNT conduction band close to the Fermi level of the Al input/output electrodes (FIG. 12B). The capacitance between a single CNT in the network and the continuous TiO.sub.2 charge-storage layer is much smaller than the capacitance between the TiO.sub.2 layer and the Al reference electrode. Therefore, the negative voltage between the CNT network with respect to the Al reference electrode predominantly drops across the CNT network and the TiO.sub.2 charge-storage layer, which induces an average difference of 1.51 eV between the CNT and TiO.sub.2 Fermi energies (FIG. 13A), and drives electrons from the CNT network into the TiO.sub.2 charge-storage layer through the 2.5 nm-thick HfO.sub.2 dielectric layer to increase the negative charge in the TiO.sub.2 layer. Based on the TCAD simulation, the negative V.sub.i and V.sub.o voltages with V.sub.i=V.sub.o=−1.75 V modify the charge in the TiO.sub.2 layer to a density of −6.86 μC/cm.sup.2 (FIG. 13B), which attracts holes in the CNT network, increasing the device conductance, w. When a pair of positive V.sub.i and V.sub.o pulses with V.sub.i=V.sub.o=1.75 V are applied on the input and output electrodes of the 200 nm CNT synstor simultaneously, the positive voltage on the CNT network with respect to the Al reference electrode induces hole accumulation in the p-type CNTs above the Al reference electrode FIG. 12C). The positive voltage between the CNT network with respect to the Al reference electrode predominantly drops across the CNT network and the TiO.sub.2 charge storage layer, which induces a difference of −1.51 eV between the CNT and TiO.sub.2 Fermi energies (FIG. 13A), and drives electrons from the TiO.sub.2 charge storage layer to the CNT network through the 2.5 nm-thick HfO.sub.2 dielectric layer (FIG. 12C). Based on the TCAD simulation, the positive V.sub.i and V.sub.o voltages with V.sub.i=V.sub.o=1.75 V modify the charge in the TiO.sub.2 layer to a density of 5.14 μC/cm.sup.2 (FIG. 13B), which attracts holes in the CNT network, increasing the device conductance, w.

(109) Electronic band diagrams were also simulated by TCAD when a pair of V.sub.i and V.sub.o pulses are applied on the input and output electrodes of the synstor with the 200 nm-wide CNT network under the different conditions: (1) V.sub.i=−1.75 V and V.sub.o=1.75 V (FIG. 12D); (2) V.sub.i=1.75 V and V.sub.o=−1.75 V (not shown, but symmetric to FIG. 12D); (3) V.sub.i=1.75 V and V.sub.o=0 (FIG. 12E); (4) V.sub.i=0 V and V.sub.o=1.75 V (not shown, but symmetric to FIG. 12E); (5) V.sub.i=−1.75 V and V.sub.o=0 (FIG. 12F); (6) V.sub.i=0 V and V.sub.o=−1.75 V (not shown, but symmetric to FIG. 12F). Under the V.sub.i.Math.V.sub.o≤0 conditions, the V.sub.i and/or V.sub.o voltages mainly drops across the hole-depletion region on the lateral space beyond the TiO.sub.2 charge storage layer (FIGS. 12D-12F), which leads to small Fermi energy differences (c 0.15 eV) between the CNTs and the recessed TiO.sub.2 layer across the HfO.sub.2 dielectric layer (FIG. 13A). Based on the TCAD simulation, the small Fermi energy differences cannot drive electrons to tunnel through the 2.5 nm-thick HfO.sub.2 dielectric layer (FIG. 13B). Thus, the charge stored in the TiO.sub.2 layer cannot be modified by V.sub.i and V.sub.o pulses with V.sub.i.Math.V.sub.o<0, and the synstor conductance, w, remains unchanged. Based on the TCAD simulation, when the synstor is scaled down to 200 nm, it still functions properly for signal processing, learning, and memory.

(110) The cross-sectional structure of a simulated synstor composed of a 40 nm-wide p-type semiconducting CNT network channel formed contacts with an Al input and an Al output electrode is shown in FIG. 12G. The CNT network is on a 1.5 nm-thick HfO.sub.2 dielectric layer on a 0.5 nm-thick TiO.sub.2 charge storage layer on a 2.5 nm-thick HfO.sub.2 dielectric layer on an Al reference electrode. There is a 10 nm lateral space between the Al reference electrode and the Al input and output electrodes, and the TiO.sub.2 charge storage layer is also laterally recessed with respect to the Al reference electrode by 2.5 nm at both ends (FIG. 12G).

(111) The simulated electronic band diagrams along the Al input electrode/CNT/AI output electrode under various V.sub.i, the voltage on the input electrode, and V.sub.o, the voltage on the output electrode of the 40 nm CNT synstor are shown in FIG. 12H-I. In the synstor learning mode, when a pair of negative V.sub.i and V.sub.o pulses with V.sub.i=V.sub.o=−0.5 V are applied on the input and output electrodes of a synstor simultaneously, the negative voltage on the CNT network with respect to the Al reference electrode inverts the p-type CNTs above the Al reference electrode to n-type CNTs, and moves the edge of the CNT conduction band close to the Fermi level of the Al input/output electrodes (FIG. 12H). The negative voltage between the CNT network with respect to the Al reference electrode predominantly drops across the CNT network and the TiO.sub.2 charge-storage layer, which induces a difference of 0.43 eV between the CNT and TiO.sub.2 Fermi energies (FIG. 13C), and drives electrons from the CNT network into the TiO.sub.2 charge-storage layer through the 1.5 nm-thick HfO.sub.2 layer (FIG. 13D). Based on the TCAD simulation, the negative V.sub.i and V.sub.o voltages with V.sub.i=V.sub.o=−0.5 V modify the charge in the TiO.sub.2 layer to a density of −3.06 μC/cm.sup.2 (FIG. 13D), which attracts the holes in the CNT network above the TiO.sub.2 layer, increasing the device conductance, w. When a pair of positive V.sub.i and V.sub.o pulses with V.sub.i=V.sub.o=0.5 V are applied on the input and output electrodes of a synstor simultaneously, the positive voltage on the CNT network with respect to the Al reference electrode induce hole accumulation in the p-type CNTs above the Al reference electrode (FIG. 12I). The positive voltage between the CNT network with respect to the Al reference electrode predominantly drops across the CNT network and the TiO.sub.2 charge storage layer, which induces a difference of −0.43 eV between the CNT and TiO.sub.2 Fermi energies (FIG. 13C), and drives electrons from the TiO.sub.2 charge storage layer to the CNT network through the 1.5 nm-thick HfO.sub.2 dielectric layer (FIG. 12I). Based on the TCAD simulation, the positive V.sub.i and V.sub.o voltages with V.sub.i=V.sub.o=0.5 V modify the charge in the TiO.sub.2 layer to a density of 2.93 μC/cm.sup.2 (FIG. 13D), which repels the holes in the CNT network above the TiO.sub.2 layer, decreasing the device conductance, w.

(112) Electronic band diagrams were also simulated by TCAD when a pair of V.sub.i and V.sub.o pulses are applied on the input and output electrodes of the 40-nm synstor under different conditions: (1) V.sub.i=−0.5 V and V.sub.o=0.5 V (FIG. 12J); (2) V.sub.i=0.5 V and V.sub.o=−0.5 V (not shown, but symmetric to FIG. 12J); (3) V.sub.i=0.5 V and V.sub.o=0 (FIG. 12K); (4) V.sub.i=0 V and V.sub.o=0.5 V (not shown, but symmetric to FIG. 12K); (5) V.sub.i=−0.5 V and V.sub.o=0 (FIG. 12I); (6) V.sub.i=0 V and V.sub.o=−0.5 V (not shown, but symmetric to FIG. 12I). Under the V.sub.i.Math.V.sub.o≤0 conditions, the V.sub.i and/or V.sub.o voltages mainly drops across the hole-depletion region on the lateral space beyond the TiO.sub.2 charge storage layer (FIG. 12J-L), which leads to small Fermi energy differences (≤0.11 eV) between the CNTs and the recessed TiO.sub.2 layer across the HfO.sub.2 dielectric layer (FIG. 13C). The small Fermi energy differences cannot drive electrons to tunnel through the 1.5 nm-thick HfO.sub.2 dielectric layer, causing ignorable changes of the charges in the TiO.sub.2 layer (FIG. 13D). Since the charge stored in the TiO.sub.2 layer cannot be modified by V.sub.i and V.sub.o pulses with V.sub.i.Math.V.sub.o<0, the synstor conductance, w, remains unchanged. Based on the TCAD simulation, when the synstor is scaled down to 40 nm, it still functions properly for concurrent signal processing, learning, and memory.

(113) I.sup.n summary, in this exemplary embodiment, the CNT synstor is composed of a p-type semiconducting CNT network which formed Schottky contacts with Al input and output electrodes as a resistor, and a recessed TiO.sub.2 charge storage layer embedded in a HfO.sub.2 dielectric layer sandwiched between an Al reference electrode and the CNT network as a capacitor. For signal processing, a synstor processes a set of voltage pulses, V.sub.i(t), on its input electrode by charging the capacitor during the pulses, and discharging the capacitor after the pulses, and triggering a current via the CNT resistor, I(t)=κ{circle around (*)}(wV.sub.l) (EQ. 1) on its grounded output electrode (V.sub.o=0). When a set of paired V.sub.i and V.sub.o voltage pulses with the same amplitude (i.e. V.sub.i=V.sub.o) are applied on the CNT synstor simultaneously, w is modified by following {dot over (w)}=αV.sub.i V.sub.o (EQ. 2). The paired negative (positive) voltage pulses generate a potential difference between the CNT network and TiO.sub.2 layer to increase (decrease) the electronic charge stored in the TiO.sub.2 layer, which in turn attracts (repels) the holes in the p-type semiconducting CNT network to increase (decrease) its conductance with α>0 (α<0). Otherwise, when a synstor experiences V.sub.i and V.sub.o pulses under the condition V.sub.i.Math.V.sub.o≤0, the V.sub.i or V.sub.o potential mainly drops beyond the TiO.sub.2 charge storage layer/Al reference electrode, and the magnitudes of the potential differences between the CNT network and the recessed TiO.sub.2 layer are below the threshold values to modify the charge stored in the TiO.sub.2 layer, thus {dot over (w)}=0 (EQ. 2) for learning and nonvolatile memory. Based on simulation of nanoscale devices, microscale synstors in this exemplary embodiment can potentially be miniaturized to nanoscale (˜40 nm).

(114) Exemplary Synstor Circuits

(115) The concurrent signal processing and learning of synstors according to embodiments were demonstrated in an exemplary 4×2 crossbar circuit, as shown schematically in FIG. 14A, composed of 72 synstors and 2 integrate-and-fire “neuron” circuits with the functions according to the Hodgkin-Huxley neuron model. In this exemplary embodiment, nine synstors were connected in parallel with an input, an output, and a reference electrode with serpentine structures at each cross point of the electrodes to reduce noises from the devices (FIG. 14B).

(116) Original speech signals consisted of unlabeled “yes” and “no” utterances were pre-processed to generate the set of voltage pulses, V.sub.i.sup.m(t), input to the crossbar synstor circuit (FIG. 14A). The input pulses had an amplitude of 1.75 V or −1.75 V, a duration of 10 ns, and firing rates, r.sub.i.sup.m, proportional to mel frequency cepstral coefficients (MFCCs) of the speech signals at the different frequency ranges (FIG. 14C). The synstor circuit processed the −1.75 V V.sub.i.sup.m(t) pulses and triggered currents by following I.sup.n(t) Σ.sub.m κ.sup.nm{circle around (*)}(w.sup.nmV.sup.m) (EQ. 3) under V.sub.o.sup.n=0, which flowed into the integrate-and-fire “neuron” circuits to trigger 10 ns-wide±1.75 V back-propagating voltage pulses, V.sub.o.sup.n(t), on the output electrodes (FIG. 14D), and forwarding-propagating 1.0 V output pulses, V.sub.f.sup.n(t) (FIG. 14E). The firing rates of the V.sub.f.sup.n pulses, r.sub.f.sup.n, increased monotonically as a nonlinear sigmoid function of I.sup.n. When a V.sub.f.sup.n pulse was triggered from the n.sup.th“neuron” as a “winner” (i.e. r.sub.f.sup.n>r.sub.f.sup.n′, n≠n′), a series of 10 ns-wide −1.75 V V.sub.o pulses was triggered on the n.sup.th output electrode of the “winner”, and then a series of 10 ns-wide 1.75 V V.sub.o pulses was triggered on the n′.sup.th output electrode of the “loser” (FIGS. 14D and 14E). To reduce the currents in the circuit, no voltage pulses with opposite polarity were applied on the input and output electrodes simultaneously. In the parallel unsupervised learning process, when the sets of V.sub.i.sup.m and V.sub.o.sup.n voltage pulses encountered each other in the synstors (FIG. 14F), the conductance matrix [W.sup.nm].sup.N,M was modified by following EQ. 4 and a “winner-take-all” learning algorithm, {dot over (w)}.sup.nmαV.sub.i.sup.mV.sub.o.sup.n ∝(r.sub.f.sup.n−r.sub.f.sup.n′)r.sub.i.sup.m, resulting in the change of

(117) $r_f^n,\delta r_f^n\propto \{\begin{array}{cc}\left({\overline{r}}_{f,Y}^n-{\stackrel{\_}{r}}_{f,Y}^{n^{\prime }}\right)& \mathrm{for}“\mathrm{yes}”\\ \left({\overline{r}}_{f,N}^n-{\stackrel{\_}{r}}_{f,N}^{n^{\prime }}\right)& \mathrm{for}“\mathrm{no}”\end{array},$
with r.sub.f,Y.sup.n and r.sub.f,N.sup.n as the average firing rates of the V.sub.f.sup.n pulses triggered by “yes” word and “no” words, respectively. Before learning started (i.e. V.sub.o=0 when t<16 s), the “yes” and “no” words triggered V.sub.f pulses from the two “neurons”, which were not orthogonal or distinguishable (FIG. 14E). After the learning started (t>16 s), the “yes” words triggered V.sub.f pulses with r.sub.f,Y.sup.2>rf.sub.f,Y.sup.1, thus “neuron” 2 was the “winner” with δr.sub.f,Y.sup.2∝(r.sub.f,Y.sup.2−r.sub.f,Y.sup.1)>0, and r.sub.f,Y.sup.2 increased and stabilized at {circumflex over (r)}.sub.f,Y.sup.2≈16 Hz; δr.sub.f,Y.sup.1∝(r.sub.f,Y.sup.1−r.sub.f,Y.sup.2)<0, and r.sub.f,Y.sup.1 decreased to {circumflex over (r)}.sub.f,Y.sup.1=0. The “no” words triggered the V, pulses with r.sub.f,N.sup.1>r.sub.f,N.sup.2, thus the “neuron” 1 was the “winner” with δr.sub.f,N.sup.1∝(r.sub.f,N.sup.1−r.sub.f,N.sup.2)>0 and r.sub.f,N.sup.1 increased and stabilized at {circumflex over (r)}.sub.f,N.sup.1≈14 Hz; δr.sub.f,N.sup.2∝(r.sub.f,N.sup.2−r.sub.f,N.sup.1)<0, and r.sub.f,N.sup.2 decreased to {circumflex over (r)}.sub.f,N.sup.2=0 (FIG. 14E). After the circuit processed and learnt from 2-3 unlabeled speech signals, the “yes” and “no” speech signals were stably mapped to two distinguishable orthogonal sets of output pulses with average firing rates

(118) ${\stackrel{.fwdarw.}{\hat{r}}}_{f,Y}\approx \left[\begin{array}{c}0\\ 16\end{array}\right]\mathrm{Hz}\mathrm{and}{\stackrel{.fwdarw.}{\hat{r}}}_{f,N}\approx \left[\begin{array}{c}14\\ 0\end{array}\right]\mathrm{Hz}.$

(119) The 4×2 crossbar synstor circuit in this exemplary embodiment was demonstrated for concurrent signal processing and learning from “yes” and “no” speech signals. The speech signals were converted to a set of input voltage pulses, {right arrow over (V)}.sub.i, processed by the synstor circuit in parallel to generate output currents (EQ. 3), which in turn triggered sets of forward-propagating output voltage pulses, {right arrow over (V)}.sub.f, from the connected integrate-and-fire “neuron” circuits for signal processing, and back-propagating voltage pulses, {right arrow over (V)}.sub.o, on the output electrodes of the synstor circuit. During the signal processing, the conductance matrix [w.sup.nm].sup.N,M of the synstor circuit was concurrently modified by following the correlative learning algorithm (EQ. 4) in a parallel learning process, leading to the orthogonal sets of output {right arrow over (V)}.sub.f voltage pulses to distinguish “yes” and “no” speech signals. As demonstrated in this exemplary embodiment, a synstor circuit can execute spatiotemporal signal processing (EQ. 3) and correlative learning (EQ. 4) algorithms concurrently with high energy efficiency by circumventing the fundamental computing limitations in existing electronic circuits such as physically separated logic and memory units, data transmission between memory and logic, the execution of the signal processing and learning algorithms in serial mode in different circuits, and the signal transmissions between the circuits.

(120) In comparison with computers, the equivalent computing operations in a M×N synstor circuit shown in FIG. 5 are approximately equal to 3MN to implement the signal processing algorithm (EQ. 3), and 3MN to implement the learning algorithm (EQ. 4). The speed for the circuit to implement 6MN signal processing and learning operations in parallel analog mode,
v.sub.s=6MNf.sub.s  (EQ. 9)
where f.sub.s denotes the circuit operation frequency. With f.sub.s=50 MHz, the 4×2 synstor circuit in this exemplary embodiment operated at a speed of 2.4×10.sup.9 FLOPS (FIG. 15).

(121) The total power consumption of an M×N synstor circuit shown in FIG. 5,
P.sub.s≈MNwV.sub.a.sup.2D.sub.p+NE.sub.pr.sub.f  (EQ. 10)
where w denotes the average conductance of the synstors in the circuit, V.sub.a denotes the voltage pulse magnitude, D.sub.p is a unitless coefficient related to the input and output voltage signals, E.sub.p denotes the average energy consumption to switch the transistors in a “neuron” circuit to trigger an output voltage pulse and modulate back-propagating V.sub.o pulses, and r.sub.f denotes the average firing rate of the output V.sub.f pulses from the “neuron” circuit. Based on the experimental results and circuit simulation, P.sub.s≈15 nW for the 4×2 crossbar synstor circuit in this exemplary embodiment with w≈1.9 nS, V.sub.a=1.75 V, D.sub.p≈0.32, and E.sub.p≈28 fJ.

(122) The energy efficiency of an M×N synstor circuit shown in FIG. 5 is equal to its speed (EQ. 9) divided by its power consumption (EQ. 10),
F.sub.s=6f.sub.s/(wV.sub.a.sup.2D.sub.p+E.sub.pr.sub.f/M)  (EQ. 11)
As shown in FIG. 15, the equivalent computing energy efficiency of the 4×2 synstor circuit in this exemplary embodiment is 1.6×10.sup.17 FLOPS/W, which exceeds the energy efficiencies of digital transistor circuits such as Summit Supercomputer, TPU from Google, and Volta V100 GPU from Nvidia (˜10.sup.13 FLOPS), and the memristor circuit from UMass/HP and PCM circuits from IBM (˜10.sup.9-10.sup.11 FLOPS/W), and of the analog neuromorphic circuits of memristors and PCM (˜10.sup.5-10.sup.14 FLOPS/W, excluding learning algorithm computations). The energy consumption of a synstor circuit decreases with decreasing synstor conductance v (EQ. 11); therefore the energy efficiency of the synstor circuit can be further improved by decreasing synstor conductance (FIG. 15).

(123) In digital serial mode, transistors operate at high conductance (˜10.sup.5 nS) in order to reduce computing latency (˜10.sup.−9 s) and enhance accuracy; in analog parallel mode, synstors (synapses) operate at low conductance (c 2 nS), and the computing latency and accuracy of an M×N synstor (synapse) circuit increase with increasing M and N, the numbers of parallel input/output electrodes (see, e.g., FIGS. 16A and 16B). The phase shifts of the pulses and the sneak currents in an M×N crossbar synstor circuit increase with increasing circuit scale, M and N, which limits M,N≤10.sup.4 for concurrent signal processing and learning in parallel, and can be improved by decreasing the conductance of synstors, and the resistance and capacitance of input/output electrodes.

(124) The speed of an M×N crossbar synstor circuit (FIG. 5) increases with increasing circuit scale, M and N (EQ. 9). With the energy efficiency equal to the 4×2 circuit in this exemplary embodiment, a 2 k×2 k circuit with a power consumption of ˜10 mW (EQ. 10) has a projected speed of ˜10.sup.15 FLOPS (FIG. 17), exceeding the speeds of digital transistor circuits such as TPU from Google, Volta V100 GPU from Nvidia, and Stratrix 10 FPGA from Intel (˜10.sup.13 FLOPS), and the memristor circuit from UMass/HP, and PCM circuits from IBM (˜10.sup.12-10.sup.14 FLOPS).

(125) The microscale synstor circuit in this exemplary embodiment has a computing performance density of ˜1.3×10.sup.11 FLOPS/mm.sup.2, which is superior to that of nanoscale transistor circuits (˜10.sup.9-10.sup.11 FLOPS/mm.sup.2) such as TPU from Google, Volta V100 GPU from Nvidia, and Stratrix 10 FPGA from Intel, and inferior to that of nanoscale memristor and PCM circuits (˜10.sup.9-10.sup.12 FLOPS/mm.sup.2). Based on simulation of nanoscale devices, synstors can potentially be miniaturized to nanoscale (˜40 nm) with a projected performance density of ˜10.sup.17 FLOPS/mm.sup.2.

(126) There is “plenty of room at the bottom” to miniaturize synstor size, scale up synstor circuits, improve their energy efficiency, speed, power consumption, and uniformity for concurrent signal processing and learning from “big data” in intelligent systems.

DOCTRINE OF EQUIVALENTS

(127) This description of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the teaching above. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications. This description will enable others skilled in the art to best utilize and practice the invention in various embodiments and with various modifications as are suited to a particular use. The scope of the invention is defined by the following claims.

(128) As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. Reference to an object in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.”

(129) As used herein, the term “set” refers to a collection of one or more objects. Thus, for example, a set of objects can include a single object or multiple objects.

(130) As used herein, the terms “substantially” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. When used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to +2%, less than or equal to +1%, less than or equal to +0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” aligned can refer to a range of angular variation of less than or equal to ±10°, such as less than or equal to 5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to 2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to 0.1°, or less than or equal to ±0.05°.

(131) Additionally, amounts, ratios, and other numerical values may sometimes be presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified. For example, a ratio in the range of about 1 to about 200 should be understood to include the explicitly recited limits of about 1 and about 200, but also to include individual ratios such as about 2, about 3, and about 4, and sub-ranges such as about 10 to about 50, about 20 to about 100, and so forth.