SEMICONDUCTOR MODULE

Abstract

A semiconductor module includes a high-side switching device and a low-side switching device that respectively form an upper arm and a lower arm, freewheeling diodes that are respectively connected to the switching devices in anti-parallel, and a high-side driver circuit and a low-side driver circuit that respectively switch the high-side switching device and the low-side switching device ON and OFF. In the upper arm, an anode electrode of the freewheeling diode and a reference voltage electrode of the high-side driver circuit are directly connected via a first wiring, and the anode electrode of the freewheeling diode is connected to a reference voltage electrode of the high-side switching device via a second wiring having an inductance.

Claims

1. A semiconductor module, comprising: a high-side switching device and a low-side switching device that respectively form an upper arm and a lower arm; a high-side freewheeling diode and a low-side freewheeling diode that are respectively connected to the high-side and low-side switching devices in anti-parallel; and a high-side driver circuit and a low-side driver circuit that respectively switch the high-side switching device and the low-side switching device ON and OFF, wherein an anode electrode of the high-side freewheeling diode and a reference voltage electrode of the high-side driver circuit are directly connected via a first wiring, and wherein the anode electrode of the high-side freewheeling diode is electrically connected to a reference voltage electrode of the high-side switching device via a second wiring having an inductance.

2. The semiconductor module according to claim 1, wherein the inductance of the second wiring is parasitic inductance of the wiring itself.

3. The semiconductor module according to claim 1, wherein the first wiring is a wire that is bonded to the anode electrode of the high-side freewheeling diode.

4. The semiconductor module according to claim 1, wherein the high-side switching device is an insulated-gate bipolar transistor (IGBT), and said reference electrode of the high-side switching device is an emitter electrode of the IGBT.

5. The semiconductor module according to claim 1, further comprising: an insulating substrate having the high-side driver circuit mounted thereon, a top surface of the high-side driver circuit having the reference voltage electrode; a conductive circuit pattern on the insulating substrate, the conductive circuit pattern being arranged in an area on the insulating substrate that is separate from an area on which the high-side driver circuit is mounted; and a conductive terminal pattern as an external terminal on the insulating substrate, the conductive terminal pattern being arranged in an area on the insulating substrate that is separate from the areas on which the high-side driver circuit and the conductive circuit pattern are respectively disposed, wherein the high-side switching device is an insulated-gate bipolar transistor (IGBT) that has, on a top surface thereof, an emitter electrode that corresponds to said reference voltage electrode of the high-side switching device and a gate electrode and that has a collector electrode on a bottom surface thereof, and the IGBT is mounted on the conductive circuit pattern so that the collector electrode is in contact with a top surface of the conductive circuit pattern and the emitter electrode and the gate electrode are accessible from above, wherein the high-side freewheeling diode connected to the high-side switching device has said anode electrode on a top surface thereof and a cathode electrode on a bottom surface thereof, and the high-side freewheeling diode is mounted on the conductive circuit pattern in an area that is separate from an area on which the IGBT is mounted so that the cathode electrode is in contact with the conductive circuit pattern and electrically connected to the collector electrode of the high-side switching device via the conductive circuit pattern and the anode electrode is accessible from above, wherein the first wiring directly connects the anode electrode on the top surface of the high-side freewheeling diode and the reference voltage electrode on the top surface thereof of the high-side driver circuit from above, wherein the second wiring directly connects the anode electrode on the top surface of the high-side freewheeling diode and the emitter electrode on the top surface of the IGBT, and wherein a bonding wire is provided to directly connect the anode electrode on the top surface of the high-side freewheeling diode and the conductive terminal pattern.

6. The semiconductor module according to claim 5, wherein the high-side driver circuit, the IGBT, the high-side freewheeling diode, and the conductive terminal pattern are arranged in that order along a straight line in a plan view.

7. The semiconductor module according to claim 1, wherein the first wiring has an inductance, and wherein the first wiring and the second wiring are arranged such that magnetic coupling occurs between the first wiring and the second wiring when the high-side switching device is switched ON and OFF.

8. A semiconductor module, comprising: a high-side switching device and a low-side switching device that respectively form an upper arm and a lower arm; a high-side freewheeling diode and a low-side freewheeling diode that are respectively connected to the high-side and low-side switching devices in anti-parallel; and a high-side driver circuit and a low-side driver circuit that respectively switch the high-side switching device and the low-side switching device ON and OFF, wherein an anode electrode of the high-side freewheeling diode and a reference voltage electrode of the high-side driver circuit are directly connected via a first wiring having an inductance, wherein the anode electrode of the high-side freewheeling diode is directly connected to a reference voltage electrode of the high-side switching device via a second wiring having an inductance, and wherein the first wiring and the second wiring are arranged such that magnetic coupling occurs between the first wiring and the second wiring when the high-side switching device is switched ON and OFF.

9. The semiconductor module according to claim 8, wherein the first wiring and the second wiring are arranged such that currents flowing therethrough are in phase.

10. The semiconductor module according to claim 8, wherein the inductance of the first wiring and the inductance of the second wiring are respectively parasitic inductance of the first wiring itself and parasitic inductance of the second wiring itself.

11. The semiconductor module according to claim 8, further comprising: an insulating substrate having the high-side driver circuit mounted thereon, a top surface of the high-side driver circuit having the reference voltage electrode; a conductive circuit pattern on the insulating substrate, the conductive circuit pattern being arranged in an area on the insulating substrate that is separate from an area on which the high-side driver circuit is mounted; and a conductive terminal pattern as an external terminal on the insulating substrate, the conductive terminal pattern being arranged in an area on the insulating substrate that is separate from the areas on which the high-side driver circuit and the conductive circuit pattern are respectively disposed, wherein the high-side switching device is an insulated-gate bipolar transistor (IGBT) that has, on a top surface thereof, an emitter electrode that corresponds to said reference voltage electrode of the high-side switching device and a gate electrode and that has a collector electrode on a bottom surface thereof, and the IGBT is mounted on the conductive circuit pattern so that the collector electrode is in contact with a top surface of the conductive circuit pattern and the emitter electrode and the gate electrode are accessible from above, wherein the high-side freewheeling diode connected to the high-side switching device has said anode electrode on a top surface thereof and a cathode electrode on a bottom surface thereof, and the high-side freewheeling diode is mounted on the conductive circuit pattern in an area that is separate from an area on which the IGBT is mounted so that the cathode electrode is in contact with the conductive circuit pattern and electrically connected to the collector electrode of the high-side switching device via the conductive circuit pattern and the anode electrode is accessible from above, wherein the first wiring directly connects the anode electrode on the top surface of the high-side freewheeling diode and the reference voltage electrode on the top surface thereof of the high-side driver circuit from above, wherein the second wiring directly connects the anode electrode on the top surface of the high-side freewheeling diode and the emitter electrode on the top surface of the IGBT, wherein the second wiring is a pair of wiring lines that each directly connect the anode electrode of the high-side freewheeling diode and the emitter electrode the IGBT, and the pair of wiring lines sandwich the first wiring in a plan view so as to produce the magnetically coupling between the first wiring and the second wiring, and wherein a bonding wire is provided to directly connect the anode electrode on the top surface of the high-side freewheeling diode and the conductive terminal pattern.

12. The semiconductor module according to claim 11, wherein the high-side driver circuit, the IGBT, the high-side freewheeling diode, and the conductive terminal pattern are arranged in that order along a straight line in the plan view.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG. 1 is a circuit diagram of a semiconductor module (IPM) according to an embodiment of the present invention and a conventional example.

[0037] FIG. 2A is a wiring diagram of the primary components of the IPM according to Embodiment 1 of the present invention, and FIG. 2B is a circuit diagram of the same.

[0038] FIG. 3A is a waveform comparison diagram of the voltage VCE, FIG. 3B is a waveform comparison diagram of the current IC, and FIG. 3C is a waveform comparison diagram of the gate voltage VGE, respectively when a high-side IGBT in the IPM is switched off in Embodiment 1 and a reference example.

[0039] FIG. 4 is a circuit diagram of an IGBT according to Comparison Example of the present invention (a comparison example relative to FIGS. 2A and 2B).

[0040] FIGS. 5A and 5B are drawings for explaining the differences between the effects of the circuit configurations illustrated in FIGS. 2B and 4, where FIG. 5A illustrates a reverse recovery current path for the circuit configuration illustrated in FIG. 4 and FIG. 5B illustrates a reverse recovery current path for the circuit configuration illustrated in FIG. 2B.

[0041] FIG. 6A is a wiring diagram of the primary components of an IPM according to Embodiment 2 of the present invention, and FIG. 6B is a circuit diagram of the same.

[0042] FIG. 7 is an explanatory drawing of the operation and effects of Embodiment 2.

[0043] FIG. 8A is a waveform comparison diagram of the voltage VCE, FIG. 8B is a waveform comparison diagram of the current IC, and FIG. 8C is a waveform comparison diagram of the gate voltage VGE, respectively when the high-side IGBT in the IPM is switched off in the reference example, Embodiments 1 and 3.

[0044] FIG. 9A is a wiring diagram of the primary components of the IPM according to the reference example, and FIG. 9B is a circuit diagram of the same.

[0045] FIGS. 10A to 10C are explanatory drawings of the switching loss that occurs at turn-on and turn-off of an IGBT (a typical switching device), where FIG. 10A is a waveform diagram of the collector-emitter voltage (VCE) of the IGBT, FIG. 10B is a waveform diagram of the collector current (IC) of the IGBT, and FIG. 10C is an explanatory drawing of the periods in which switching loss occurs.

[0046] FIGS. 11A to 11C are explanatory drawings of the Miller period, where FIG. 11A is a waveform diagram of the voltage VCE of an IGBT at turn-off, FIG. 11B is a waveform diagram of the current IC at this time, and FIG. 11C illustrates the gate voltage VGE waveform and the Miller period.

[0047] FIG. 12 is a drawing for explaining the concept of parasitic inductance in wires connected to the emitters of IGBTs.

[0048] FIG. 13A is a waveform diagram of the voltages VCE of a high-side IGBT and a lowside IGBT at turn-off, and FIG. 13B is a waveform diagram of the currents IC of the same.

[0049] FIGS. 14A to 14C illustrate the relationship between the magnitude of a gate resistance Rg, the surge voltage at turn-off of an IGBT, and the Miller period, where FIG. 14A is a waveform diagram of the voltage VCE, FIG. 14B is a waveform diagram of the current IC, and FIG. 14C is a waveform diagram of the gate voltage VGE.

DETAILED DESCRIPTION OF EMBODIMENTS

[0050] Embodiment 1 of the present invention will be described with reference to figures. Note that the overall circuit configuration of a semiconductor module (IPM) 1 according to the present embodiment is the same as is illustrated for the conventional example in FIG. 1 and therefore will not be described in detail here. Moreover, the following description focuses on a high-side circuit, and therefore the terms high-side and low-side will be omitted.

Embodiment 1

[0051] FIG. 2A illustrates the interior module wiring configuration of the IPM 1 according to Embodiment 1, and FIG. 2B illustrates the circuit configuration of the same. Note that although FIGS. 2A and 2B illustrate the U-phase circuit among the three phases as a representative example, the same configuration can be applied to the other phases as well.

[0052] As illustrated in FIG. 2A, in the IPM 1, an HVIC 6u (6v, 6w) and an external terminal U (V, W) are arranged on an insulating substrate, and between the HVIC 6u (6v, 6w) and the external terminal U (V, W), an IGBT 2u (2v, 2w) and an FWD 4u (4v, 4w) are arranged in that order from the HVIC 6u (6v, 6w) side.

[0053] Moreover, a reference voltage Vs of the HVIC 6u (6v, 6w) is connected to the anode of the FWD 4u (4v, 4w) via a bonding wire 9u (9v, 9w). Furthermore, an output OUT of the HVIC 6u (6v, 6w) is connected to the gate of the IGBT 2u (2v, 2w) via a bonding wire 10u (10v, 10w). The emitter of the IGBT 2u (2v, 2w) is connected to the anode of the FWD 4u (4v, 4w) via a bonding wire 11u (11v, 11w), and the anode of the FWD 4u (4v, 4w) is connected to the external terminal U (V, W) via a bonding wire 12u (12v, 12w). In addition, the collector of the IGBT 2u (2v, 2w) is connected to the cathode of the FWD 4u (4v, 4w) via a circuit pattern 16u (16v, 16w).

[0054] Moreover, although in FIG. 2A the two parallel bonding wires 11u (11v, 11w) and 12u (12v, 12w) are used, any number of wires can be used as appropriate given the current capacity of those wires.

[0055] The bonding wires, the IGBT device, and the FWD device have the inductances illustrated in FIG. 2B. In FIG. 2B, Li and Lf respectively represent the internal inductance of the IGBT 2u (2v, 2w) and the FWD 4u (4v, 4w), L2 represents the wire inductance of the bonding wire 11u (11v, 11w) between the emitter of the IGBT 2u (2v, 2w) and the anode of the FWD 4u (4v, 4w), and L4 represents the wire inductance of the bonding wire 12u (12v, 12w) to the external terminal U (V, W) of the IPM 1. Moreover, L1 represents the wire inductance of the bonding wire 9u (9v, 9w) between the anode of the FWD 4u (4v, 4w) and the reference voltage of the HVIC 6u (6v, 6w).

[0056] Next, the effects of the wiring configuration of the semiconductor module (IPM) 1 will be described in comparison to those of a reference example illustrated in FIGS. 9A and 9B.

[0057] In the wiring configuration of the IPM 1 of the present embodiment as illustrated in FIGS. 2A and 2B, the inductance between the emitter E (reference voltage) of the IGBT 2u (2v, 2w) and the reference voltage Vs of the HVIC 6u (6v, 6w) is Li+L2+L1. Meanwhile, in the wiring configuration of the reference example illustrated in FIGS. 9A and 9B, the inductance between the emitter E of the IGBT 2u (2v, 2w) and the reference voltage Vs of the HVIC 6u (6v, 6w) is Li+L1. Typically, L1 and L1 are either substantially equal or, as in the configuration illustrated in FIG. 2A in which the IGBT 2u (2v, 2w) is arranged between the HVIC 6u (6v, 6w) and the FWD 4u (4v, 4w), L1 is greater. Therefore, in the wiring configuration of the present embodiment, the inductance between the emitter E of the IGBT 2u (2v, 2w) and the reference voltage Vs of the HVIC 6u (6v, 6w) is greater than the inductance in the reference example by at least an amount equal to the inductance L2. In other words, the wiring configuration of the present embodiment produces a counter-electromotive force (due to the -di/dt at turn-off of the IGBT) which is greater than a counter-electromotive force in the reference example by an amount corresponding to at least the inductance L2, thereby biasing the gate of the IGBT 2u (2v, 2w) to a greater degree. This reduces the magnitude of the slope di/dt at turn-off of the IGBT in the present embodiment than in the reference example, thereby allowing the present embodiment to achieve a greater reduction in surge voltage than in the reference example by a corresponding amount.

[0058] Note that the electromotive force produced by an inductance L can be calculated using the formula L.Math.di/dt. Therefore, when di/dt=1000 A/s, using a bonding wire having a wire inductance of 5 to 10 nH as the inductance L2 makes it possible to achieve a reduction of approximately 5 to 10 V in the surge voltage.

[0059] FIGS. 3A to 3C illustrate the changes in the voltage VCE, current IC, and voltage VGE waveforms over time at turn-off of the IGBT 2u (2v, 2w) in the wiring configuration of the present embodiment in comparison to in the reference example. In FIGS. 3A to 3C, the solid lines represent the waveforms in the present embodiment and the dashed lines represent the waveforms in the reference example. As illustrated in FIG. 3A, the peak value of the surge voltage VCE (surge) in the circuit of the present embodiment is less than the peak value of the surge voltage VCE (surge) in the circuit of the reference example. In other words, the circuit of the present embodiment keeps the slope dV/dt during the period from t1 to t2 (the Miller period) as well as during the subsequent period until t3 the same as in the reference example but also makes it possible to reduce the subsequent surge voltage VCE (surge).

[0060] Moreover, as illustrated in FIG. 3B, the magnitude of the slope di/dt is smaller in the present embodiment than in the reference example. Furthermore, as illustrated in FIG. 3C, the Miller period (from t1 to t2) is the same in both circuits.

[0061] By using the wiring configuration of the semiconductor module (IPM) according to the present embodiment as described above, in a circuit configuration in which a freewheeling diode (FWD) is connected in anti-parallel to a switching device (IGBT), the inductance increases on the emitter side of the IGBT without changing the gate resistance Rg of the IGBT. This makes it possible to reduce the surge voltage VCE (surge) without increasing the length of the Miller period and while also keeping the switching loss during the Miller period approximately the same as in conventional configurations.

[0062] Moreover, the wiring configuration illustrated in FIGS. 2A and 2B makes it possible to directly connect the anode electrode of the FWD 4u (4v, 4w) to the reference voltage electrode of the HVIC 6u (6v, 6w) via the bonding wire 9u (9v, 9w). Therefore, by using a bonding wire for which the inductance (L1) is appropriately adjusted, it is possible to set the inductance Li+L2+L1 between the emitter of the IGBT 2u (2v, 2w) and the reference voltage of the HVIC 6u (6v, 6w) to a value sufficiently greater than an inductance value in conventional configurations and to thereby adjust the magnitude of the slope di/dt at turn-off of the IGBT to a desired value which is less than the magnitude of the slope di/dt in conventional configurations. For the inductance L1 between the anode of the FWD 4u (4v, 4w) and the reference voltage of the HVIC 6u (6v, 6w), an inductor may be inserted or the parasitic inductance of the wire can be used.

[0063] In particular, in a configuration in which the IGBT 2u (2v, 2w) is arranged between the HVIC 6u (6v, 6w) and the FWD 4u (4v, 4w) as in FIG. 2, the reference voltage terminal (Vs) of the HVIC 6u (6v, 6w) is directly connected to the anode terminal of the FWD 4u (4v, 4w) via the bonding wire 9u (9v, 9w), which increases the parasitic inductance (L1) of the bonding wire and thereby makes it possible to easily reduce the surge voltage VCE (surge).

[0064] Furthermore, connecting the emitter electrode of the IGBT 2u (2v, 2w) to the anode electrode of the FWD 4u (4v, 4w) via a bonding wire makes it possible to adjust the inductance L2 in addition to the inductance L1.

Comparison Example

[0065] In the configuration illustrated in FIGS. 2A and 2B, the reference voltage electrode of the HVIC 6u (6v, 6w) and the anode electrode of the FWD 4u (4v, 4w) are directly wire-bonded together. However, as illustrated in FIG. 4, an external inductance Lex can also be inserted between the emitter electrode of the IGBT 2u (2v, 2w) and the reference voltage of the HVIC 6u (6v, 6w). In the circuit configuration illustrated in FIG. 4, the inductance between the emitter E (reference voltage) of the IGBT 2u (2v, 2w) and the reference voltage Vs of the HVIC 6u (6v, 6w) is Li+Lex+L1. In other words, the inductance on the emitter side of the IGBT 2u (2v, 2w) is greater than in the circuit configuration of the reference example illustrated in FIGS. 9A and 9B by an amount equal to Lex. This increases the IGBT gate bias by a corresponding amount and makes it possible to reduce di/dt.

[0066] Similar to the wiring configuration illustrated in FIGS. 2A and 2B, the wiring configuration illustrated in FIG. 4 makes it possible to increase only the inductance on the emitter side without changing the resistance value of the gate resistance Rg of the IGBT. Therefore, Comparison Example similarly makes it possible to reduce the surge voltage VCE (surge) at turn-off without increasing the loss that occurs during the Miller period.

[0067] It should be noted that the wiring configuration illustrated in FIG. 4 results in an increase in reverse recovery current in comparison to the wiring configuration illustrated in FIGS. 2A and 2B. Here, reverse recovery current refers to the current which flows during the instant at which a voltage applied to a freewheeling diode (FWD) switches from being a forward voltage to being a reverse voltage, and the magnitude of this reverse voltage current is determined by the inductance of the current path formed by the freewheeling diode (FWD).

[0068] As illustrated by the current path shown in FIG. 5A, the inductance during the reverse recovery current period in the circuit configuration illustrated in FIG. 4 is Lf+L2+Lex+L4. Meanwhile, the inductance during the reverse recovery current period in the circuit configuration illustrated in FIG. 9B is Lf+L4. Therefore, although the circuit configuration of Comparison Example illustrated in FIG. 4 reduces the surge voltage VCE (surge) at turn-off, this configuration also exhibits the disadvantage of increasing surge voltage during the recovery period of the FWD.

[0069] Meanwhile, as illustrated by the current path shown in FIG. 5B, in the circuit configuration illustrated in FIG. 2 the inductance during the reverse recovery current period is Lf+L4, which is the same as in the reference example illustrated in FIG. 6. Therefore, the circuit configuration illustrated in FIG. 2 does not exhibit this disadvantage of increasing surge voltage during the recovery period of the FWD relative to in the reference example.

[0070] As described above, in the semiconductor module according to the present embodiments, increasing the inductance on the emitter side of the IGBT makes it possible to reduce the surge voltage VCE (surge) at turn-off without increasing the loss that occurs during the Miller period. Furthermore, the circuit configuration illustrated in FIGS. 2A and 2B, in which the anode electrode of the freewheeling diode (FWD) is directly connected to the reference voltage electrode of the driver circuit (HVIC) via a bonding wire, exhibits the practically advantageous effect of making it possible to achieve the above advantage without increasing the surge voltage during the recovery period.

Embodiment 2

[0071] Next, Embodiment 2 of the present invention will be described. In the present embodiment, in contrast to the wiring configuration illustrated in FIG. 2A, the bonding wire 9u (9v, 9w) having the inductance L1 and the bonding wire 11u (11v, 11w) having the inductance L2 are arranged neighboring one another. The resulting magnetic coupling between the inductances L1 and L2 creates a counter-electromotive force in the inductance L1 of the bonding wire 9u (9v, 9w) at turn-off of the IGBT 2u (2v, 2w), and this counter-electromotive force is utilized to reduce the gate drive capability of the IGBT 2u (2v, 2w) and to thereby reduce the surge voltage VCE (surge) at turn-off.

[0072] FIG. 6A illustrates the interior module wiring configuration of an IPM 1 according to Embodiment 2 of the present embodiment, and FIG. 6B illustrates the circuit configuration of the same. Note that although FIG. 6A illustrates the U-phase circuit among the three phases as a representative example, the same configuration can be applied to the other phases as well.

[0073] The wiring configuration of the present embodiment is specifically characterized in that the bonding wire 9u (9v, 9w) is bonded to a substantially center position between the terminals of the FWD 4u (4v, 4w) for the two bonding wires 11u (11v, 11w). Selecting the position at which the bonding wire 9u (9v, 9w) is connected to the FWD 4u (4v, 4w) in this manner makes it possible to pass the bonding wire 9u (9v, 9w) (which extends from the reference voltage Vs of the HVIC 6u (6v, 6w) to the FWD 4u (4v, 4w)) between the two bonding wires 11u (11v, 11w), thereby making it possible to establish a segment (hereinafter, a parallel wiring segment) in which the bonding wires 9u (9v, 9w) and 11u (11v, 11w) are wired parallel to one another with no more than a prescribed interval therebetween. Moreover, in this parallel wiring segment of the wiring configuration illustrated in FIG. 6A, the currents respectively flowing through the bonding wires 9u (9v, 9w) and 11u (11v, 11w) are in phase.

[0074] The bonding wires 9u (9v, 9w) and 11u (11v, 11w) respectively have an inductance L1 and L2. The parasitic inductance of the wires can be used as this inductance. In this case, the intervals between the bonding wires 9u (9v, 9w) and 11u (11v, 11w) as well as the length of the parallel wiring segment affect the magnitude of the counter-electromotive force resulting from mutual inductance or magnetic coupling. In other words, reducing the intervals between the bonding wires 9u (9v, 9w) and 11u (11v, 11w) or increasing the length of the parallel wiring segment makes it possible to increase the mutual inductance between the bonding wires 9u (9v, 9w) and 11u (11v, 11w) as well as the counter-electromotive force resulting therefrom.

[0075] Next, the operation and effects of the wiring configuration illustrated in FIG. 6A will be described with reference to FIG. 7. Among the components of the IPM 1, FIG. 7 only depicts the components that are required to explain magnetic coupling. In this figure, the current (i1) flowing from the reference voltage electrode (Vs) of the HVIC 6u (6v, 6w) via the bonding wire 9u (9v, 9w) and the current (i2) flowing from the emitter of the IGBT 2u (2v, 2w) are in phase, as indicated by the arrows pointing in the same direction.

[0076] In this circuit configuration, when the IGBT 2u (2v, 2w) switches OFF, the current (i2) begins to decrease. As a result, the mutual inductance with the bonding wire 11u (11v, 11w) creates a counter-electromotive force (equal to the magnitude of the mutual inductance times the time rate of change of the current i2) in the magnetically coupled bonding wire 9u (9v, 9w), thereby causing an increase in the emitter voltage of the IGBT 2u (2v, 2w) relative to the reference voltage Vs of the HVIC 6u (6v, 6w). This biases the gate of the IGBT 2u (2v, 2w) and thereby reduces the gate drive capability of the HVIC 6u (6v, 6w). In other words, in the wiring configuration illustrated in FIG. 6A, the magnetic coupling between the bonding wires 11u (11v, 11w) and the bonding wire 9u (9v, 9w) acts to increase the respective inductances L2 and L1 thereof. This, as shown by the dot-dashed lines in FIGS. 8A to 8C, reduces the magnitude of the time rate of change di/dt of the collector current at turn-off, thereby reducing the surge in VCE (surge).

[0077] Practically speaking, for bonding wires 9u (9v, 9w) and 11u (11v, 11w) both having a normal current capacity, it is preferable that the interval therebetween be approximately 3 mm or less (preferably, 1.5 mm or less) and that the length of the parallel wiring segment be 10 mm or greater (preferably, 15 mm or greater).

[0078] Under these conditions, for a di/dt of 1000 A/s, a reduction of approximately 20 V in VCE surge can be expected relative to in conventional configurations (the reference example).

[0079] Moreover, although in FIG. 6A the bonding wire 11u (11v, 11w) is constituted by two wiring lines and the bonding wire 9u (9v, 9w) is arranged at a substantially center position therebetween, the number of bonding wiring lines 11u (11v, 11w) is not limited to this and may be any number n (where n is an integer greater than or equal to 2), in which case n-1 bonding wires 9u (9v, 9w) may be respectively arranged between the bonding wires 11u (11v, 11w). Meanwhile, if the current capacity of the bonding wire 11u (11v, 11w) is sufficient, a single wire may be used. In this case, the bonding wire 9u (9v, 9w) is connected to near the position at which the bonding wire 11u (11v, 11w) is connected to the FWD 4u (4v, 4w).

[0080] The present embodiment as described above exhibits the following advantageous effects in addition to those of Embodiment 1. In the present embodiment, the circuit is configured such that, without changing the gate resistance, the wire going from the emitter terminal of the IGBT to the anode terminal of the FWD is magnetically coupled to the wire going from the reference voltage terminal (Vs) of the HVIC to the anode terminal of the FWD. Therefore, the electromotive force induced at turn-off of the IGBT decreases the gate drive capability of the IGBT, thereby making it possible to reduce -di/dt as illustrated in FIG. 8B. This, in turn, makes it possible to reduce VCE (surge) without increasing switching loss. Moreover, in comparison to Embodiment 1, the same degree of reduction in VCE (surge) can be achieved using a shorter wire length, thereby making it possible to miniaturize the IPM package.

[0081] The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the invention. For example, although above an NPN IGBT was used as the semiconductor switching device as an example and circuits in which the emitter terminal was the reference voltage electrode of the IGBT were described, the present invention is equally applicable when using a PNP IGBT and working with a circuit in which the collector terminal is the reference voltage electrode of the IGBT.

[0082] Moreover, the present invention is similarly applicable when using semiconductor switching devices other than IGBTs, such as bipolar transistors and MOSFETs. Here, when using an NMOS, the reference voltage electrode would be the source electrode, and when using a PMOS, the reference voltage electrode would be the drain electrode.

[0083] The bonding wires should be bonded to positions on the wiring patterns that respectively have the same voltages as the anode terminal of the FWD, the reference voltage terminal of the HVIC, and the reference voltage terminal of the IGBT. The switching devices or the freewheeling diodes or both can be made of any of silicon, silicon carbide, a gallium nitride material, a gallium oxide material, or diamond.

[0084] It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover modifications and variations that come within the scope of the appended claims and their equivalents. In particular, it is explicitly contemplated that any part or whole of any two or more of the embodiments and their modifications described above can be combined and regarded within the scope of the present invention.