DETECTION CIRCUIT FOR PHOTO SENSOR WITH STACKED SUBSTRATES

Abstract

Embodiments relate to a stacked photo sensor assembly where two substrates are stacked vertically. The two substrates are connected via interconnects at a pixel level to provide a signal from a photodiode at a first substrate to circuitry on a second substrate. The circuitry on the second substrate performs operations that were conventionally performed on first substrate. More specifically, charge storage of the first substrate is replaced with capacitors on the second substrate. A voltage signal corresponding to the amount of charge in the first substrate is generated and processed in the second substrate. By stacking the first and second substrates, the photo sensor assembly can be made more compact while increasing or at least retaining the photodiode fill factor of the photo sensor assembly.

Claims

1. A pixel in a photo sensor, comprising: a portion of a first substrate including a photodiode, a floating diffusion point, and a first transistor between the photodiode and the floating diffusion point to transfer charge from the photodiode to the floating diffusion point responsive to turning on the first transistor; a portion of a second substrate including a current source, a conductive line, a first switch selectively coupling the conductive line to the floating diffusion point, and a first capacitor configured to store a signal voltage responsive to turning on the first switch, the second substrate overlapping the first substrate, the signal voltage representing an amount of charge transferred from the photodiode to the floating diffusion point; and a pixel level interconnect between the floating diffusion point and the conductive line to carry the signal voltage.

2. The pixel of claim 1, wherein the portion of the second substrate further comprises a second switch selectively coupling the conductive line to the floating diffusion point, and a second capacitor configured to store a reset voltage responsive to turning on the second switch.

3. The pixel of claim 2, wherein the first switch is turned on and the second switch is turned off to store the signal voltage in the first capacitance.

4. The pixel of claim 2, wherein the first substrate further comprises: a first reset transistor configured to reset a voltage at the floating diffusion point responsive to turning on the first reset transistor after an exposure period; and an amplifier having an input terminal connected to the floating diffusion point and an output terminal connected to the pixel level interconnect.

5. The pixel of claim 4, wherein the amplifier is a source follower transistor.

6. The pixel of claim 4, wherein the second substrate further comprises: a second reset transistor configured to reset a voltage at the conductive line responsive turning on of the second reset transistor; and a sense transistor having a gate is connected to the conductive line and a terminal providing an amplified version of the voltage at the conductive line.

7. The pixel of claim 6, wherein the second switch is turned off to store the reset voltage in the second capacitor.

8. The pixel of claim 6, wherein the second substrate further comprises: a read transistor configured to gate the amplified version of the voltage at the conductive line to a readout circuit outside the pixel.

9. The pixel according to claim 1, wherein the floating diffusion point is configured to reset after each cycle of an exposure period and a sensing period.

10. The pixel according to claim 1, wherein the current source is turned on during a portion of a sensing period subsequent to an exposure period and turned off during a remaining portion of the sensing period.

11. A method for operating a pixel, the method comprising: turning on a first transistor during an exposure period; transferring charge from a photodiode to a floating diffusion point in a first substrate responsive to turning on the first transistor; generating a signal voltage at the first substrate, the signal voltage representing an amount of charge transferred from the photodiode to the floating diffusion point; carrying a signal voltage between the floating diffusion point and a conductive line in a second substrate via a pixel level interconnect; and storing the signal voltage in a first capacitor in the second substrate responsive to turning on a first switch, the second substrate overlapping the first substrate;

12. The method of claim 11, the method further comprising: storing a reset voltage in a second capacitor responsive to turning on a second switch.

13. The method of claim 12, the method further comprising: storing the signal voltage in the first capacitor responsive to turning on the first switch and turning off the second switch;

14. The method of claim 12, the method further comprising: resetting a voltage at the floating diffusion point responsive to turning on a first reset transistor after the exposure period;

15. The method of claim 12, the method further comprising: resetting a voltage at a conductive line responsive to turning on a second reset transistor; and providing an amplified version of the voltage at the conductive line via a sense transistor;

16. The method of claim 15, the method further comprising: storing a reset voltage in the second capacitor responsive to turning off the second switch and turning on the second reset transistor;

17. The method of claim 15, the method further comprising: transferring the amplified version of the voltage at the conductive line to a readout circuit outside the pixel via a read transistor.

18. The method of claim 11, the method further comprising: resetting the floating diffusion point after each cycle of an exposure period and a sensing period.

19. The method of claim 11, the method further comprising: turning on a current source during a portion of a sensing period subsequent to an exposure period; and turning off the current source during a remaining portion of the sensing period.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 is a high-level block diagram illustrating the electronic device, according to one embodiment.

[0008] FIG. 2 is a view illustrating the sensor architecture, according to one embodiment.

[0009] FIG. 3 is a cross-sectional view illustration the stacked photo assembly, according to one embodiment.

[0010] FIG. 4 is a circuit diagram illustrating the circuitry of a pixel of the photo sensor, according to one embodiment.

[0011] FIG. 5 is a timing diagram illustrating signals associated with the operation of a photo sensor pixel, according to one embodiment.

[0012] FIG. 6 is a process flow diagram illustrating a method for operating a pixel, according to one embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Reference will now be made in detail to the preferred embodiment, an example of which is illustrated in the accompanying drawings. Whenever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

[0014] Embodiments relate to a stacked photo sensor assembly where two substrates that are stacked vertically. The two substrates are connected via interconnects at a pixel level to provide a signal from a photodiode at a first substrate to circuitry on a second substrate. The circuitry on the second substrate performs operations that were conventionally performed on first substrate. More specifically, charge storage of the first substrate is replaced with capacitors on the second substrate. A voltage signal corresponding to the amount of charge in the first substrate is generated and processed in the second substrate.

Example System Architecture

[0015] FIG. 1 is a high-level block diagram illustrating the electronic device, according to one embodiment. In one embodiment, the electronic device 100 includes, among other components, a processor 102 and a photo sensor 104 that are commutatively coupled. The electronic device 100 may include other components not illustrated in FIG. 1 such as memory and various other sensors.

[0016] The processor 102 is an electronic circuit that performs operations on a data source. The data source may include the photo sensor 104 that provides sensor data 108. The processor 102 generates operation instructions 106 that are sent to the photo sensor 104. The processing performed by the processor 102 may include an analog-digital conversion of the sensor data 108, which converts voltage analog signals or current analog signals into digital signals.

[0017] The photo sensor 104 is a circuit that measures light intensity and performs a photoconversion. Measuring light intensity may involve detecting light by a photodiode and the photoconversion may involve converting the light by the photodiode into a voltage or current signal.

[0018] FIG. 2 is a schematic view illustrating the photo sensor 104, according to one embodiment. The photo sensor 104 includes, among other components, a digital block 202, a global counter 203, a row drivers and global signal drivers module 204, Mobile Industry Processor Interface (MIPI) 205, counter buffers 206, a digital pixel array 207, sense amplifiers 208, a line memory 209, a power conditioner 210, a ramp generation and buffers module 211, and a sense amplification biasing module 212.

[0019] The digital block 202 is a circuit that processes digital signals associated with the operation of the photo sensor 104. In one or more embodiments, at least part of the digital block 202 may be provided as part of the digital pixel array 207 instead of being a circuit separate from the digital pixel array 207.

[0020] The global counter 203 is a digital sequential logic circuit constructed of cascading flip-flops, and provides counter signals to various components of the photo sensor 104.

[0021] The row drivers and global signal drivers module 204 is a circuit that provides signals to rows of pixels via scan lines (not shown). The signal provided to each row of pixels indicates sensing of image signal and/or resetting operations at each row of pixels.

[0022] MIPI 205 is a serial interface for transmitting the sensor data 108 from the photo sensor 104 to the processor 102. An MIPI interface typically has a single clock lane and one or more data lanes (not shown) that carry serial data. These lanes carry signals on pairs of wires where the signals are often differential.

[0023] The counter buffers 206 is a circuit that receives counter signals from the global counter 203, and sends signals to columns of pixels in the digital pixel array 207 to coordinate sensing and resetting operations.

[0024] The digital pixel array 207 includes a plurality of pixels. In one embodiment, the digital pixel array is arranged in two dimensions, addressable by row and column. Each pixel is configured to sense light and output a signal corresponding to the intensity of the input light. Each pixel may include components as described below with reference to FIG. 3.

[0025] The sense amplifiers 208 are elements in the read circuitry that are used to the read out of the digital signals from the digital pixel array 207. The sense amplifiers 208 sense low power signals from a bitline that represents the intensity of light captured by the pixels in the digital pixel array 207. The sense amplifiers 208 may generate a digital output signal by utilizing an analog-to-digital converter (ADC). In one or more embodiments, at least part of the sense amplifiers 208 may be included in the digital pixel array 207.

[0026] The line memory 209 temporarily stores the sensed digital values of the light intensity detected at the digital pixel array 207, as sensed by the sense amplifiers 208 and processed by digital block 202 before sending the digital values to the processor 102 via MIPI 205 as the sensor data 108.

[0027] The power conditioner 210 is a circuit that improves the quality of the power that is delivered to components of the photo sensor 104. The power conditioner 210 may maintain and deliver a constant voltage that allows the components of the photo sensor 104 to function properly. In one embodiment, the power conditioner 210 is an AC power conditioner which smoothes the sinusoidal AC waveform. In alternate embodiments, the power conditioner 210 is a power line conditioner which takes in power and modifies it based on the requirements of the components connected to the power line conditioner.

[0028] The ramp generator and buffers module 211 comprises a ramp generator and buffers. The ramp generator is a function generator that increases its voltage to a particular value. The ramp generator may be used to avoid jolts when changing a load. The buffers provide electrical impedance transformation from one circuit to another to prevent the ramp generator from being affected by the load.

[0029] The sense amplification biasing module 212 provides biasing voltage signal to the sense amplifiers 208. The biasing voltage signal is a predetermined voltage for the purpose of establishing proper operating conditions of the sense amplifiers 208 such as a steady DC voltage.

Example Stacked Photo Sensor Assembly

[0030] FIG. 3 is a cross-sectional view illustrating the stacked photo sensor assembly 300, according to one embodiment. In one embodiment, the stacked photo assembly includes a first substrate 310 coupled to a second substrate 340. The first substrate 310 may be a back-side illumination 302 sensor that is flipped over and includes, among other components, a first n+ diffusion well 312, a photodiode 314, a transistor AB 313, a transistor TX 316, and a second n+ diffusion well 320.

[0031] Each of transistor AB 311 and transistor TX 316 includes an active layer, a drain electrode coupled to the active layer, a photodiode 314 that serves as a source of both transistor AB and transistor TX, an insulation layer over the active layer, and a gate electrode (not shown). By controlling a voltage level at the gates of the transistors AB 311 and the transistor TX 316, the transistors AB 311 and the transistor TX 316 can be turned on or off. The gates of these transistors receive signals from circuits external to the digital pixel array 207.

[0032] The first n+ diffusion well 312 is an N doped implant region formed in the first substrate 310. The first n+ diffusion well 312 receives photoelectrons that are transferred from the photodiode 314 when transistor AB 313 is turned on during non-exposure times. This is equivalent to a closed shutter mode in a traditional film camera. The transfer of photoelectrons from the photodiode 314 to the first n+ diffusion well 312 ensures that no photoelectrons are accumulated on the photodiode 314, as the non-exposure times are periods when no signal is generated. The first n+ diffusion well 312 is typically connected to a positive voltage source, for example VDD, so the photoelectrons are drained away. During an exposure time, which is equivalent to the shutter open mode in a film camera, both transistor AB 313 and transistor TX 316 are turned off and the photoelectrons are initially stored inside the photodiode 314. At the end of exposure, transistor TX 316 is turned on. As a result, the charge stored in the photodiode 314 is transferred to the second n+ diffusion well 320.

[0033] The photodiode 314 is a semiconductor device that converts light into an electric current. Current is generated when photons are absorbed in the photodiode 314. The photodiode 314 may be a p-n junction or PIN structure. When the intensity of light through back-side illumination 302 is higher, the amount of charge accumulated on the photodiode 314 is high. Similarly, when the intensity of light through back-side illumination 302 is lower, the amount of charge accumulated on the photodiode 314 is low.

[0034] The interconnect 350 may be a pixel level direct interconnect from the second n+ diffusion well 320 to a circuit 342 in the second substrate 340. In one embodiment, the interconnect 350 transmits a voltage signal that reflects the amount of charge transferred from the photodiode 314 to the second n+ diffusion well 320. In alternative embodiments, the interconnect 350 transmits a current signal that reflects the amount of charge transferred from the photodiode 314 to the second n+ diffusion well 320. The interconnect 350 carries the voltage signal to the circuit 342 for further processing such as sampling and analog-to-digital conversion. In still other embodiments, the stacked photo sensor assembly 300 may include additional interconnects that also transmit signals from the circuit 342 of the second substrate 340 to the first substrate 310. For example, signals for controlling transistor AB 313 and transistor TX 316 may be transmitted from the circuit 342 via these additional interconnects.

[0035] Embodiments move various circuit components provided on the first substrate 310 in conventional photo sensors to the second substrate 340, and connect the circuits of the second substrate 340 to the components in the first substrate 310 via the pixel level interconnect 350. The various circuit components moved to the second substrate 340 may include, among others, switches, amplifiers and current source. In this way, the area occupied by other than photodiode components in the first substrate 310 can be beneficially reduced and the fill factor can be increased.

Example Circuitry of a Pixel of the Photo Sensor

[0036] FIG. 4 is a circuit diagram illustrating the circuitry of a pixel of the photo sensor 104, according to one embodiment. In the embodiment of FIG. 4, the first substrate 310 includes, among other components, the photodiode 314, a first transistor TX, a first reset transistor T.sub.RST1, and an amplifier T.sub.S. Parasitic capacitance C.sub.D is also present in the first substrate 310 between the transistor T.sub.RST1 and the amplifier T.sub.S. The operation of the photodiode 314 and the first transistor TX is described above in detail with reference to FIG. 3.

[0037] The first reset transistor T.sub.RST1 functions to reset the voltage at floating diffusion point F.sub.D when the first reset transistor T.sub.RST1 is turned on. The first reset transistor T.sub.RST1 is turned on when a reset signal RST1 is received at the gate of the first reset transistor T.sub.RST1 before each cycle of exposure and sensing. The drain of the first reset transistor T.sub.RST1 is connected to a voltage source VDD. The source of the first reset transistor T.sub.RST1 is connected to the floating diffusion point F.sub.D.

[0038] The voltage level at the floating diffusion point F.sub.D serves as a proxy that indicates the duration and/or intensity of light exposure of the photodiode 314 during an exposure phase. The floating diffusion point F.sub.D is connected to the second n+ diffusion well 320. As the charge is transferred from the photodiode 314 to the floating diffusion point F.sub.D via the first transistor TX, the voltage level at the floating diffusion point F.sub.D is decreased from the original reset voltage level. The voltage change on the floating diffusion node is proportional to the charge transferred from the photodiode. When the duration and/or intensity of light exposure of the photodiode 314 during the exposure phase is increased, the voltage change at the floating diffusion point F.sub.D is also increased. When the duration and/or intensity of light exposure of the photodiode 314 during the exposure phase is decreased, the voltage change at the floating diffusion point F.sub.D is also decreased.

[0039] The amplifier T.sub.S is a source follower amplifier that amplifies its gate signal to generate a voltage signal V.sub.SIG that is transmitted to the circuit 342. The gate of the amplifier T.sub.S is connected to the floating diffusion point F.sub.D. The drain of the amplifier T.sub.S is connected to a voltage source VDD. The source of the amplifier T.sub.S is connected to the interconnect 350. The voltage signal V.sub.SIG corresponds to the voltage level at the floating diffusion point F.sub.D.

[0040] The second substrate 340 includes the circuit 342 that processes signals based on the voltage signal V.sub.SIG. The circuit 342 includes, among other components, a current source T.sub.CS, a first switch SW1, a second switch SW2, a second reset transistor T.sub.RST2, a sense transistor T.sub.SENSE, and a read transistor T.sub.READ.

[0041] The current source T.sub.CS operates as a current source when turned on. In one embodiment, the gate of current source T.sub.CS is applied with a pulse of bias voltage V.sub.BIAS at the start of the readout phase, as described below in detail with reference to FIG. 5 in order to turn on and off the current source T.sub.CS. The current source T.sub.CS is turned on only during the readout phase and is turned off when the pixel is not in the readout phase to save power. The drain of the current source T.sub.CS is connected to the interconnect 350 and the source of the current source T.sub.CS is grounded.

[0042] The second reset transistor T.sub.RST2 resets the voltage at a terminal of the second in-pixel capacitor C2 when it is turned on. While the second switch SW2 is turned off, reset signal R.sub.ST2 is provided to the gate of the second reset transistor T.sub.RST2 to reset and store the reset voltage V.sub.RST2 at the terminal of the second in-pixel capacitor C2. In this embodiment where a PMOS type is used as the second reset transistor T.sub.RST2, the source of the second reset transistor T.sub.RST2 is connected to a voltage source VDD. The drain of the second reset transistor T.sub.RST2 is connected to conductive line L1. The second reset transistor T.sub.RST2 is also used to reset the first in-pixel capacitor C1 when the second switch SW2 is turned on.

[0043] The sense transistor T.sub.SENSE is a source follower amplifier that amplifies the voltage V.sub.SIG transmitted over conductive line L1. The gate of the sense transistor T.sub.SENSE is connected to conductive line L1. The source of the sense transistor T.sub.SENSE is connected to the read transistor T.sub.READ.

[0044] The read transistor T.sub.READ is turned on when a word line signal V.sub.WORD turns active, enabling the amplified version of the voltage at conductive line L1 to be sent to a pixel value readout circuit 434 located outside the pixel.

[0045] In alternate embodiments, the amplifiers or current sources are replaced with various other circuits that are not shown in FIG. 4. Alternatively, in one embodiment, the circuit 342 does not include the second reset transistor T.sub.RST2.

[0046] Example Timing Diagram

[0047] FIG. 5 is a timing diagram illustrating signals associated with the operation of a photo sensor pixel, according to one embodiment. A cycle of the pixel operation is divided into an exposure phase and a readout phase. The readout phase is further divided into a readout from the photodiode to in-pixel capacitors C1, C2 and a readout from the in-pixel capacitors C1, C2 to outside of the digital pixel array through the read transistor T.sub.READ. During the exposure phase, the photodiode 314 accumulates charge. During the readout phase, the accumulated charge in the photodiode 314 is converted to the voltage signal V.sub.SIG and processed through the circuit 342.

[0048] The gate voltage R.sub.ST1 of the first reset transistor T.sub.RST1 is high before exposure, turns low at time T0 at which the exposure phase starts, remains low throughout the exposure phase, and turns high again at the start of the readout phase. When the first reset transistor T.sub.RST1 is turned on, the voltage level at the floating diffusion point F.sub.D is reset to a predetermined voltage.

[0049] The first transistor TX is turned off at time T0 and remains turned off during the exposure phase. Then, the first transistor TX is turned on at time T4 and remains turned on for an amount of time Tb to enable charge accumulated in the photodiode 314 to transfer to the floating diffusion point F.sub.D. The voltage change on the floating diffusion point F.sub.D corresponds to the amount of charge accumulated in the photodiode 314 and parasitic capacitance C.sub.D on the floating diffusion point F.sub.D. Then, the first transistor TX is turned off throughout the remaining readout phase.

[0050] Bias voltage V.sub.BIAS is turned active at time T1, which indicates the start of the readout phase to turn on the transistor T.sub.CS. The current source T.sub.CS remains turned on for an amount of time T.sub.C and is then turned off. By turning on the current source T.sub.CS only for the amount of time T.sub.C instead of the entire readout phase, the power consumption of the circuit 342 can be reduced. The time T.sub.C is the readout phase where the signal from the photodiode 314 is read into in-pixel capacitors C1, C2.

[0051] In this readout phase, the first switch SW1 and the second switch SW2 are turned on at time T2. At time T3, the second switch SW2 is turned off to store the reset voltage V.sub.RST1 in the second in-pixel capacitor C2. Time T3 is before time T4, which is at the time when the first transistor TX gate is turned on and charge is transferred from the photodiode 314 onto the floating diffusion point F.sub.D.

[0052] Once the first transistor TX gate is turned off and the charge transfer is finished, the first switch SW1 is turned off at time T5. The voltage signal on the floating diffusion F.sub.D node V.sub.SIG is stored in the first capacitor C1. After storing the voltage signal V.sub.SIG in the first in-pixel capacitor C1 and V.sub.RST1 voltage in the second in-pixel capacitor C2, at time T6, bias voltage V.sub.BIAS is turned low and the sensor is finished with the readout from the photodiode 314 to in-pixel capacitors C1, C2. This first readout phase is performed simultaneously for all the pixels in the array, hence this is a global shutter operation.

[0053] The second readout from the in-pixel capacitors C1, C2 to outside of the digital pixel array may occur at a later time, and this is typically performed one row of pixels at a time. The second readout starts at time T7, where the word line signal V.sub.WORD signal is high and the read transistor T.sub.READ and the sense transistor T.sub.SENSE are turned on. The pixel reset voltage V.sub.RST1 stored on the second in-pixel capacitor C2 is readout first to the pixel value readout circuit 434, then at time T8, the second reset transistor T.sub.RST2 is turned on and the voltage on the second in-pixel capacitor C2 is reset to a known voltage level V.sub.RST2. The second reset transistor T.sub.RST2 is turned off at time T9. Afterward, at time T10, the second switch SW2 is turned on. As a result, the voltage V.sub.OUT at conductive line L1 becomes the following:

V.sub.OUT=(V.sub.SIG.Math.C1+V.sub.RST2.Math.C1)/(C1+C2)(1)

[0054] Since the read transistor T.sub.READ is on when the word line signal V.sub.WORD is applied to the read transistor T.sub.READ, the voltage V.sub.OUT is provided to the pixel value readout circuit 434.

[0055] One of many advantages of the embodiments is that the first substrate 310 does not include a storage capacitor for storing the charge transferred from the photodiode 314 when the first transistor TX is turned on. Because the storage capacitor is not required in the first substrate, the fill factor of the photo sensor can be increased.

Example Process Flow

[0056] FIG. 6 is a process flow diagram illustrating a method for operating a pixel, according to one embodiment. Before the exposure phase T0, the first transistor TX and the first reset transistor T.sub.RST1 are turned on. A first reset signal R.sub.ST1 is applied to turn on the first reset transistor T.sub.RST1. When the first reset transistor T.sub.RST1 is turned on 600, the voltage level at the floating diffusion point F.sub.D is reset to a predetermined level.

[0057] The exposure period begins at T0. During the exposure period, the photodiode accumulates charge. The first transistor TX is turned off and remains turned off during the exposure phase to prevent the transfer of charge from the photodiode. The first reset transistor T.sub.RST1 is also turned off.

[0058] The readout phase begins at time T1. The readout phase is divided into readout from the photodiode to in-pixel capacitors C1, C2 (time T1 to T5) and readout from the in-pixel capacitors C1, C2 to outside of the digital pixel array (time T7 to T12), as described above with reference to FIG. 5. During the readout from the photodiode to in-pixel capacitors C1, C2 the first transistor TX is turned on 600 and charge is transferred 610 from the photodiode to the floating diffusion point F.sub.D.

[0059] The signal voltage V.sub.SIG is generated 620 at the first substrate. The signal voltage V.sub.SIG corresponds to the voltage level at the floating diffusion point F.sub.D.

[0060] Bias voltage V.sub.BIAS applied to the current source T.sub.CS is turned active at the start of the readout from the photodiode to in-pixel capacitors C1, C2 and enables the pixel level interconnect to carry the signal voltage V.sub.SIG from the amplifier T.sub.S. The current source T.sub.CS remains turned on for an amount of time T.sub.C. During time T.sub.C, the signal voltage V.sub.SIG is carried 630 between the floating diffusion point F.sub.D and the conductive line via the pixel level interconnect and stored 640 into in-pixel capacitors C1 and C2. Then, the second switch SW2 is turned off to store the reset voltage V.sub.RST1 of the floating diffusion point F.sub.D in the second in-pixel capacitor C2.

[0061] After storing the voltage signal V.sub.SIG in the first in-pixel capacitor C1 and reset voltage V.sub.RST1 in the second in-pixel capacitor C2, the sensor is finished with the readout from the photodiode to in-pixel capacitors C1, C2.

[0062] During the second readout from the in-pixel capacitors C1, C2 to outside of the digital pixel array, the reset voltage V.sub.RST1 stored on the second in-pixel capacitor C2 is readout first to the pixel value readout circuit 434. Then, the second reset transistor T.sub.RST2 is turned on and the voltage on the second in-pixel capacitor C2 is reset to a known voltage level V.sub.RST2. As a result, an output voltage V.sub.OUT at the conductive line L1 can be described in terms of the signal voltage V.sub.SIG stored in the first in-pixel capacitor C1 and the reset voltage V.sub.RESET stored in the second in-pixel capacitor C2, as shown in equation 1.

[0063] Word line signal V.sub.WORD is applied to the read transistor T.sub.READ to provide the output voltage V.sub.OUT to the pixel value readout circuit. The output voltage V.sub.WORD is processed by the pixel value readout circuit.

[0064] The language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the patent rights be limited not by this detailed description, but rather by any claims that issue on an application based hereon. Accordingly, the disclosure of the embodiments is intended to be illustrative, but not limiting, of the scope of the patent rights, which is set forth in the following claims.