IMAGE SENSOR CIRCUIT AND IMAGE DEPTH SENSOR SYSTEM

Abstract

The present disclosure provides an image sensor circuit, including: a pixel array, including a plurality of pixel series, where a pixel series in the plurality of pixel series includes a plurality of pixel circuits; and a clock signal generating circuit, coupled to a first end and a second end of the pixel series; where a first clock signal is propagated from the first end of the pixel series to the second end of the pixel series at a first time; and where a second clock signal is propagated from the second end of the pixel series to the first end of the pixel series.

Claims

1. An image sensor circuit, comprising: a pixel array, comprising a plurality of pixel series, wherein a pixel series in the plurality of pixel series comprises a plurality of pixel circuits; and a clock signal generating circuit, coupled to a first end and a second end of the pixel series; wherein the first end of the pixel series is electrically connected to the clock signal generating circuit to receive a first clock signal at a first time, and the first clock signal is propagated from the first end of the pixel series to the second end of the pixel series; and wherein the second end of the pixel series is electrically connected to the clock signal generating circuit to receive a second clock signal at a second time, and the second clock signal is propagated from the second end of the pixel series to the first end of the pixel series.

2. The image sensor circuit according to claim 1, wherein the pixel series comprises a clock signal transmitting unit, the clock signal transmitting unit being electrically connected to the plurality of pixel circuits in the pixel series.

3. The image sensor circuit according to claim 2, wherein a first end of the clock signal transmitting unit is electrically connected to the clock signal generating circuit to receive the first clock signal at the first time, and the first clock signal is propagated from the first end of the clock signal transmitting unit to a second end of the clock signal transmitting unit; and the second end of the clock signal transmitting unit is electrically connected to the clock signal generating circuit to receive the second clock signal at the second time, and the second clock signal is propagated from the second end of the clock signal transmitting unit to the first end of the clock signal transmitting unit.

4. The image sensor circuit according to claim 2, wherein the clock signal transmitting unit comprises at least one buffer module, configured to buffer the first clock signal or the second clock signal transferred in the clock signal transmitting unit.

5. The image sensor circuit according to claim 4, wherein the buffer module comprises a plurality of buffers, the plurality of buffers forming a buffer series, wherein a first buffer in the plurality of buffers is located at a first end of the buffer series, and a second buffer in the plurality of buffers is located at a second end of the buffer series.

6. The image sensor circuit according to claim 5, wherein the buffer module comprises a plurality of first switches and a plurality of second switches, the plurality of first switches being electrically connected to input ends of the plurality of buffers respectively, and the plurality of second switches being electrically connected to output ends of the plurality of buffers respectively, wherein the plurality of first switches are conducted while the plurality of second switches are cutoff at the first time, and the plurality of second switches are conducted while the plurality of first switches are cutoff at the second time.

7. An image depth sensor system, comprising: a light emitting unit, configured to emit incident light; and an image sensor circuit, configured to receive reflected light corresponding to the incident light, and comprising: a pixel array, comprising a plurality of pixel series, wherein a pixel series in the plurality of pixel series comprises a plurality of pixel circuits; and a clock signal generating circuit, coupled to a first end and a second end of the pixel series; wherein the first end of the pixel series is electrically connected to the clock signal generating circuit to receive a first clock signal at a first time, and the first clock signal is propagated from the first end of the pixel series to the second end of the pixel series; and wherein the second end of the pixel series is electrically connected to the clock signal generating circuit to receive a second clock signal at a second time, and the second clock signal is propagated from the second end of the pixel series to the first end of the pixel series.

8. The image depth sensor system according to claim 7, wherein the pixel series comprises a clock signal transmitting unit, the clock signal transmitting unit being electrically connected to the plurality of pixel circuits in the pixel series.

9. The image depth sensor system according to claim 8, wherein a first end of the clock signal transmitting unit is electrically connected to the clock signal generating circuit to receive the first clock signal at the first time, and the first clock signal is propagated from the first end of the clock signal transmitting unit to a second end of the clock signal transmitting unit; and the second end of the clock signal transmitting unit is electrically connected to the clock signal generating circuit to receive the second clock signal at the second time, and the second clock signal is propagated from the second end of the clock signal transmitting unit to the first end of the clock signal transmitting unit.

10. The image depth sensor system according to claim 8, wherein the clock signal transmitting unit comprises at least one buffer module, configured to buffer the first clock signal or the second clock signal transferred in the clock signal transmitting unit.

11. The image depth sensor system according to claim 10, wherein the buffer module comprises a plurality of buffers, the plurality of buffers forming a buffer series, wherein a first buffer in the plurality of buffers is located at a first end of the buffer series, and a second buffer in the plurality of buffers is located at a second end of the buffer series.

12. The image depth sensor system according to claim 11, wherein the buffer module comprises a plurality of first switches and a plurality of second switches, the plurality of first switches being electrically connected to input ends of the plurality of buffers respectively, and the plurality of second switches being electrically connected to output ends of the plurality of buffers respectively, wherein the plurality of first switches are conducted while the plurality of second switches are cutoff at the first time, and the plurality of second switches are conducted while the plurality of first switches are cutoff at the second time.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0015] FIG. 1 is a schematic diagram of an image depth sensor system according to an embodiment of the present disclosure;

[0016] FIG. 2 is a schematic diagram of a clock signal transmitting unit according to an embodiment of the present disclosure;

[0017] FIG. 3 is a schematic diagram of a buffer module according to an embodiment of the present disclosure;

[0018] FIG. 4 is a schematic diagram of a pixel array according to an embodiment of the present disclosure; and

[0019] FIG. 5 is a schematic diagram of a pixel array.

DESCRIPTION OF EMBODIMENTS

[0020] To make objectives, technical solutions and advantages of the present disclosure clearer, a further detailed description on the present disclosure will be given below in combination with accompanying drawings and embodiments. It should be understood that, specific embodiments described herein are merely used for illustrating the present disclosure, rather than limiting the present disclosure.

[0021] In the description and claims, the term coupled refers to any direct or indirect electrical connection means, and the term electrically connected refers to a direct electrical connection.

[0022] Referring to FIG. 1, FIG. 1 is a schematic diagram of an image depth sensor system 10 according to an embodiment of the present disclosure. The image depth sensor system 10 may be a three dimensional image sensor system, and may sense a distance/depth thereof with respect to a target object (not shown in FIG. 1) according to time of flight (ToF) of ray or light to create a three dimensional image of the target object. The image depth sensor system 10 includes a light emitting unit 12 and an image sensor circuit 14, and the light emitting unit 12 may be an invisible light emitting diode (LED), such as an infrared light emitting diode. The light emitting unit 12 is configured to emit incident light, and the image sensor circuit 14 may receive reflected light corresponding to the incident light.

[0023] The image sensor circuit 14 includes a pixel array 140 and a clock signal generating circuit 142, the pixel array 140 includes a plurality of pixel series PXSs, a pixel series PXS may be a column or a row of pixels located in the pixel array 140, and the pixel series PXS includes a plurality of pixel circuits PX_1?PX_M, where the pixel circuit PX_1 is a pixel circuit located at a first end (Terminal/End) of the pixel series PXS, the pixel circuit PX_M is a pixel circuit located at a second end of the pixel series PXS, and the clock signal generating circuit 142 is coupled to the first end of the pixel series PXS/pixel circuit PX_1 and the second end of the pixel series PXS/pixel circuit PX_M.

[0024] The first end of the pixel series PXS/pixel circuit PX_1 is directly electrically connected to the clock signal generating circuit 142 to receive a first clock signal CK1 at a first time, and the first clock signal CK1 is propagated from the first end of the pixel series PXS/pixel circuit PX_1 to the second end of the pixel series PXS/pixel circuit PX_M. That is to say, the first clock signal CK1 is propagated from the first end of the pixel series PXS/pixel circuit PX_1 to the second end of the pixel series PXS/pixel circuit PX_M in a first direction D1 (for example, in FIG. 1, the first direction D1 is from top to bottom).

[0025] The second end of the pixel series PXS/pixel circuit PX_M is directly electrically connected to the clock signal generating circuit 142 to receive a second clock signal CK2 at a second time, and the second clock signal CK2 is propagated from the second end of the pixel series PXS/pixel circuit PX_M to the first end of the pixel series PXS/pixel circuit PX_1. That is to say, the second clock signal CK2 is propagated from the second end of the pixel series PXS/pixel circuit PX_M to the first end of the pixel series PXS/pixel circuit PX_1 in a second direction D2 (for example, in FIG. 1, the second direction D2 is from top to bottom).

[0026] Specifically, the pixel series PXS includes a clock signal transmitting unit PXTL. In an embodiment, as shown in FIG. 1, the clock signal transmitting unit PXTL may include metal transmission lines, which are electrically connected to the pixel circuits PX_1?PX_M. A first end of the clock signal transmitting unit PXTL is coupled to the clock signal generating circuit 142 via a switch S1 (that is, the first end of the pixel series PXS/pixel circuit PX_1 is coupled to the clock signal generating circuit 142 via the switch S1), and a second end of the clock signal transmitting unit PXTL is coupled to the clock signal generating circuit 142 via a switch S2 (that is, the second end of the pixel series PXS/pixel circuit PX_M is coupled to the clock signal generating circuit 142 via the switch S2). The switch S1 is conducted while the switch S2 is cutoff at the first time; and the switch S1 is cutoff while the switch S2 is conducted at the second time.

[0027] When the switch S1 is conducted at the first time, the first end of the pixel series PXS/pixel circuit PX_1 and the first end of the clock signal transmitting unit PXTL are considered to be directly electrically connected to the clock signal generating circuit 142, the pixel circuit PX_1 and the first end of the clock signal transmitting unit PXTL may receive the first clock signal CK1, and the first clock signal CK1 is carried/conducted in the clock signal transmitting unit PXTL, and is propagated from the pixel circuit PX_1 to the pixel circuit PX_M in the first direction D1.

[0028] When the switch S2 is conducted at the second time, the second end of the pixel series PXS/pixel circuit PX_M and the second end of the clock signal transmitting unit PXTL are considered to be directly electrically connected to the clock signal generating circuit 142, the pixel circuit PX_M and the second end of the clock signal transmitting unit PXTL may receive the second clock signal CK2, and the second clock signal CK2 is carried/conducted in the clock signal transmitting unit PXTL, and is propagated from the pixel circuit PX_M to the pixel circuit PX_1 in the second direction D2.

[0029] It should be noted that, clock signals actually received by the pixel circuits PX_1?PX_M of the same pixel series PXS (received clock signals for short) have phase differences therebetween since the clock signals conducted in the clock signal transmitting unit PXTL have propagation delay For the convenience of description, the received clock signals corresponding to the pixel circuits PX_1?PX_M have phase differences ?.sub.11??.sub.1M with respect to the first clock signal CK1 without propagation delay at the first time, and the received clock signals corresponding to the pixel circuits PX_1?PX_M have phase differences ?.sub.21??.sub.2M with respect to the second clock signal CK2 without propagation delay at the second time, where the phase differences ?.sub.11.Math.?.sub.1M are related to transmission distances of lines from an output end of the clock signal generating circuit 142 that outputs the first clock signal CK1 to the pixel circuits PX_1?PX_M, the phase differences ?.sub.21??.sub.2M are related to transmission distances of lines from an output end of the clock signal generating circuit 142 that outputs the second clock signal CK2 to the pixel circuits PX_1?PX_M, and there is a relationship of ?.sub.11<?.sub.12<?.sub.13< . . . <?.sub.1M among the phase differences ?.sub.11??.sub.1M, and there is a relationship of ?.sub.21>?.sub.22>?.sub.23> . . . >?.sub.2M among the phase differences ?.sub.21??.sub.2M. Preferably, the transmission distances of lines from the output ends of the signal generating circuit 142 that output the first clock signal CK1 and the second clock signal CK2 to the pixel circuit PX_1?PX_M may be designed to make ?.sub.11+?.sub.21=?.sub.12+?.sub.22= . . . =?.sub.1M+?.sub.2M, in this way, the phase differences ?.sub.11??.sub.1M and the phase differences ?.sub.21??.sub.2M may compensate each other, and in a long term, an influence of the phase differences ?.sub.11??.sub.1M or the phase differences ?.sub.21??.sub.2M on calculation of a distance/depth may be reduced, thereby reducing errors when the distance/depth is calculated.

[0030] By comparison, referring to FIG. 5, FIG. 5 is a schematic diagram of an existing pixel array 540. Clock signals CKs in the pixel array 540 are propagated only in a single direction D, while received clock signals corresponding to pixel circuits PX_1?PX_M have phase differences ?.sub.1??.sub.M with respect to the clock signals CKs without propagation delay, and the phase differences ?.sub.1??.sub.M may have an influence on calculation of a distance/depth, so as to increase errors when the distance/depth is calculated.

[0031] Further, to make waveforms of a first clock signal CK1 and a second clock signal CK2 more complete during conduction of the first clock signal CK1 and the second clock signal CK2 in a clock signal transmitting unit, the clock signal transmitting unit may include a buffer module. Referring to FIG. 2, FIG. 2 is a schematic diagram of a clock signal transmitting unit PXTL2 according to an embodiment of the present disclosure. The clock signal transmitting unit PXTL2 is an embodiment manner of the clock signal transmitting unit PXTL in FIG. 1, and the clock signal transmitting unit PXTL2 includes a plurality of buffer modules BFMs. In an embodiment, as shown in FIG. 2, the buffer modules BFMs are inserted between every k pixel circuits, but this is not limited thereto. A first clock signal CK1 is received by a first end N1 of a buffer module BFM at a first time, and a second end N2 of the buffer module BFM outputs the buffered first clock signal CK1; and a second clock signal CK2 is received by the second end N2 of the buffer module BFM at a second time, and the first end N1 of the buffer module BFM outputs the buffered second clock signal CK2.

[0032] Specifically, Referring to FIG. 3, FIG. 3 is a schematic diagram of a buffer module BFM according to an embodiment of the present disclosure. The buffer module BFM includes a plurality of buffers BF1, BF2, BF3, first switches SW11, SW12, SW13, and second switches SW21, SW22, SW23, where the first switches SW11, SW12, SW13 are electrically connected to input ends of the buffers BF1, BF2, BF3 respectively, and the second switches SW21, SW22, SW23 are electrically connected to output ends of the buffers BF3, BF2, BF1 respectively. Further, the first switch SW12 is electrically connected between the output end of the buffer BF1 and the input end of the buffer BF2, the first switch SW13 is electrically connected between the output end of the buffer BF2 and the input end of the buffer BF3, the second switch SW21 is electrically connected between the output end of the buffer BF3 and the input end of the buffer BF2, and the second switch SW22 is electrically connected between the output end of the buffer BF2 and the input end of the buffer BF1.

[0033] The first switches SW11, SW12, SW13 are conducted and the second switches SW21, SW22, SW23 are cutoff at a first time, and a first clock signal CK1 is input to the buffer module BFM through the first switch SW11 and is output from the input end of the buffer BF3; and the first switches SW11, SW12, SW13 are cutoff and the second switches SW21, SW22, SW23 are conducted at a second time, and a second clock signal CK2 is input to the buffer module BFM from the input end of the buffer BF3 and is output through the second switch SW23.

[0034] From the foregoing description, it can be seen that an image sensor circuit 14 has phase differences ?.sub.11??.sub.1M in pixel circuits PX_1?PX_M at the first time, and has phase differences ?.sub.21??.sub.2M in the pixel circuits PX_1?PX_M at the second time using the first clock signal CK1 propagated in a first direction D1 and the second clock signal CK2 propagated in the second direction D2. Preferably, transmission distances of lines from output ends of a signal generating circuit 142 that output the first clock signal CK1 and the second clock signal CK2 to the pixel circuits PX_1?PX_M may be adjusted to make ?.sub.11+?.sub.21= . . . =?.sub.1M+?.sub.2M, the phase differences ?.sub.11??.sub.1M and the phase differences ?.sub.21??.sub.2M may compensate each other, and an influence of the phase differences ?.sub.11??.sub.1M or the phase differences ?.sub.21??.sub.2M on calculation of a distance/depth may be reduced, thereby reducing errors when the distance/depth is calculated.

[0035] It should be noted that the foregoing embodiment is used for illustrating concepts of the present disclosure, persons with ordinary knowledge in the art can make different modifications according to these, but this is not limited thereto. For example, a clock signal transmitting unit is not limited to including a plurality of buffer modules, and the clock signal transmitting unit may only include one buffer module, which is also within the scope of the present disclosure. Furthermore, the buffer module is not limited to including three buffers, the buffer module may include a plurality of buffers, and it is possible to satisfy requirements of the present disclosure as long as first switches and second switches are used at a suitable time to switch transmission paths of the first clock signal CK1 and the second clock signal CK2 in the buffer module.

[0036] Furthermore, referring to FIG. 4, FIG. 4 is a schematic diagram of a pixel array 440 according to an embodiment of the present disclosure. The pixel array 440 is similar to the pixel array 140, therefore, the same components follow the same marks. Unlike the pixel array 140, a clock signal transmitting unit PXTL4 in the pixel array 440 includes metal transmission lines L1, L2, and the metal transmission lines L1, L2 are directly electrically connected to pixel circuits PX_1?PX_M, the metal transmission line L1 is used to conduct a first clock signal CK1, and the metal transmission line L2 is used to conduct a second clock signal CK2. In other words, the first clock signal CK1 is carried/conducted in the metal transmission line L1 at a first time, and is propagated from the pixel circuit PX_1 to the pixel circuit PX_M in a first direction D1; and the second clock signal CK2 is carried/conducted in the metal transmission line L2 at a second time, and is propagated from the pixel circuit PX_M to the pixel circuit PX_1 in a second direction D2, which also belongs to the scope of the present disclosure.

[0037] To sum up, according to the present disclosure, clock signals propagated in opposite directions are used to form phase differences in pixel circuits of a pixel series at a first time and a second time, and phase differences formed in the pixel circuits of the pixel series at the first time and phase differences formed in the pixel circuits of the pixel series at the second time may compensate each other, so as to reduce an influence of the phase differences on calculation of a distance/depth, thereby reducing errors when the distance/depth is calculated.

[0038] The foregoing descriptions are merely preferred embodiments of the present disclosure, rather than limiting the present disclosure, and any modifications, equivalent substitutions, improvements and the like, made within the spirit and principle of the present disclosure, are all encompassed in the protection scope of the present disclosure.