Solid-state image sensor and electronic information device

Abstract

Provided are a solid-state image sensor and an electronic information device capable of effectively reducing the occurrence of pseudo-smear by adopting a simple configuration and operation. A solid-state image sensor 1 includes multiple pixel circuit units P.sub.N and P.sub.OB, each including a photoelectric conversion unit that generates charges via photoelectric conversion and accumulates the generated charges, a floating diffusion unit that retains charges transferred from the photoelectric conversion unit, a transfer unit through which charges accumulated by the photoelectric conversion unit are transferred to the floating diffusion unit, an output unit that outputs a signal corresponding to the amount of charges retained by the floating diffusion unit, and a reset unit that discharges charges retained by the floating diffusion unit to the outside; and an A/D conversion unit 23 that acquires a signal output from the output unit and performs A/D conversion on the acquired signal using a set gain. At least one of the pixel circuit units P.sub.N and P.sub.OB is configured such that charges transferred from the photoelectric conversion unit to the floating diffusion unit and retained by the floating diffusion unit are limited so as not to exceed an upper limit amount which is set to be smaller by the extent of an increase in the gain.

Claims

1. A solid-state image sensor, comprising a plurality of pixel circuit units, each including a photoelectric conversion unit that generates charges via photoelectric conversion and accumulates the generated charges, a floating diffusion unit that retains charges transferred from the photoelectric conversion unit, a transfer unit through which charges accumulated by the photoelectric conversion unit are transferred to the floating diffusion unit, an output unit that outputs a signal corresponding to the amount of charges retained by the floating diffusion unit, and a reset unit that discharges charges retained by the floating diffusion unit to the outside, an A/D conversion unit that acquires a signal output from the output unit, and performs A/D conversion on the acquired signal using a set gain, and charge retaining circuitry that temporarily retains charges before being transferred from the photoelectric conversion unit to the floating diffusion unit, wherein at least one of the pixel circuit units is configured such that charges transferred from the photoelectric conversion unit to the floating diffusion unit and retained by the floating diffusion unit are limited so as not to exceed an upper limit amount which is set to be smaller by the extent of an increase in the gain, the transfer unit includes a first transfer unit through which charges accumulated by the photoelectric conversion unit are transferred to the charge retaining circuitry, and a second transfer unit through which charges retained by the charge retaining circuitry are transferred to the floating diffusion unit, and wherein at least one of the pixel circuit units is configured to perform at least one of a first upper limit amount limiting operation in which charges retained by the floating diffusion unit are limited so as not to exceed the upper limit amount, a second upper limit amount limiting operation in which charges accumulated by the photoelectric conversion unit are limited so as not to exceed the upper limit amount, and a third upper limit amount limiting operation in which charges retained by the charge retaining circuitry are limited so as not to exceed the upper limit amount.

2. The solid-state image sensor according to claim 1, further comprising an intermediate voltage generation unit configured to generate an intermediate voltage of a magnitude between a first voltage and a second voltage in correspondence with the gain, wherein in at least one of the pixel circuit units, the second transfer unit forms a control terminal of a transistor which enters an ON mode if the first voltage is applied thereto, and enters an OFF mode if the second voltage is applied thereto, and when the third upper limit amount limiting operation is performed, the intermediate voltage is applied to the second transfer unit.

3. The solid-state image sensor according to claim 2, wherein all the transistors are configured such that the first voltage, the intermediate voltage, and the second voltage are selectively applied to the control terminals.

4. The solid-state image sensor according to claim 2, at least one of the pixel circuit units is configured such that the third upper limit amount limiting operation is performed in such a way that the second transfer unit transfers charges exceeding the upper limit amount from the charge retaining circuitry to the floating diffusion unit, and the reset unit discharges charges which are transferred from the charge retaining circuitry to the floating diffusion unit.

5. The solid-state image sensor according to claim 2, the polarity of the second voltage is different from that of the first voltage.

6. The solid-state image sensor according to claim 1, further comprising an intermediate voltage generation unit configured to generate an intermediate voltage of a magnitude between a first voltage and a second voltage in correspondence with the gain, wherein in at least one of the pixel circuit units, the reset unit includes a transistor which enters an ON mode if the first voltage is applied to a control terminal of the transistor, and enters an OFF mode if the second voltage is applied to the control terminal, and when the first upper limit amount limiting operation is performed, the intermediate voltage is applied to the control terminal of the transistor of the reset unit.

7. The solid-state image sensor according to claim 1, further comprising an intermediate voltage generation unit configured to generate an intermediate voltage of a magnitude between a first voltage and a second voltage in correspondence with the gain, wherein at least one of the pixel circuit units includes a discharge circuitry that discharges charges accumulated by the photoelectric conversion unit to the outside, the discharge circuitry including a transistor which enters an ON mode if the first voltage is applied to a control terminal of the transistor, and enters an OFF mode if the second voltage is applied to the control terminal, and when the second upper limit amount limiting operation is performed, the intermediate voltage is applied to the control terminal of the transistor of the discharge circuitry.

8. The solid-state image sensor according to claim 1, further comprising an offset correction processing unit that performs an offset correction process on data obtained by performing A/D conversion on signal, which is output from a pixel circuit unit exposed to light, by the A/D conversion unit, based on data obtained by performing A/D conversion on a signal, which is output from a pixel circuit unit shielded from light, by the A/D conversion unit.

9. An electronic information device comprising a solid-state image sensor according to claim 1.

10. A solid-state image sensor, comprising a plurality of pixel circuit units, each including a photoelectric conversion unit that generates charges via photoelectric conversion and accumulates the generated charges, a floating diffusion unit that retains charges transferred from the photoelectric conversion unit, a transfer unit through which charges accumulated by the photoelectric conversion unit are transferred to the floating diffusion unit, an output unit that outputs a signal corresponding to the amount of charges retained by the floating in diffusion unit, and a reset unit that discharges charges retained by the floating diffusion unit to the outside; an A/D conversion unit that acquires a signal output from the output unit, and performs A/D conversion on the acquired signal using a set gain, an intermediate voltage generation unit configured to generate an intermediate voltage of a magnitude between a first voltage and a second voltage in correspondence with the gain, wherein at least one of the pixel circuit units is configured such that charges transferred from the photoelectric conversion unit to the floating diffusion unit and retained by the floating diffusion unit are limited so as not to exceed an upper limit amount which is set to be smaller by the extent of an increase in the gain, at least one of the pixel circuit units is configured to perform at least one of a first upper limit amount limiting operation in which charges retained by the floating diffusion unit are limited so as not to exceed the upper limit amount, and a second upper limit amount limiting operation in which charges accumulated by the photoelectric conversion unit are limited so as not to exceed the upper limit amount, in at least one of the pixel circuit units, the transfer unit forms a control terminal of a transistor which enters an ON mode if the first voltage is applied thereto, and enters an OFF mode if the second voltage is applied thereto, and when the second upper limit amount limiting operation is performed, the intermediate voltage is applied to the transfer unit.

11. The solid-state image sensor according to claim 10, further comprising an intermediate voltage generation unit configured to generate an intermediate voltage of a magnitude between a first voltage and a second voltage in correspondence with the gain, wherein in at least one of the pixel circuit units, the reset unit includes a transistor which enters an ON mode if the first voltage is applied to a control terminal of the transistor, and enters an OFF mode if the second voltage is applied to the control terminal, and when the first upper limit amount limiting operation is performed, the intermediate voltage is applied to the control terminal of the transistor of the reset unit.

12. The solid-state image sensor according to claim 11, the polarity of the second voltage is different from that of the first voltage.

13. The solid-state image sensor according to claim 10, further comprising an intermediate voltage generation unit configured to generate an intermediate voltage of a magnitude between a first voltage and a second voltage in correspondence with the gain, wherein at least one of the pixel circuit units includes discharge circuity that discharges charges accumulated by the photoelectric conversion unit to the outside, the discharge circuitry including a transistor which enters an ON mode if the first voltage is applied to a control terminal of the transistor, and enters an OFF mode if the second voltage is applied to the control terminal, and when the second upper limit amount limiting operation is performed, the intermediate voltage is applied to the control terminal of the transistor of the discharge circuitry.

14. The solid-state image sensor according to claim 13, the polarity of the second voltage is different from that of the first voltage.

15. The solid-state image sensor according to claim 10, wherein all the transistors are configured such that the first voltage, the intermediate voltage, and the second voltage are selectively applied to the control terminals.

16. The solid-state image sensor according to claim 10, further comprising an offset correction processing unit that performs an offset correction process on data obtained by performing A/D conversion on signal, which is output from a pixel circuit unit exposed to light, by the A/D conversion unit, based on data obtained by performing A/D conversion on a signal, which is output from a pixel circuit unit shielded from light, by the A/D conversion unit.

17. An electronic information device comprising a solid-state image sensor according to claim 10.

18. The solid-state image sensor according to claim 10, at least one of the pixel circuit units is configured such that the second upper limit amount limiting operation is performed in such a way that the transfer unit transfers charges exceeding the upper limit amount from the photoelectric conversion unit to the floating diffusion unit, and the reset unit discharges charges which are transferred from the photoelectric conversion unit to the floating diffusion unit.

19. The solid-state image sensor according to claim 10, the polarity of the second voltage is different from that of the first voltage.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a block diagram illustrating the configuration of a solid-state image sensor of a first embodiment of the present invention.

(2) FIG. 2 is a circuit diagram of a pixel circuit of the solid-state image sensor illustrated in FIG. 1.

(3) FIG. 3 is a diagram illustrating an example of an effect of a gain on A/D conversion.

(4) FIG. 4 is a timing chart illustrating the operation of a pixel circuit on which strong light is incident in a case where a set gain is low.

(5) FIG. 5 is a potential diagram of an effective pixel circuit that performs the operation illustrated in FIG. 4.

(6) FIG. 6 is a timing chart illustrating the operation of a pixel circuit on which strong light is incident in a case where a set gain is high.

(7) FIG. 7 is a potential diagram of an effective pixel circuit that performs the operation illustrated in FIG. 6.

(8) FIG. 8 is a timing chart illustrating the operation of a pixel circuit of a solid-state image sensor of a second embodiment of the present invention.

(9) FIG. 9 is a potential diagram of an effective pixel circuit that performs the operation illustrated in FIG. 8.

(10) FIG. 10 is a timing chart illustrating the operation of a pixel circuit of a solid-state image sensor of a third embodiment of the present invention.

(11) FIG. 11 is a circuit diagram of a pixel circuit of a solid-state image sensor of a fourth embodiment of the present invention.

(12) FIG. 12 is a timing chart illustrating the operation of the pixel circuit of the solid-state image sensor of the fourth embodiment of the present invention.

(13) FIG. 13 is a potential diagram of an effective pixel circuit that performs the operation illustrated in FIG. 12.

(14) FIG. 14 is a timing chart illustrating the operation of a pixel circuit of a solid-state image sensor of a fifth embodiment of the present invention.

(15) FIG. 15 is a circuit diagram of a pixel circuit of a solid-state image sensor of a sixth embodiment of the present invention.

(16) FIG. 16 is a schematic sectional view illustrating an example of the configuration of a portion of the pixel circuit illustrated in FIG. 15.

(17) FIG. 17 is a timing chart illustrating the operation of the pixel circuit of the solid-state image sensor of the sixth embodiment of the present invention.

(18) FIG. 18 is a potential diagram of an effective pixel circuit that performs the operation illustrated in FIG. 17.

(19) FIG. 19 is a potential diagram of the effective pixel circuit that performs the operation illustrated in FIG. 17.

(20) FIG. 20 is a timing chart illustrating the operation of a pixel circuit of a solid-state image sensor of a seventh embodiment of the present invention.

(21) FIG. 21 is a potential diagram of an effective pixel circuit that performs the operation illustrated in FIG. 20.

(22) FIG. 22 is a potential diagram of the effective pixel circuit that performs the operation illustrated in FIG. 20.

(23) FIG. 23 is a timing chart illustrating the operation of a pixel circuit of a solid-state image sensor of a ninth embodiment of the present invention.

(24) FIG. 24 is a timing chart illustrating the operation of a pixel circuit of a solid-state image sensor of a tenth embodiment of the present invention.

(25) FIG. 25 is a potential diagram of an effective pixel circuit that performs the operation illustrated in FIG. 24.

(26) FIG. 26 is a potential diagram of the effective pixel circuit that performs the operation illustrated in FIG. 24.

(27) FIG. 27 is a block diagram illustrating the configuration of a modification example of the solid-state image sensor of the embodiments of the present invention.

(28) FIG. 28 is a block diagram illustrating the configuration of another modification example of the solid-state image sensor of the embodiments of the present invention.

(29) FIG. 29 is a block diagram illustrating the configuration of an electronic information device of an embodiment of the present invention.

(30) FIG. 30 is a schematic diagram illustrating a typical pixel array.

(31) FIG. 31 is a circuit diagram of a pixel circuit illustrating a cause of pseudo-smear occurring in a solid-state imaging device in the related art.

(32) FIG. 32 is a timing chart illustrating the operation of the pixel circuit illustrated in FIG. 31, on which weak light is incident.

(33) FIG. 33 is a timing chart illustrating the operation of the pixel circuit illustrated in FIG. 31, on which strong light is incident.

(34) FIG. 34 is a schematic view illustrating an offset correction process in a case where pseudo-smear has occurred.

(35) FIG. 35 is a schematic view illustrating an offset correction process in a case where pseudo-smear has occurred.

DESCRIPTION OF EMBODIMENTS

(36) <<Solid-State Image Sensor>>

(37) Hereinafter, solid-state image sensors of embodiments of the present invention will be described with reference to the accompanying drawings. Hereinafter, for illustrative and descriptive purposes, a CMOS image sensor, which generates and accumulates electrons and includes multiple pixel circuits including N-channel FETs, will be described as a specific example of the solid-state image sensor of each embodiment of the present invention.

(38) <First Embodiment>

(39) A solid-state image sensor of a first embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram illustrating the configuration of the solid-state image sensor of the first embodiment of the present invention. FIG. 2 is a circuit diagram of a pixel circuit of the solid-state image sensor illustrated in FIG. 1.

(40) As illustrated in FIG. 1, a solid-state image sensor 1 includes a pixel array 10; a vertical scan circuit 21; a pixel power supply regulator 22; an A/D conversion circuit (A/D conversion unit) 23; a ramp wave generation circuit 24; an intermediate voltage generation circuit (intermediate voltage generation unit) 25; a control circuit 26; a horizontal scan circuit 27; and an offset correction processing circuit (offset correction processing unit) 28.

(41) The pixel array 10 includes multiple pixel circuits (pixel circuit units) P.sub.N and P.sub.OB which are arrayed in a matrix pattern. Specific, the pixel array 10 includes multiple effective pixel circuits P.sub.N and multiple OB pixel circuits P.sub.OB. The effective pixel circuit P.sub.N is a pixel circuit of an effective pixel on which light is incident (which is exposed to light). The OB pixel circuit P.sub.OB is an optically black pixel circuit that is shielded from light. In FIG. 1, for illustrative and descriptive purposes, a small number of the pixel circuits P.sub.N and P.sub.OB of the pixel array 10 are illustrated on a very large scale.

(42) Any one of the effective pixel circuits P.sub.N and the OB pixel circuits P.sub.OB has a circuit configuration illustrated in FIG. 2. As illustrated in FIG. 31, at least a transfer control line TX is common to the effective pixel circuits P.sub.N and the OB pixel circuit P.sub.OB which belong to the same control group. A reset control line RST or a reset power supply line VR may be common to the effective pixel circuits P.sub.N and the OB pixel circuit P.sub.OB which belong to the same control group.

(43) As illustrated in FIG. 2, each of the effective pixel circuit P.sub.N and the OB pixel circuit P.sub.OB includes a photodiode (photoelectric conversion unit) PD that generates charges via photoelectric conversion; a floating diffusion area (floating diffusion unit) FD that retains charges transferred from the photodiode PD; a transfer gate (transfer unit) 11 through which charges are transferred from the photodiode PD to the floating diffusion area FD; an output transistor (output unit) 12 that outputs a signal (voltage) corresponding to the amount of charges retained by the floating diffusion area FD; and a reset transistor (reset unit) 13 that discharges charges in the photodiode PD and the floating diffusion area FD to the outside of the effective pixel circuit P.sub.N and the OB pixel circuit P.sub.OB.

(44) An anode of the photodiode PD is grounded. The transfer gate 11 is connected to the transfer control line TX, and is a gate of a transistor, the drain of which is the floating diffusion area FD, and the source of which is a cathode of the photodiode PD. The output transistor 12 has a gate connected to the floating diffusion area FD, a drain connected to a common power supply line VD, and a source connected to an output signal line VS. The reset transistor 13 has a gate connected to the reset control line RST, a drain connected to the reset power supply line VR, and a source connected to the floating diffusion area FD.

(45) The vertical scan circuit 21 outputs a signal (voltage) to control the operation of the pixel circuits P.sub.N and P.sub.OB in the pixel array 10. As described above, signal lines (for example, the transfer control line TX, the reset control line RST, and the reset power supply line VR) for controlling the operation of the pixel circuits P.sub.N and P.sub.OB are common to the pixel circuits P.sub.N and P.sub.OB (for example, the pixel circuits P.sub.N and P.sub.OB in the same row of the pixel array 10 which are arrayed in a lateral direction in FIG. 1) which belong to the same control group in the pixel array 10. If the vertical scan circuit 21 applies a signal (voltage) to a common signal line, the pixel circuits P.sub.N and P.sub.OB belonging to the same control group are controlled such that the pixel circuits P.sub.N and P.sub.OB perform the same operation at the same timing.

(46) The pixel power supply regulator 22 supplies power for operation of all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10. The common power supply line VD is common to all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10. The pixel power supply regulator 22 supplies a certain magnitude of voltage to the common power supply line VD. The pixel power supply regulator 22 supplies power to the vertical scan circuit 21 so as to generate a voltage to control the operation of the pixel circuits P.sub.N and P.sub.OB.

(47) The A/D conversion circuit 23 acquires the voltage of the output signal line VS, and performs A/D conversion on the acquired voltage using a set gain. For example, after the A/D conversion circuit 23 obtains a difference between the voltage of the output signal line VS when the floating diffusion area FD is reset and the voltage of the output signal line VS when charges are transferred from the photodiode PD to the floating diffusion area FD via correlated double sampling, the A/D conversion circuit 23 performs A/D conversion on the voltage difference.

(48) The ramp wave generation circuit 24 generates a ramp wave (sawtooth wave) of a slope corresponding to a gain set by the control circuit 26, and applies the generated ramp wave to the A/D conversion circuit 23. For example, the A/D conversion circuit 23 performs A/D conversion in such a way as to count the time from when a ramp wave applied from the ramp wave generation circuit 24 has risen to when the ramp wave has increased to a voltage (correlated double sampled difference), which is an A/D conversion target, or higher. In this case, the number of counts decreases to the extent of a decrease in gain (the slope of the ramp wave is steep), and thus the value of A/D converted data is small. In contrast, the number of counts increases to the extent of an increase in gain (the slope of the ramp wave is gradual), and thus the value of A/D converted data is large.

(49) The intermediate voltage generation circuit 25 generates an intermediate voltage of a magnitude corresponding to the gain set by the control circuit 26, and applies the generated intermediate voltage to the vertical scan circuit 21. The vertical scan circuit 21 controls the operation of at least a portion of transistors of the pixel circuits P.sub.N and P.sub.OB using the intermediate voltage applied from the intermediate voltage generation circuit 25 (details will be described later).

(50) The control circuit 26 sets a gain, and applies a signal or data indicating the magnitude of the gain to the ramp wave generation circuit 24 and the intermediate voltage generation circuit 25. For example, the control circuit 26 sets a gain higher by the extent of the darkness of an object (that is, light incident on the pixel array 10 is weak as a whole, and thus by the extent of a decrease in the amount of charges generated by the photodiode PD and retained in the floating diffusion area FD). Alternatively, for example, the control circuit 26 sets a gain (a gain corresponding to an imaging mode such as clear weather or night scene selected by a user, a gain as a numeric value directly specified by the user, or the like) as instructed by the user of an electronic information device in which the solid-state image sensor 1 is mounted.

(51) The horizontal scan circuit 27 controls the timing when the A/D conversion circuit 23 outputs A/D converted data. Specifically, the horizontal scan circuit 27 controls the data output timing of the A/D conversion circuit 23 such that one item of data or multiple items of data are selectively input to the offset correction processing circuit 28.

(52) The offset correction processing circuit 28 performs an offset correct process on data output from the A/D conversion circuit 23. Specifically, the offset correction processing circuit 28 performs an offset correction process on data which is obtained by performing A/D conversion on an output signal (voltage) of the effective pixel circuit P.sub.N via the A/D conversion circuit 23, based on data which is obtained by performing A/D conversion on an output signal (voltage) of the OB pixel circuit P.sub.OB via the A/D conversion circuit 23. Specifically, the offset correction processing circuit 28 subtracts A/D converted data of an output signal (voltage) of an OB pixel circuit P.sub.OB from A/D converted data of an output signal (voltage) of the effective pixel circuit P.sub.N belonging to the same control group as that of the OB pixel circuit P.sub.OB.

(53) A relationship between an A/D conversion gain and pseudo-smear will be described with reference to the accompanying drawings. FIG. 3 is a diagram illustrating the relationship between the A/D conversion gain and the pseudo-smear. FIG. 3 illustrates a signal (voltage) before A/D conversion, data that is obtained by performing A/D conversion on the signal using one times the gain, and data that is obtained by performing A/D conversion on the signal using four times the gain. FIG. 3 illustrates a very simple case where A/D converted data is two bits.

(54) As illustrated in FIG. 3, even if a voltage before A/D conversion is such a low level that data obtained by performing A/D conversion thereon using one times the gain becomes the minimum value [00], if A/D conversion is performed on the voltage using four times the gain, data becomes the maximum value [11]. As such, if the gain is increased, even if a voltage before A/D conversion is a low level, A/D converted data can be substantially increased.

(55) Accordingly, if the gain is increased, in a case where strong light is incident on an effective pixel circuit P.sub.N, and an output signal (voltage) of other pixel circuits P.sub.N and P.sub.OB belonging to the same control group as that of the effective pixel circuit P.sub.N is increased (refer to FIGS. 31 and 33), data obtained from the pixel circuits P.sub.N and P.sub.OB can be substantially increased.

(56) As described above, if an effect of an effective pixel circuit P.sub.N, on which strong light is incident, on other pixel circuits P.sub.N and P.sub.OB is large, it is difficult to cancel out the effect well, and thus, pseudo-smear is likely to appear in image data, which is a problem (refer to FIGS. 34 and 35).

(57) Hereinafter, this problem will be continuously described with reference to FIG. 3. In the following description, the voltage before A/D conversion illustrated in FIG. 3 is assumed to be a correlated double sampled difference (V.sub.rOB?V.sub.sOB) (refer to FIGS. 32 and 33) between signals (voltages) obtained from the OB pixel circuit P.sub.OB affected by the effective pixel circuit P.sub.N on which strong light is incident. A/D converted data for gains is assumed to be data obtained by performing A/D conversion on the correlated double sampled difference using each gain.

(58) As illustrated in FIG. 3, if A/D conversion is performed on the difference, which is obtained from the OB pixel circuit P.sub.OB, using one times the gain, resultant data becomes the minimum value [00]. Accordingly, even if an offset correction process is performed on A/D converted data of the difference, which is obtained from the effective pixel circuit P.sub.N, based on that data, the A/D converted data is not corrected at all, or is slightly corrected. That is, if the gain is low, pseudo-smear is unlikely to appear in image data (refer to FIG. 34).

(59) In contrast, if A/D conversion is performed on the difference, which is obtained from the OB pixel circuit P.sub.OB, using four times the gain, resultant data becomes the maximum value [11]. Accordingly, even if an offset correction process is performed on A/D converted data of the difference, which is obtained from the effective pixel circuit P.sub.N, based on that data, the A/D converted data is substantially corrected. That is, if the gain is high, pseudo-smear is likely to appear in image data. Particularly, in the very simple example illustrated in FIG. 3, an offset correction process is performed in such a way as to subtract the maximum value [11], which is the A/D converted data of the difference obtained from the OB pixel circuit P.sub.OB, from the A/D converted data of the difference obtained from the effective pixel circuit P.sub.N. Accordingly, regardless of the value of the A/D converted data of the difference obtained from the effective pixel circuit P.sub.N, the A/D converted data is forcibly corrected to the minimum value [00], and thus black pseudo-smear appears in image data (refer to FIG. 35).

(60) Since the solid-state image sensor 1 of the first embodiment of the present invention includes the pixel circuits P.sub.N and P.sub.OB which perform an operation described below, the occurrence of pseudo-smear is effectively reduced.

(61) Hereinafter, a specific operation of the pixel circuits P.sub.N and P.sub.OB will be described with reference to the accompanying drawings. Particularly, herein, two relative cases in which a set gain is high or low are described; however, the operation of the solid-state image sensor 1 of the first embodiment of the present invention is not limited to these two types.

(62) FIG. 4 is a timing chart illustrating the operation of a pixel circuit on which strong light is incident in a case where a set gain is low. FIG. 5 is a potential diagram of an effective pixel circuit that performs the operation illustrated in FIG. 4. FIG. 6 is a timing chart illustrating the operation of a pixel circuit on which strong light is incident in a case where a set gain is high. FIG. 7 is a potential diagram of an effective pixel circuit that performs the operation illustrated in FIG. 6. FIGS. 5 and 7 are potential diagrams of the effective pixel circuit P.sub.N. Since the only difference between the effective pixel circuit P.sub.N and the OB pixel circuit P.sub.OB is the existence and non-existence of charges E generated via photoelectric conversion, the potential diagrams illustrated in FIGS. 5 and 7 are suitable for the OB pixel circuit P.sub.OB if the existence of the charges E is removed. In FIGS. 4 and 6, a fluctuation in the voltage of the output signal line VS is illustrated in an emphasized manner, and the illustration of noise superimposed on the transfer control line TX or the reset control line RST is omitted.

(63) Although in FIGS. 4 to 7 illustration starts from a period T.sub.1, the accumulation of the charges E in the photodiode PD is assumed to start at a certain timing before the period T.sub.1 (electronic shutter). At this time, initially, both the transfer control line TX and the reset control line RST go to a high voltage H (first voltage), and both the transistor including the transfer gate 11 as a gate and the reset transistor 13 enter an ON mode. Therefore, charges in the photodiode PD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the floating diffusion area FD and the reset power supply line VR. The transfer control line TX goes to a low voltage L (second voltage), the transistor including the transfer gate 11 as a gate enters an OFF mode, the reset control line RST goes to an intermediate voltage, and the accumulation of the charges E in the photodiode PD starts. Since light is not incident on the OB pixel circuit P.sub.OB, the generation of charges via photoelectric conversion does not occur, and charges are not accumulated in the photodiode PD, but charges may be accumulated due to dark current or the like.

(64) Initially, the case where a set gain is low will be described with reference to FIGS. 4 and 5. As illustrated in FIGS. 4 and 5, first, if the reset control line RST goes to the high voltage H during the period T.sub.1, a potential barrier under a gate of the reset transistor 13 decreases, the reset transistor 13 enters an ON mode, and charges in the floating diffusion area FD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the reset power supply line VR at the high voltage H.

(65) Subsequently, the reset control line RST goes to an intermediate voltage M.sub.1 during a period T.sub.2. The intermediate voltage M.sub.1 is a voltage generated by the intermediate voltage generation unit 25, and is a voltage of a magnitude between the high voltage H and the low voltage L. If the reset control line RST goes to the intermediate voltage M.sub.1, a potential barrier under the gate of the reset transistor 13 increases to a level between an ON mode and an OFF mode.

(66) At the end of the period T.sub.2 (after a settling time has elapsed), the A/D conversion circuit 23 samples a voltage V.sub.rN of the output signal line VS in a state where charges are not retained in the floating diffusion area FD of the effective pixel circuit P.sub.N, and a voltage V.sub.rOB of the output signal line VS in a state where charges are not retained in the floating diffusion area FD of the OB pixel circuit P.sub.OB.

(67) Subsequently, if the transfer control line TX goes to the high voltage H during a period T.sub.3, a potential barrier under the transfer gate 11 decreases, the transistor including the transfer gate 11 as a gate enters an ON mode, and the charges E in the photodiode PD are transferred to the floating diffusion area FD. At this time, the charges E exceeding the potential barrier (that is, an upper limit amount of charges retained by the floating diffusion area FD) under the gate of the reset transistor 13 are discharged to the outside of the effective pixel circuit P.sub.N via the reset power supply line VR at the high voltage H. As such, if the intermediate voltage M.sub.1 is applied to the gate, the reset transistor 13 is capable of entering both states, that is, an ON mode and an OFF mode in correspondence with a fluctuation in charges of the source (the floating diffusion area FD) (hereinafter, this is the same for other transistors including gates to which the intermediate voltage is applied). Since photoelectric conversion is not performed in the OB pixel circuit P.sub.OB, almost no charges are transferred, and the voltage of the output signal line VS increases due to an effect of the transfer control line TX going to the high voltage H (refer to FIG. 4).

(68) Subsequently, if the transfer control line TX goes to the low voltage L during a period T.sub.4, a potential barrier under the transfer gate 11 increases, the transistor including the transfer gate 11 as a gate enters an OFF mode, and the transfer of charges from the photodiode PD to the floating diffusion area FD stops. At the end of the period T.sub.14 (after a settling time has elapsed), the A/D conversion circuit 23 samples a voltage V.sub.sN of the output signal line VS which corresponds to charges retained in the floating diffusion area FD of the effective pixel circuit P.sub.N, and a voltage V.sub.sOB of the output signal line VS which corresponds to charges retained in the floating diffusion area FD of the OB pixel circuit P.sub.OB.

(69) The A/D conversion circuit 23 generates effective pixel data of image data by performing A/D conversion on a correlated double sampled difference V.sub.rN?V.sub.sN for the effective pixel circuit P.sub.N. The A/D conversion circuit 23 generates OB pixel data of image data by performing A/D conversion on a correlated double sampled difference V.sub.rOB?V.sub.sOB for the OB pixel circuit P.sub.OB.

(70) The case where a set gain is high will be described with reference to FIGS. 6 and 7. The magnitude of a generated intermediate voltage is the only difference between the operation of the pixel circuits P.sub.N and P.sub.OB in a case where a gain is high illustrated in FIGS. 6 and 7 and the operation of the pixel circuits P.sub.N and P.sub.OB in a case where a gain is low illustrated in FIGS. 4 and 5.

(71) Hereinafter, a difference in operation will be described based on a difference in generated intermediate voltage. For clear illustration of the difference from the operation illustrated in FIGS. 4 and 5, in FIGS. 6 and 7, reference sign M.sub.1 is assigned to an intermediate voltage or a potential barrier in a case where a gain is low illustrated in FIGS. 4 and 5, and reference sign M.sub.2 is assigned to an intermediate voltage or a potential barrier in a case where a gain is high.

(72) As illustrated in FIGS. 6 and 7, in a case where a high gain is set, the reset control line RST goes to an intermediate voltage M.sub.2 during periods T.sub.2 to T.sub.4. The intermediate voltage M.sub.2 is a voltage higher than the intermediate voltage M.sub.1. Accordingly, a potential barrier under the gate of the reset transistor 13 is smaller than that at the intermediate voltage M.sub.1. That is, an upper limit amount of charges retained by the floating diffusion area FD is smaller than that at the intermediate voltage M.sub.1.

(73) As illustrated in FIGS. 4 to 7, the intermediate voltage generation unit 25 of the solid-state image sensor 1 generates an intermediate voltage higher by the extent of an increase in A/D conversion gain set by the control circuit 26. Accordingly, in a case where a low gain is set, the upper limit amount of the charges E eventually retained in the floating diffusion area FD is large. In a case where a high gain is set, the upper limit amount of the charges E eventually retained in the floating diffusion area FD is small.

(74) As described with reference to FIG. 3, in a case where a low gain is set, pseudo-smear is unlikely to appear in image data. Therefore, as illustrated in FIG. 4, it is possible to allow a somewhat increase in the correlated double sampled difference V.sub.rOB?V.sub.sOB for the OB pixel circuit P.sub.OB. Accordingly, in this case, even if the upper limit amount of the charges E eventually retained in the floating diffusion area FD is somewhat large, it is possible to satisfactorily reduce the occurrence of pseudo-smear by generating a somewhat low intermediate voltage M.sub.1.

(75) In contrast, in a case where a high gain is set, pseudo-smear is likely to appear in image data. Therefore, as illustrated in FIG. 6, the correlated double sampled difference V.sub.rOB?V.sub.sOB for the OB pixel circuit P.sub.OB preferably is as small as possible. Accordingly, in this case, the upper limit amount of the charges E eventually retained in the floating diffusion area FD is decreased by generating a high intermediate voltage M.sub.2. As a result, the occurrence of pseudo-smear is satisfactorily reduced.

(76) As described above, in the solid-state image sensor 1 of the first embodiment of the present invention, it is possible to directly reduce a fluctuation in the output of the pixel circuits P.sub.N and P.sub.OB belonging to the same control group, which is a cause of pseudo-smear, by limiting the upper limit amount of the charges E retained in the floating diffusion area FD. As a result, it is possible to effectively reduce the occurrence of pseudo-smear by adopting a simple configuration and operation in which the upper limit amount of the charges E eventually retained in the floating diffusion area FD is limited.

(77) In the solid-state image sensor 1 of the first embodiment of the present invention, the upper limit amount of the charges E eventually retained in the floating diffusion area FD is further decreased to the extent corresponding to the condition in which pseudo-smear is likely to appear due to a high A/D conversion gain. As a result, it is possible to effectively reduce the occurrence of pseudo-smear as necessary.

(78) <Second Embodiment>

(79) Hereinafter, a solid-state image sensor of a second embodiment of the present invention will be described. The only difference between the solid-state image sensor of the second embodiment of the present invention and the solid-state image sensor of the first embodiment of the present invention is a portion of the operation of the pixel circuits P.sub.N and P.sub.OB. Hereinafter, the points of difference between the solid-state image sensor of the second embodiment of the present invention and the solid-state image sensor of the first embodiment of the present invention will be described with reference to the accompanying drawings.

(80) FIG. 8 is a timing chart illustrating the operation of a pixel circuit of the solid-state image sensor of the second embodiment of the present invention. FIG. 9 is a potential diagram of an effective pixel circuit that performs the operation illustrated in FIG. 8. FIGS. 8 and 9 respectively correspond to FIGS. 6 and 7 which illustrate the operation of the solid-state image sensor of the first embodiment of the present invention in a case where a set gain is high. Similar to FIGS. 6 and 7, reference sign M.sub.11 is assigned to an intermediate voltage or a potential barrier in a case where a gain is low, and reference sign M.sub.12 is assigned to an intermediate voltage or a potential barrier in a case where a gain is high. In FIG. 8, a fluctuation in the voltage of the output signal line VS is illustrated in an emphasized manner, and the illustration of noise superimposed on the transfer control line TX or the reset control line RST is omitted.

(81) Although in FIGS. 8 to 9 illustration starts from a period T.sub.11, the accumulation of the charges E in the photodiode PD is assumed to start at a certain timing before the period T.sub.11 (electronic shutter). At this time, initially, both the transfer control line TX and the reset control line RST go to the high voltage H, and both the transistor including the transfer gate 11 as a gate and the reset transistor 13 enter an ON mode. Therefore, charges in the photodiode PD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the floating diffusion area FD and the reset power supply line VR. The transfer control line TX goes to an intermediate voltage M.sub.12, and the reset control line RST goes to the low voltage L. Therefore, the accumulation of the charges E in the photodiode PD starts. Since light is not incident on the OB pixel circuit P.sub.OB, the generation of charges via photoelectric conversion does not occur, and charges are not accumulated in the photodiode PD, but charges may be accumulated due to dark current or the like.

(82) After the transfer control line TX goes to the intermediate voltage M.sub.12, a potential barrier under the transfer gate 11 is present between an ON mode and an OFF mode. Accordingly, charges are being accumulated in the photodiode PD, and charges exceeding the potential barrier (that is, the upper limit amount of charges accumulated by the photodiode PD) under the transfer gate 11 flow into the floating diffusion area FD without being accumulated in the photodiode PD. In a case where a set gain is low, the transfer control line TX goes to an intermediate voltage M.sub.11 lower than the intermediate voltage M.sub.12, and a potential barrier under the transfer gate 11 is larger than that at the intermediate voltage M.sub.12.

(83) As illustrated in FIGS. 8 and 9, if the reset control line RST goes to the high voltage H during the period T.sub.11, a potential barrier under the gate of the reset transistor 13 decreases, the reset transistor 13 enters an ON mode, and charges in the floating diffusion area FD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the reset power supply line VR at the high voltage H.

(84) Subsequently, the reset control line RST goes to the low voltage L during a period T.sub.12. At the end of the period T.sub.12 (after a settling time has elapsed), the A/D conversion circuit 23 samples the voltage V.sub.rN of the output signal line VS in a state where charges are not retained in the floating diffusion area FD of the effective pixel circuit P.sub.N, and the voltage V.sub.rOB of the output signal line VS in a state where charges are not retained in the floating diffusion area FD of the OB pixel circuit P.sub.OB.

(85) Subsequently, if the transfer control line TX goes to the high voltage H during a period T.sub.13, a potential barrier under the transfer gate 11 decreases, the transistor including the transfer gate 11 as a gate enters an ON mode, and the charges E in the photodiode PD are transferred to the floating diffusion area FD. In this case, as described above, the charges E transferred from the photodiode PD to the floating diffusion area FD are the charges E which are accumulated in the photodiode PD as the result of limiting the upper limit amount by applying the intermediate voltage M.sub.12 to the transfer control line TX. Since photoelectric conversion is not performed in the OB pixel circuit P.sub.OB, almost no charges are transferred, and the voltage of the output signal line VS increases due to an effect of the transfer control line TX going to the high voltage H (refer to FIG. 8).

(86) Subsequently, if the transfer control line TX goes to the intermediate voltage M.sub.12 during a period T.sub.14, a potential barrier under the transfer gate 11 increases to a level between an ON mode and an OFF mode, and the transfer of charges from the photodiode PD to the floating diffusion area FD stops. At the end of the period T.sub.14 (after a settling time has elapsed), the A/D conversion circuit 23 samples the voltage V.sub.sN of the output signal line VS which corresponds to charges retained in the floating diffusion area FD of the effective pixel circuit P.sub.N, and the voltage V.sub.sOB of the output signal line VS which corresponds to charges retained in the floating diffusion area FD of the OB pixel circuit P.sub.OB.

(87) As described above, in the solid-state image sensor 1 of the second embodiment of the present invention, it is possible to directly reduce a fluctuation in the output of the pixel circuits P.sub.N and P.sub.OB belonging to the same control group, which is a cause of pseudo-smear, by limiting the upper limit amount of the charges E accumulated in the photodiode PD. As a result, it is possible to effectively reduce the occurrence of pseudo-smear by adopting a simple configuration and operation in which the upper limit amount of the charges E eventually retained in the floating diffusion area FD is limited.

(88) In the solid-state image sensor 1 of the second embodiment of the present invention, the upper limit amount of the charges E eventually retained in the floating diffusion area FD is further decreased to the extent corresponding to the condition in which pseudo-smear is likely to appear due to a high A/D conversion gain. As a result, it is possible to effectively reduce the occurrence of pseudo-smear as necessary.

(89) <Third Embodiment>

(90) Hereinafter, a solid-state image sensor of a third embodiment of the present invention will be described. The solid-state image sensor of the third embodiment of the present invention is equivalent to a modification example of the solid-state image sensor of the second embodiment of the present invention. Hereinafter, the points of difference between the solid-state image sensor of the third embodiment of the present invention and the solid-state image sensor of the second embodiment of the present invention will be described with reference to the accompanying drawings.

(91) FIG. 10 is a timing chart illustrating the operation of a pixel circuit of the solid-state image sensor of the third embodiment of the present invention. FIG. 10 corresponds to FIG. 8 which illustrates the operation of the solid-state image sensor of the second embodiment of the present invention. Similar to FIG. 8, reference sign M.sub.11 is assigned to an intermediate voltage in a case where a gain is low, and reference sign M.sub.12 is assigned to an intermediate voltage in a case where a gain is high. In FIG. 10, a fluctuation in the voltage of the output signal line VS is illustrated in an emphasized manner, and the illustration of noise superimposed on the transfer control line TX or the reset control line RST is omitted.

(92) As illustrated in FIG. 10, in the solid-state image sensor 1 of the third embodiment of the present invention, the transfer control line TX goes to the low voltage L or the intermediate voltage M.sub.12 during periods apart from a period during which the transfer control line TX goes to the high voltage H. Particularly, during periods apart from the periods T.sub.11 to T.sub.14, the transfer control line TX goes to the low voltage L, and thus the transistor including the transfer gate 11 as a gate enters an OFF mode.

(93) As such, if the transistor including the transfer gate 11 as a gate enters an OFF mode, the concentration of charges (positive holes) having polarity opposite to that of charges (electrons) accumulated in the photodiode PD may increase under the transfer gate 11. Accordingly, charges generated due to dark current can be reduced from flowing into the photodiode PD.

(94) A period during which the transfer control line TX goes to the low voltage L (period during which the low voltage L is applied to the transfer gate 11) may account for 90% or greater of a period that is the sum of the period during which the transfer control line TX goes to the low voltage L (period during which the low voltage L is applied to the transfer gate 11) and periods during which the transfer control line TX goes to the intermediate voltages M.sub.11 and M.sub.12 (period during which the intermediate voltages M.sub.11 and M.sub.12 are applied to the transfer gate 11).

(95) In this configuration, dark current which increases due to the intermediate voltages M.sub.11 and M.sub.12 being used instead of the low voltage L can be reduced to one tenth or less.

(96) <Fourth Embodiment>

(97) Hereinafter, a solid-state image sensor of a fourth embodiment of the present invention will be described. The only difference between the solid-state image sensor of the fourth embodiment of the present invention and the solid-state image sensor of the first embodiment of the present invention is a portion of the configuration and operation of the pixel circuits P.sub.N and P.sub.OB. Hereinafter, the points of difference between the solid-state image sensor of the fourth embodiment of the present invention and the solid-state image sensor of the first embodiment of the present invention will be described with reference to the accompanying drawings.

(98) FIG. 11 is a circuit diagram of a pixel circuit of the solid-state image sensor of the fourth embodiment of the present invention. As illustrated in FIG. 11, each of the effective pixel circuit P.sub.N and the OB pixel circuit P.sub.OB includes the photodiode PD; the floating diffusion area FD; the transfer gate 11; the output transistor 12; the reset transistor 13; a selective transistor 14 that is connected in series to the output transistor 12; and a discharge transistor 15 that discharges charges in the photodiode PD to the outside of the effective pixel circuit P.sub.N and the OB pixel circuit P.sub.OB.

(99) The anode of the photodiode PD is grounded. The transfer gate 11 is connected to the transfer control line TX, and is a gate of a transistor, the drain of which is the floating diffusion area FD, and the source of which is the cathode of the photodiode PD. The output transistor 12 has a gate connected to the floating diffusion area FD, a drain connected to the common power supply line VD, and a source connected to a drain of the selective transistor 14. The reset transistor 13 has a gate connected to the reset control line RST, a drain connected to the common power supply line VD, and a source connected to the floating diffusion area FD. The selective transistor 14 has a gate connected to a selection control line SEL, and a source connected to the output signal line VS. The discharge transistor 15 has a gate connected to a discharge control line OFG, a drain connected to the common power supply line VD, and a source connected to the cathode of the photodiode PD.

(100) The reset control line RST and the selection control line SEL are common to the pixel circuits P.sub.N and P.sub.OB which belong to the same control group in the pixel array 10. The transfer control line TX, the discharge control line OFG, and the common power supply line VD are common to all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10.

(101) FIG. 12 is a timing chart illustrating the operation of the pixel circuit of the solid-state image sensor of the fourth embodiment of the present invention. FIG. 13 is a potential diagram of an effective pixel circuit that performs the operation illustrated in FIG. 12. FIGS. 12 and 13 respectively correspond to FIGS. 6 and 7 which illustrate the operation of the solid-state image sensor of the first embodiment of the present invention in a case where a set gain is high. Similar to FIGS. 6 and 7, reference sign M.sub.21 is assigned to an intermediate voltage or a potential barrier in a case where a gain is low, and reference sign M.sub.22 is assigned to an intermediate voltage or a potential barrier in a case where a gain is high. In FIG. 12, a fluctuation in the voltage of the output signal line VS is illustrated in an emphasized manner, and the illustration of noise superimposed on the transfer control line TX or the reset control line RST is omitted.

(102) Although in FIGS. 12 to 13 illustration starts from a period T.sub.21, the accumulation of the charges E in the photodiode PD is assumed to start at a certain timing before the period T.sub.21 (electronic shutter). At this time, initially, the discharge control line OFG goes to the high voltage H, and the discharge transistor 15 enters an ON mode. Therefore, charges in the photodiode PD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD. The discharge control line OFG goes to an intermediate voltage M.sub.22, and thus the accumulation of the charges E in the photodiode PD starts. Since light is not incident on the OB pixel circuit P.sub.OB, the generation of charges via photoelectric conversion does not occur, and charges are not accumulated in the photodiode PD, but charges may be accumulated due to dark current or the like.

(103) After the discharge control line OFG goes to the intermediate voltage M.sub.22, a potential barrier under the gate of the discharge transistor 15 is present between an ON mode and an OFF mode. Accordingly, charges are being accumulated in the photodiode PD, and charges exceeding the potential barrier (that is, the upper limit amount of charges accumulated by the photodiode PD) under the gate of the discharge transistor 15 are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD instead of being accumulated in the photodiode PD. In a case where a set gain is low, the discharge control line OFG goes to an intermediate voltage M.sub.21 lower than the intermediate voltage M.sub.22, and a potential barrier under the gate of the discharge transistor 15 is larger than that at the intermediate voltage M.sub.22.

(104) In the aforementioned example, an electronic shutter can be operated using the discharge transistor 15 independent of the floating diffusion area FD, and thus an electronic shutter can be operated for all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10 (global shutter). In this case, the charges E can be simultaneously transferred from the photodiodes PD to the floating diffusion areas FD in all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10. It is possible to acquire signals (voltages) of all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10 by sequentially turning on the selective transistors 14 of the pixel circuits P.sub.N and P.sub.OB in the pixel array 10 in the unit of the control group.

(105) As illustrated in FIGS. 12 and 13, if the reset control line RST goes to the high voltage H during the period T.sub.21, a potential barrier under the gate of the reset transistor 13 decreases, the reset transistor 13 enters an ON mode, and charges in the floating diffusion area FD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD.

(106) Subsequently, if the reset control line RST goes to the low voltage L during a period T.sub.22, a potential barrier under the gate of the reset transistor 13 increases, and the reset transistor 13 enters an OFF mode.

(107) Subsequently, if the transfer control line TX goes to the high voltage H during a period T.sub.23, a potential barrier under the transfer gate 11 decreases, the transistor including the transfer gate 11 as a gate enters an ON mode, and the charges E in the photodiode PD are transferred to the floating diffusion area FD. In this case, as described above, the charges E transferred from the photodiode PD to the floating diffusion area FD are the charges E which are accumulated in the photodiode PD as the result of limiting the upper limit amount by applying the intermediate voltage M.sub.22 to the discharge control line OFG. Since photoelectric conversion is not performed in the OB pixel circuit P.sub.OB, almost no charges are transferred.

(108) Subsequently, if the transfer control line TX goes to the low voltage L during a period T.sub.24, a potential barrier under the transfer gate 11 increases, the transistor including the transfer gate 11 as a gate enters an OFF mode, and the transfer of charges from the photodiode PD to the floating diffusion area FD stops.

(109) Subsequently, if the discharge control line OFG goes to the high voltage H during a period T.sub.25, a potential barrier under the gate of the discharge transistor 15 decreases, and the discharge transistor 14 enters an ON mode. Therefore, the charges E in the photodiode PD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD. The aforementioned operations performed during the periods T.sub.21 to T.sub.25 can be simultaneously performed by all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10.

(110) Subsequently, if the selection control line SEL goes to the high voltage H during a period T.sub.26, the selective transistor 14 enters an ON mode, and a signal (voltage) output from the output transistor 12 is applied to the output signal line VS. At the end of the period T.sub.26 (after a settling time has elapsed), the A/D conversion circuit 23 samples the voltage V.sub.sN of the output signal line VS which corresponds to charges retained in the floating diffusion area FD of the effective pixel circuit P.sub.N, and the voltage V.sub.sOB of the output signal line VS which corresponds to charges retained in the floating diffusion area FD of the OB pixel circuit P.sub.OB.

(111) Subsequently, if the reset control line RST goes to the high voltage H during a period T.sub.27, a potential barrier under the gate of the reset transistor 13 decreases, and the reset transistor 13 enters an ON mode. Therefore, charges in the floating diffusion area FD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD.

(112) Subsequently, if the reset control line RST goes to the low voltage L during a period T.sub.28, a potential barrier under the gate of the reset transistor 13 increases, and the reset transistor 13 enters an OFF mode. At the end of the period T.sub.28 (after a settling time has elapsed), the A/D conversion circuit 23 samples the voltage V.sub.rN of the output signal line VS in a state where charges are not retained in the floating diffusion area FD of the effective pixel circuit P.sub.N, and the voltage V.sub.rOB of the output signal line VS in a state where charges are not retained in the floating diffusion area FD of the OB pixel circuit P.sub.OB.

(113) Subsequently, if the selection control line SEL goes to the low voltage L during a period T.sub.29, the selective transistor 14 enters an OFF mode. The aforementioned operations performed during the periods T.sub.26 to T.sub.29 can be performed by the pixel circuits P.sub.N and P.sub.OB in each control group of the pixel array 10.

(114) Subsequently, if the discharge control line OFG goes to the intermediate voltage M.sub.22 during a period T.sub.30, a potential barrier under the gate of the discharge transistor 15 increases to a level between an ON mode and an OFF mode. Therefore, the discharge of charges from the photodiode PD stops. The operation performed during the period T.sub.30 can be simultaneously performed by all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10. The accumulation of charges in the photodiode PD may start from the period T.sub.30. In this case, the timing when the discharge control line OFG goes to the intermediate voltage M.sub.22 during the period T.sub.30 is the timing of an electronic shutter (particularly, global shutter). In addition, in this case, in all the control groups, the period T.sub.30 is not necessarily required to start after the completion of the operations performed during the periods T.sub.26 to T.sub.29 as illustrated in FIGS. 12 and 13, and there may be a control group in which the period T.sub.30 starts before the start of the operations performed during the periods T.sub.26 to T.sub.29 or in the middle of the operations performed during the periods T.sub.26 to T.sub.29.

(115) As described above, in the solid-state image sensor 1 of the fourth embodiment of the present invention, it is possible to directly reduce a fluctuation in the output of the pixel circuits P.sub.N and P.sub.OB belonging to the same control group, which is a cause of pseudo-smear, by limiting the upper limit amount of the charges E accumulated in the photodiode PD. As a result, it is possible to effectively reduce the occurrence of pseudo-smear by adopting a simple configuration and operation in which the upper limit amount of the charges E eventually retained in the floating diffusion area FD is limited.

(116) In the solid-state image sensor 1 of the fourth embodiment of the present invention, the upper limit amount of the charges E eventually retained in the floating diffusion area FD is further decreased to the extent corresponding to the condition in which pseudo-smear is likely to appear due to a high A/D conversion gain. As a result, it is possible to effectively reduce the occurrence of pseudo-smear as necessary.

(117) <Fifth Embodiment>

(118) Hereinafter, a solid-state image sensor of a fifth embodiment of the present invention will be described. The solid-state image sensor of the fifth embodiment of the present invention is equivalent to a modification example of the solid-state image sensor of the fourth embodiment of the present invention. Hereinafter, the points of difference between the solid-state image sensor of the fifth embodiment of the present invention and the solid-state image sensor of the fourth embodiment of the present invention will be described with reference to the accompanying drawings.

(119) FIG. 14 is a timing chart illustrating the operation of a pixel circuit of the solid-state image sensor of the fifth embodiment of the present invention. FIG. 14 corresponds to FIG. 12 which illustrates the operation of the solid-state image sensor of the fourth embodiment of the present invention. Similar to FIG. 12, reference sign M.sub.21 is assigned to an intermediate voltage in a case where a gain is low, and reference sign M.sub.22 is assigned to an intermediate voltage in a case where a gain is high. In FIG. 14, a fluctuation in the voltage of the output signal line VS is illustrated in an emphasized manner, and the illustration of noise superimposed on the transfer control line TX or the reset control line RST is omitted.

(120) As illustrated in FIG. 14, in the solid-state image sensor 1 of the fifth embodiment of the present invention, the discharge control line OFG goes to the low voltage L or the intermediate voltage M.sub.22 during periods apart from a period during which the discharge control line OFG goes to the high voltage H. Particularly, during periods apart from the periods T.sub.21 to T.sub.29, the discharge control line OFG goes to the low voltage L, and thus the discharge transistor 15 enters an OFF mode.

(121) As such, if the discharge transistor 15 enters an OFF mode, the concentration of charges (positive holes) having polarity opposite to that of charges (electrons) accumulated in the photodiode PD may increase under the gate of the discharge transistor 15. Accordingly, charges generated due to dark current can be inhibited from flowing into the photodiode PD.

(122) A period during which the discharge control line OFG goes to the low voltage L (period during which the low voltage L is applied to the gate of the discharge transistor 15) may account for 90% or greater of a period that is the sum of the period during which the discharge control line OFG goes to the low voltage L (period during which the low voltage L is applied to the gate of the discharge transistor 15) and periods during which the discharge control line OFG goes to the intermediate voltages M.sub.21 and M.sub.22 (periods during which the intermediate voltages M.sub.21 and M.sub.22 are applied to the gate of the discharge transistor 15).

(123) In this configuration, dark current which increases due to the intermediate voltages M.sub.21 and M.sub.22 being used instead of the low voltage L can be reduced to one tenth or less.

(124) <Sixth Embodiment>

(125) Hereinafter, a solid-state image sensor of a sixth embodiment of the present invention will be described. The only difference between the solid-state image sensor of the sixth embodiment of the present invention and the solid-state image sensor of the fourth embodiment of the present invention is a portion of the configuration and operation of the pixel circuits P.sub.N and P.sub.OB. Hereinafter, the points of difference between the solid-state image sensor of the sixth embodiment of the present invention and the solid-state image sensor of the fourth embodiment of the present invention will be described with reference to the accompanying drawings.

(126) FIG. 15 is a circuit diagram of a pixel circuit of the solid-state image sensor of the sixth embodiment of the present invention. As illustrated in FIG. 15, each of the effective pixel circuit P.sub.N and the OB pixel circuit P.sub.OB includes the photodiode PD; the floating diffusion area FD; the output transistor 12; the reset transistor 13; the selective transistor 14; the discharge transistor 15; a memory area (charge retaining unit) MEM that temporarily retains charges before being transferred from the photodiode PD to the floating diffusion area FD; a first transfer gate (first transfer unit) 16 through which charges are transferred from the photodiode PD to the memory area MEM; and a second transfer gate (second transfer unit) 17 through which charges retained by the memory area MEM are transferred to the floating diffusion area FD.

(127) Since charges accumulated by the photodiode PD are transferred to the floating diffusion area FD via the first transfer gate 16 and the second transfer gate 17, it can be said that the first transfer gate 16 and the second transfer gate 17 are equivalent to the transfer gate 11 of the solid-state image sensor of the first to fifth embodiments. The first transfer gate 16 and the second transfer gate 17 are different from the transfer gate 11 of the solid-state image sensor of the first to fifth embodiments in that the first transfer gate 16 and the second transfer gate 17 can be individually controlled, and are capable of temporarily retaining charges in the memory area MEM in the middle of transferring charges from the photodiode PD to the floating diffusion area FD.

(128) The anode of the photodiode PD is grounded. The first transfer gate 16 is connected to a first transfer control line TRX. The second transfer gate 17 is connected to a second transfer control line TRG. The output transistor 12 has a gate connected to the floating diffusion area FD, a drain connected to the common power supply line VD, and a source connected to the drain of the selective transistor 14. The reset transistor 13 has a gate connected to the reset control line RST, a drain connected to the common power supply line VD, and a source connected to the floating diffusion area FD. The selective transistor 14 has a gate connected to a selection control line SEL, and a source connected to the output signal line VS. The discharge transistor 15 has a gate connected to the discharge control line OFG, a drain connected to the common power supply line VD, and a source connected to the cathode of the photodiode PD.

(129) The reset control line RST, the selection control line SEL, and the second transfer control line TRG are common to the pixel circuits P.sub.N and P.sub.OB which belong to the same control group in the pixel array 10. The first transfer control line TRX, the discharge control line OFG, and the common power supply line VD are common to all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10.

(130) FIG. 16 is a schematic sectional view illustrating an example of the configuration of a portion of the pixel circuit illustrated in FIG. 15. FIG. 16 illustrates a section of the path from the discharge transistor 15 to the floating diffusion area FD in the pixel circuit illustrated in FIG. 15.

(131) As illustrated in FIG. 16, each portion of the pixel circuit is provided in a P-well W that is formed inside of and on an upper surface side (upper side in FIG. 16, and hereinafter, referred to as an upper side) of an N-substrate S. A gate oxide film X is provided on an upper surface of the substrate S (well W), and various gates such as a gate 15G of the discharge transistor, the first transfer gate 16, and the second transfer gate 17 are provided on an upper surface of the gate oxide film X.

(132) The photodiode PD includes an N-type (N?) area that is formed inside of the P-well W. The photodiode PD accumulates charges (electrons), which are generated via photoelectric conversion, in this area. Strictly speaking, the photodiode is formed of a combination of a P-well which is a cathode and an N-type (N?) area which is an anode; however, herein, the photodiode PD refers to only the N-type (N?) area in which charges are accumulated.

(133) A P-type (P+) embedded area B is formed on the upper side of the photodiode PD and in the vicinity of an upper surface of the inside of the substrate S (well W). Since the embedded area B is formed, the photodiode PD accumulates charges at a position spaced from the upper surface of the substrate S which may have many defects. As a result, dark current is reduced.

(134) A drain 15D of the discharge transistor and the floating diffusion area FD are N-type (N+) areas which are formed in the vicinity of the upper surface of the inside of the substrate S (well W). The gate 15G of the discharge transistor is formed on the uppers surface of the gate oxide film X at a position at which the gate 15G covers an area between the drain 15D of the discharge transistor and the photodiode PD. The photodiode PD is equivalent to the source of the discharge transistor.

(135) The memory area MEM is an N-type (N) area that is formed in the vicinity of the upper surface of the inside of the substrate S (well W). The memory area MEM is provided in an area between the photodiode PD and the floating diffusion area FD.

(136) The first transfer gate 16 is formed on the upper surface of the gate oxide film X at a position at which the first transfer gate 16 covers an area between the photodiode PD and the memory area MEM, and a portion or the entirety of the memory area MEM. The second transfer gate 17 is formed on the upper surface of the gate oxide film X at a position at which the second transfer gate 17 covers an area between the memory area MEM and the floating diffusion area FD.

(137) FIG. 17 is a timing chart illustrating the operation of the pixel circuit of the solid-state image sensor of the sixth embodiment of the present invention. FIGS. 18 and 19 are potential diagrams of an effective pixel circuit that performs the operation illustrated in FIG. 17. FIGS. 17 to 19 correspond to FIGS. 12 and 13 which illustrate the operation of the solid-state image sensor of the fourth embodiment of the present invention. Similar to FIGS. 12 and 13, reference sign M.sub.31 is assigned to an intermediate voltage or a potential barrier in a case where a gain is low, and reference sign M.sub.32 is assigned to an intermediate voltage or a potential barrier in a case where a gain is high. In FIG. 17, a fluctuation in the voltage of the output signal line VS is illustrated in an emphasized manner, and the illustration of noise superimposed on the second transfer control line TRG or the reset control line RST is omitted.

(138) Although in FIGS. 17 to 19 illustration starts from a period T.sub.31, the accumulation of the charges E in the photodiode PD is assumed to start at a certain timing before the period T.sub.31 (electronic shutter). At this time, initially, the discharge control line OFG goes to the high voltage H, and the discharge transistor 15 enters an ON mode. Therefore, charges in the photodiode PD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD. The discharge control line OFG goes to the low voltage L, and thus the accumulation of the charges E in the photodiode PD starts. Since light is not incident on the OB pixel circuit P.sub.OB, the generation of charges via photoelectric conversion does not occur, and charges are not accumulated in the photodiode PD, but charges may be accumulated due to dark current or the like.

(139) As illustrated in FIGS. 17 to 19, first, both the second transfer control line TRG and the reset control line RST go to the high voltage H during the period T.sub.31, and both the transistor including the second transfer gate 17 as a gate and the reset transistor 13 enter an ON mode. Therefore, charges in the memory area MEM and the floating diffusion area FD are discharged to the common power supply line VD.

(140) Subsequently, if the reset control line RST goes to the low voltage L during a period T.sub.32, a potential barrier under the gate of the reset transistor 13 increases, and the reset transistor 13 enters an OFF mode. If the second transfer control line TRG goes to an intermediate voltage M.sub.32 at the same time, a potential barrier under the second transfer gate 17 is present between an ON mode and an OFF mode.

(141) Subsequently, if the first transfer control line TRX goes to the high voltage H during a period T.sub.33, a potential barrier under the first transfer gate 16 decreases. That is, the potential barrier of the area between the photodiode PD and the memory area MEM decreases, and the potential of the memory area MEM decreases. Accordingly, the charges E in the photodiode PD are transferred to the memory area MEM. Since photoelectric conversion is not performed in the OB pixel circuit P.sub.OB, almost no charges are transferred to the memory area MEM.

(142) Subsequently, if the first transfer control line TRX goes to the low voltage L during a period T.sub.34, a potential barrier under the first transfer gate 16 increases. That is, the potential barrier of the area between the photodiode PD and the memory area MEM increases, and the potential of the memory area MEM increases. Accordingly, the transfer of the charges E from the photodiode PD to the memory area MEM stops. In this case, the charges E exceeding the potential barrier (that is, the upper limit amount of charges retained by the memory area MEM) under the second transfer gate 17 overflow from the memory area MEM, and are discharged to the floating diffusion area FD. In a case where a set gain is low, the second control line TRG goes to an intermediate voltage M.sub.31 lower than the intermediate voltage M.sub.32, and a potential barrier under the second transfer gate 17 is larger than that at the intermediate voltage M.sub.32.

(143) Subsequently, if the discharge control line OFG goes to the high voltage H during a period T.sub.35, a potential barrier under the gate 15G of the discharge transistor 15 decreases, and the discharge transistor 15 enters an ON mode. Therefore, the charges E in the photodiode PD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD. The aforementioned operations performed during the periods T.sub.31 to T.sub.35 can be simultaneously performed by all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10.

(144) Subsequently, if the selection control line SEL goes to the high voltage H during a period T.sub.36, the selective transistor 14 enters an ON mode, and a signal (voltage) output from the output transistor 12 is applied to the output signal line VS.

(145) Subsequently, if the reset control line RST goes to the high voltage H during a period T.sub.37, a potential barrier under the gate of the reset transistor 13 decreases, and the reset transistor 13 enters an ON mode. Therefore, charges in the floating diffusion area FD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD.

(146) Subsequently, if the reset control line RST goes to the low voltage L during a period T.sub.38, a potential barrier under the gate of the reset transistor 13 increases, and the reset transistor 13 enters an OFF mode. At the end of the period T.sub.38 (after a settling time has elapsed), the A/D conversion circuit 23 samples the voltage V.sub.rN of the output signal line VS in a state where charges are not retained in the floating diffusion area FD of the effective pixel circuit P.sub.N, and the voltage V.sub.rOB of the output signal line VS in a state where charges are not retained in the floating diffusion area FD of the OB pixel circuit P.sub.OB.

(147) Subsequently, if the second transfer control line TRG goes to the high voltage H during a period T.sub.39, a potential barrier under the second transfer gate 17 decreases, and the transistor including the second transfer gate 17 as a gate enters an ON mode. Therefore, the charges E in the memory area MEM are transferred to the floating diffusion area FD. In this case, as described above, the charges E transferred from the memory area MEM to the floating diffusion area FD are the charges E which are accumulated in the memory area MEM as the result of limiting the upper limit amount by applying the intermediate voltage M.sub.32 to the second transfer control line TRG. Since as described above, the OB pixel circuit P.sub.OB retains almost no charges to be transferred to and accumulated in the memory area MEM, almost no charges are transferred to the floating diffusion area FD.

(148) Subsequently, if the second transfer control line TRG goes to the intermediate voltage M.sub.32 during a period T.sub.40, a potential barrier under the second transfer gate 17 increases to a level between an ON mode and an OFF mode. Therefore, the transfer of charges from the memory area MEM to the floating diffusion area FD stops. At the end of the period T.sub.40 (after a settling time has elapsed), the A/D conversion circuit 23 samples the voltage V.sub.sN of the output signal line VS which corresponds to charges retained in the floating diffusion area FD of the effective pixel circuit P.sub.N, and the voltage V.sub.sOB of the output signal line VS which corresponds to charges retained in the floating diffusion area FD of the OB pixel circuit P.sub.OB.

(149) Subsequently, if the selection control line SEL goes to a low voltage during a period T.sub.41, the selective transistor 14 enters an OFF mode. The aforementioned operations performed during the periods T.sub.36 to T.sub.41 can be performed by the pixel circuits P.sub.N and P.sub.OB in each control group of the pixel array 10.

(150) Subsequently, if the discharge control line OFG goes to the low voltage L during a period T.sub.42, a potential barrier under the gate 15G of the discharge transistor 15 increases, and the discharge transistor 15 enters an OFF mode. Therefore, the discharge of charges from the photodiode PD stops. The operation performed during the period T.sub.42 can be simultaneously performed by all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10. The accumulation of charges in the photodiode PD may start from the period T.sub.42. In this case, the timing when the discharge control line OFG goes to the low voltage L during the period T.sub.42 is the timing of an electronic shutter (particularly, global shutter). In addition, in this case, in all the control groups, the period T.sub.42 is not necessarily required to start after the completion of the operations performed during the periods T.sub.36 to T.sub.41 as illustrated in FIGS. 17 to 19, and there may be a control group in which the period T.sub.42 starts before the start of the operations performed during the periods T.sub.36 to T.sub.41 or in the middle of the operations performed during the periods T.sub.36 to T.sub.41.

(151) As described above, in the solid-state image sensor 1 of the sixth embodiment of the present invention, it is possible to directly reduce a fluctuation in the output of the pixel circuits P.sub.N and P.sub.OB belonging to the same control group, which is a cause of pseudo-smear, by limiting the upper limit amount of the charges E retained in the memory area MEM. As a result, it is possible to effectively reduce the occurrence of pseudo-smear by adopting a simple configuration and operation in which the upper limit amount of the charges E eventually retained in the floating diffusion area FD is limited.

(152) In the solid-state image sensor 1 of the sixth embodiment of the present invention, the upper limit amount of the charges E eventually retained in the floating diffusion area FD is further decreased to the extent corresponding to the condition in which pseudo-smear is likely to appear due to a high A/D conversion gain. As a result, it is possible to effectively reduce the occurrence of pseudo-smear as necessary.

(153) <Seventh Embodiment>

(154) Hereinafter, a solid-state image sensor of a seventh embodiment of the present invention will be described. The only difference between the solid-state image sensor of the seventh embodiment of the present invention and the solid-state image sensor of the sixth embodiment of the present invention is a portion of an operation. Hereinafter, the points of difference between the solid-state image sensor of the seventh embodiment of the present invention and the solid-state image sensor of the sixth embodiment of the present invention will be described with reference to the accompanying drawings.

(155) FIG. 20 is a timing chart illustrating the operation of a pixel circuit of the solid-state image sensor of the seventh embodiment of the present invention. FIGS. 21 and 22 are potential diagrams of an effective pixel circuit that performs the operation illustrated in FIG. 20. FIGS. 20 to 22 respectively correspond to FIGS. 17 to 19 which illustrate the operation of the solid-state image sensor of the sixth embodiment of the present invention in a case where a set gain is high. Similar to FIGS. 17 to 19, reference sign M.sub.41 is assigned to an intermediate voltage or a potential barrier in a case where a gain is low, and reference sign M.sub.42 is assigned to an intermediate voltage or a potential barrier in a case where a gain is high. In FIG. 20, a fluctuation in the voltage of the output signal line VS is illustrated in an emphasized manner, and the illustration of noise superimposed on the second transfer control line TRG or the reset control line RST is omitted.

(156) Although in FIGS. 20 to 22 illustration starts from a period T.sub.51, the accumulation of the charges E in the photodiode PD is assumed to start at a certain timing before the period T.sub.51 (electronic shutter). At this time, initially, the discharge control line OFG goes to the high voltage H, and the discharge transistor 15 enters an ON mode. Therefore, charges in the photodiode PD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD. The discharge control line OFG goes to an intermediate voltage M.sub.42, and thus the accumulation of the charges E in the photodiode PD starts. Since light is not incident on the OB pixel circuit P.sub.OB, the generation of charges via photoelectric conversion does not occur, and charges are not accumulated in the photodiode PD, but charges may be accumulated due to dark current or the like.

(157) After the discharge control line OFG goes to the intermediate voltage M.sub.42, a potential barrier under the gate 15G of the discharge transistor 15 is present between an ON mode and an OFF mode. Accordingly, charges are being accumulated in the photodiode PD, and charges exceeding the potential barrier (that is, the upper limit amount of charges accumulated by the photodiode PD) under the gate 15G of the discharge transistor 15 are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD instead of being accumulated in the photodiode PD. In a case where a set gain is low, the discharge control line OFG goes to an intermediate voltage M.sub.41 lower than the intermediate voltage M.sub.42, and a potential barrier under the gate 15G of the discharge transistor 15 is larger than that at the intermediate voltage M.sub.42.

(158) As illustrated in FIGS. 20 to 22, both the second transfer control line TRG and the reset control line RST go to the high voltage H during the period T.sub.51, and both the transistor including the second transfer gate 17 as a gate and the reset transistor 13 enter an ON mode. Therefore, charges in the memory area MEM and the floating diffusion area FD are discharged to the common power supply line VD.

(159) Subsequently, if the reset control line RST goes to the low voltage L during a period T.sub.52, a potential barrier under the gate of the reset transistor 13 increases, and the reset transistor 13 enters an OFF mode. If the second transfer control line TRG goes to the low voltage L at the same time, a potential barrier under the second transfer gate 17 increases, and the transistor including the second transfer gate 17 as a gate enters an OFF mode.

(160) Subsequently, if the first transfer control line TRX goes to the high voltage H during a period T.sub.53, a potential barrier under the first transfer gate 16 decreases. That is, the potential barrier of the area between the photodiode PD and the memory area MEM decreases, and the potential of the memory area MEM decreases. Accordingly, the charges E in the photodiode PD are transferred to the memory area MEM. In this case, as described above, the charges E transferred from the photodiode PD to the memory area MEM are the charges E which are accumulated in the photodiode PD as the result of limiting the upper limit amount by applying the intermediate voltage M.sub.42 to the discharge control line OFG. Since photoelectric conversion is not performed in the OB pixel circuit P.sub.OB, almost no charges are transferred to the memory area MEM.

(161) Subsequently, if the first transfer control line TRX goes to the low voltage L during a period T.sub.54, a potential barrier under the first transfer gate 16 increases. That is, the potential barrier of the area between the photodiode PD and the memory area MEM increases, and the potential of the memory area MEM increases. Accordingly, the transfer of the charges E from the photodiode PD to the memory area MEM stops.

(162) Subsequently, if the discharge control line OFG goes to the high voltage H during a period T.sub.55, a potential barrier under the gate 15G of the discharge transistor 15 decreases, and the discharge transistor 15 enters an ON mode. Therefore, the charges E in the photodiode PD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD. The aforementioned operations performed during the periods T.sub.51 to T.sub.55 can be simultaneously performed by all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10.

(163) Subsequently, if the selection control line SEL goes to the high voltage H during a period T.sub.56, the selective transistor 14 enters an ON mode, and a signal (voltage) output from the output transistor 12 is applied to the output signal line VS.

(164) Subsequently, if the reset control line RST goes to the high voltage H during a period T.sub.57, a potential barrier under the gate of the reset transistor 13 decreases, and the reset transistor 13 enters an ON mode. Therefore, charges in the floating diffusion area FD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD.

(165) Subsequently, if the reset control line RST goes to the low voltage L during a period T.sub.58, a potential barrier under the gate of the reset transistor 13 increases, and the reset transistor 13 enters an OFF mode. At the end of the period T.sub.58 (after a settling time has elapsed), the A/D conversion circuit 23 samples the voltage V.sub.rN of the output signal line VS in a state where charges are not retained in the floating diffusion area FD of the effective pixel circuit P.sub.N, and the voltage V.sub.rOB of the output signal line VS in a state where charges are not retained in the floating diffusion area FD of the OB pixel circuit P.sub.OB.

(166) Subsequently, if the second transfer control line TRG goes to the high voltage H during a period T.sub.59, a potential barrier under the second transfer gate 17 decreases, and the transistor including the second transfer gate 17 as a gate enters an ON mode. Therefore, the charges E in the memory area MEM are transferred to the floating diffusion area FD. Since as described above, the OB pixel circuit P.sub.OB retains almost no charges to be transferred to and accumulated in the memory area MEM, almost no charges are transferred to the floating diffusion area FD.

(167) Subsequently, if the second transfer control line TRG goes to the low voltage L during a period T.sub.60, a potential barrier under the second transfer gate 17 increases, and the transistor including the second transfer gate 17 as a gate enters an OFF mode. Therefore, the transfer of charges from the memory area MEM to the floating diffusion area FD stops. At the end of the period T.sub.60 (after a settling time has elapsed), the A/D conversion circuit 23 samples the voltage V.sub.sN of the output signal line VS which corresponds to charges retained in the floating diffusion area FD of the effective pixel circuit P.sub.N, and the voltage V.sub.sOB of the output signal line VS which corresponds to charges retained in the floating diffusion area FD of the OB pixel circuit P.sub.OB.

(168) Subsequently, if the selection control line SEL goes to a low voltage during a period T.sub.61, the selective transistor 14 enters an OFF mode. The aforementioned operations performed during the periods T.sub.56 to T.sub.61 can be performed by the pixel circuits P.sub.N and P.sub.OB in each control group of the pixel array 10.

(169) Subsequently, if the discharge control line OFG goes to the intermediate voltage M.sub.42 during a period T.sub.62, a potential barrier under the gate 15G of the discharge transistor 15 increases to a level between an ON mode and an OFF mode. Therefore, the discharge of charges from the photodiode PD stops. The operation performed during the period T.sub.62 can be simultaneously performed by all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10. The accumulation of charges in the photodiode PD may start from the period T.sub.62. In this case, the timing when the discharge control line OFG goes to the intermediate voltage M.sub.42 during the period T.sub.62 is the timing of an electronic shutter (particularly, global shutter). In addition, in this case, in all the control groups, the period T.sub.62 is not necessarily required to start after the completion of the operations performed during the periods T.sub.56 to T.sub.61 as illustrated in FIGS. 20 to 22, and there may be a control group in which the period T.sub.62 starts before the start of the operations performed during the periods T.sub.56 to T.sub.61 or in the middle of the operations performed during the periods T.sub.56 to T.sub.61.

(170) As described above, in the solid-state image sensor 1 of the seventh embodiment of the present invention, it is possible to directly reduce a fluctuation in the output of the pixel circuits P.sub.N and P.sub.OB belonging to the same control group, which is a cause of pseudo-smear, by limiting the upper limit amount of the charges E retained in the photodiode PD. As a result, it is possible to effectively reduce the occurrence of pseudo-smear by adopting a simple configuration and operation in which the upper limit amount of the charges E eventually retained in the floating diffusion area FD is limited.

(171) In the solid-state image sensor 1 of the seventh embodiment of the present invention, the upper limit amount of the charges E eventually retained in the floating diffusion area FD is further decreased to the extent corresponding to the condition in which pseudo-smear is likely to appear due to a high A/D conversion gain. As a result, it is possible to effectively reduce the occurrence of pseudo-smear as necessary.

(172) <Eighth Embodiment>

(173) Hereinafter, a solid-state image sensor of an eighth embodiment of the present invention will be described. The solid-state image sensor of the eighth embodiment of the present invention is equivalent to a modification example of the solid-state image sensor of the seventh embodiment of the present invention. Hereinafter, the points of difference between the solid-state image sensor of the eighth embodiment of the present invention and the solid-state image sensor of the seventh embodiment of the present invention will be described with reference to the accompanying drawings.

(174) FIG. 23 is a timing chart illustrating the operation of a pixel circuit of the solid-state image sensor of the eighth embodiment of the present invention. FIG. 23 corresponds to FIG. 20 which illustrates the operation of the solid-state image sensor of the seventh embodiment of the present invention. Similar to FIG. 20, reference sign M.sub.41 is assigned to an intermediate voltage in a case where a gain is low, and reference sign M.sub.42 is assigned to an intermediate voltage in a case where a gain is high. In FIG. 23, a fluctuation in the voltage of the output signal line VS is illustrated in an emphasized manner, and the illustration of noise superimposed on the transfer control line TX or the reset control line RST is omitted.

(175) As illustrated in FIG. 23, in the solid-state image sensor 1 of the eighth embodiment of the present invention, the discharge control line OFG goes to the low voltage L or the intermediate voltage M.sub.42 during periods apart from a period during which the discharge control line OFG goes to the high voltage H. Particularly, during periods apart from the periods T.sub.51 to T.sub.61, the discharge control line OFG goes to the low voltage L, and thus the discharge transistor 15 enters an OFF mode.

(176) As such, if the discharge transistor 15 enters an OFF mode, the concentration of charges (positive holes) having polarity opposite to that of charges (electrons) accumulated in the photodiode PD may increase under the gate 15G of the discharge transistor 15. Accordingly, charges generated due to dark current can be inhibited from flowing into the photodiode PD.

(177) A period during which the discharge control line OFG goes to the low voltage L (period during which the low voltage L is applied to the gate 15G of the discharge transistor 15) may account for 90% or greater of a period that is the sum of the period during which the discharge control line OFG goes to the low voltage L (period during which the low voltage L is applied to the gate 15G of the discharge transistor 15) and periods during which the discharge control line OFG goes to the intermediate voltages M.sub.41 and M.sub.42 (periods during which the intermediate voltages M.sub.41 and M.sub.42 are applied to the gate 15G of the discharge transistor 15).

(178) In this configuration, dark current which increases due to the intermediate voltages M.sub.41 and M.sub.42 being used instead of the low voltage L can be reduced to one tenth or less.

(179) <Ninth Embodiment>

(180) Hereinafter, a solid-state image sensor of a ninth embodiment of the present invention will be described. The only difference between the solid-state image sensor of the ninth embodiment of the present invention and the solid-state image sensor of the sixth embodiment of the present invention is a portion of an operation. Hereinafter, the points of difference between the solid-state image sensor of the ninth embodiment of the present invention and the solid-state image sensor of the sixth embodiment of the present invention will be described with reference to the accompanying drawings.

(181) FIG. 24 is a timing chart illustrating the operation of a pixel circuit of the solid-state image sensor of the ninth embodiment of the present invention. FIGS. 25 and 26 are potential diagrams of an effective pixel circuit that performs the operation illustrated in FIG. 24. FIGS. 24 to 26 respectively correspond to FIGS. 17 to 19 which illustrate the operation of the solid-state image sensor of the sixth embodiment of the present invention in a case where a set gain is high. Similar to FIGS. 17 to 19, reference sign M.sub.51 is assigned to an intermediate voltage or a potential barrier in a case where a gain is low, and reference sign M.sub.52 is assigned to an intermediate voltage or a potential barrier in a case where a gain is high. In FIG. 24, a fluctuation in the voltage of the output signal line VS is illustrated in an emphasized manner, and the illustration of noise superimposed on the second transfer control line TRG or the reset control line RST is omitted.

(182) Although in FIGS. 24 to 26 illustration starts from a period T.sub.71, the accumulation of the charges E in the photodiode PD is assumed to start at a certain timing before the period T.sub.71 (electronic shutter). At this time, initially, the discharge control line OFG goes to the high voltage H, and the discharge transistor 15 enters an ON mode. Therefore, charges in the photodiode PD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD. The discharge control line OFG goes to the low voltage L, and thus the accumulation of the charges E in the photodiode PD starts. Since light is not incident on the OB pixel circuit P.sub.OB, the generation of charges via photoelectric conversion does not occur, and charges are not accumulated in the photodiode PD, but charges may be accumulated due to dark current or the like.

(183) As illustrated in FIGS. 24 to 26, first, both the second transfer control line TRG and the reset control line RST go to the high voltage H during the period T.sub.71, and both the transistor including the second transfer gate 17 as a gate and the reset transistor 13 enter an ON mode. Therefore, charges in the memory area MEM and the floating diffusion area FD are discharged to the common power supply line VD.

(184) Subsequently, if the second transfer control line TRG goes to the low voltage L during a period T.sub.72, a potential barrier under the second transfer gate 17 increases, and the transistor including the second transfer gate 17 as a gate enters an OFF mode. If the reset control line RST goes to an intermediate voltage M.sub.52 at the same time, a potential barrier under the gate of the reset transistor 13 is present between an ON mode and an OFF mode.

(185) Subsequently, if the first transfer control line TRX goes to the high voltage H during a period T.sub.73, a potential barrier under the first transfer gate 16 decreases. That is, the potential barrier of the area between the photodiode PD and the memory area MEM decreases, and the potential of the memory area MEM decreases. Accordingly, the charges E in the photodiode PD are transferred to the memory area MEM. Since photoelectric conversion is not performed in the OB pixel circuit P.sub.OB, almost no charges are transferred to the memory area MEM.

(186) Subsequently, if the first transfer control line TRX goes to the low voltage L during a period T.sub.74, a potential barrier under the first transfer gate 16 increases. That is, the potential barrier of the area between the photodiode PD and the memory area MEM increases, and the potential of the memory area MEM increases. Accordingly, the transfer of the charges E from the photodiode PD to the memory area MEM stops.

(187) Subsequently, if the discharge control line OFG goes to the high voltage H during a period T.sub.75, a potential barrier under the gate 15G of the discharge transistor 15 decreases, and the discharge transistor 15 enters an ON mode. Therefore, the charges E in the photodiode PD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD. The aforementioned operations performed during the periods T.sub.71 to T.sub.75 can be simultaneously performed by all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10.

(188) Subsequently, if the selection control line SEL goes to the high voltage H during a period T.sub.76, the selective transistor 14 enters an ON mode, and a signal (voltage) output from the output transistor 12 is applied to the output signal line VS.

(189) Subsequently, if the reset control line RST goes to the high voltage H during a period T.sub.77, a potential barrier under the gate of the reset transistor 13 decreases, and the reset transistor 13 enters an ON mode. Therefore, charges in the floating diffusion area FD are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD.

(190) Subsequently, if the reset control line RST goes to the intermediate voltage M.sub.52 during a period T.sub.78, a potential barrier under the gate of the reset transistor 13 increases to a level between an ON mode and an OFF mode. At the end of the period T.sub.78 (after a settling time has elapsed), the A/D conversion circuit 23 samples the voltage V.sub.rN of the output signal line VS in a state where charges are not retained in the floating diffusion area FD of the effective pixel circuit P.sub.N, and the voltage V.sub.rOB of the output signal line VS in a state where charges are not retained in the floating diffusion area FD of the OB pixel circuit P.sub.OB.

(191) Subsequently, if the second transfer control line TRG goes to the high voltage H during a period T.sub.79, a potential barrier under the second transfer gate 17 decreases, and the transistor including the second transfer gate 17 as a gate enters an ON mode. Therefore, the charges E in the memory area MEM are transferred to the floating diffusion area FD. In this case, the charges E exceeding the potential barrier (that is, the upper limit amount of charges retained by the floating diffusion area FD) under the gate of the reset transistor 13 are discharged to the outside of the pixel circuits P.sub.N and P.sub.OB via the common power supply line VD. In a case where a set gain is low, the reset control line RST goes to an intermediate voltage M.sub.51 lower than the intermediate voltage M.sub.52, and a potential barrier under the gate 17 of the reset transistor 13 is larger than that at the intermediate voltage M.sub.52.

(192) Subsequently, if the second transfer control line TRG goes to the low voltage L during a period T.sub.80, a potential barrier under the second transfer gate 17 increases, and the transistor including the second transfer gate 17 as a gate enters an OFF mode. Therefore, the transfer of charges from the memory area MEM to the floating diffusion area FD stops. At the end of the period T.sub.80 (after a settling time has elapsed), the A/D conversion circuit 23 samples the voltage V.sub.sN of the output signal line VS which corresponds to charges retained in the floating diffusion area FD of the effective pixel circuit P.sub.N, and the voltage V.sub.sOB of the output signal line VS which corresponds to charges retained in the floating diffusion area FD of the OB pixel circuit P.sub.OB.

(193) Subsequently, if the selection control line SEL goes to a low voltage during a period T.sub.81, the selective transistor 14 enters an OFF mode. The aforementioned operations performed during the periods T.sub.76 to T.sub.81 can be performed by the pixel circuits P.sub.N and P.sub.OB in each control group of the pixel array 10.

(194) Subsequently, if the discharge control line OFG goes to the low voltage L during a period T.sub.82, a potential barrier under the gate 15G of the discharge transistor 15 increases, and the discharge transistor 15 enters an OFF mode. Therefore, the discharge of charges from the photodiode PD stops. The operation performed during the period T.sub.82 can be simultaneously performed by all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10. The accumulation of charges in the photodiode PD may start from the period T.sub.82. In this case, the timing when the discharge control line OFG goes to the low voltage L during the period T.sub.82 is the timing of an electronic shutter (particularly, global shutter). In addition, in this case, in all the control groups, the period T.sub.82 is not necessarily required to start after the completion of the operations performed during the periods T.sub.76 to T.sub.81 as illustrated in FIGS. 24 to 26, and there may be a control group in which the period T.sub.82 starts before the start of the operations performed during the periods T.sub.76 to T.sub.81 or in the middle of the operations performed during the periods T.sub.76 to T.sub.81.

(195) As described above, in the solid-state image sensor 1 of the ninth embodiment of the present invention, it is possible to directly reduce a fluctuation in the output of the pixel circuits P.sub.N and P.sub.OB belonging to the same control group, which is a cause of pseudo-smear, by limiting the upper limit amount of the charges E retained in the floating diffusion area FD. As a result, it is possible to effectively reduce the occurrence of pseudo-smear by adopting a simple configuration and operation in which the upper limit amount of the charges E eventually retained in the floating diffusion area FD is limited.

(196) In the solid-state image sensor 1 of the ninth embodiment of the present invention, the upper limit amount of the charges E eventually retained in the floating diffusion area FD is further decreased to the extent corresponding to the condition in which pseudo-smear is likely to appear due to a high A/D conversion gain. As a result, it is possible to effectively reduce the occurrence of pseudo-smear as necessary.

(197) <Modifications and the Like>

(198) A portion of the solid-state image sensor 1 of the aforementioned embodiments can be modified as will be described, and modification examples can be realized.

(199) [1] The intermediate voltages M.sub.1, M.sub.2, M.sub.11, M.sub.12, . . . M.sub.51 and M.sub.52 applied to the pixel circuits P.sub.N and P.sub.OB by the vertical scan circuit 21 may be negative voltages in correspondence with the magnitude of a gain. An example of the configuration of a solid-state image sensor in this case will be described with reference to the accompanying drawings. FIG. 27 is a block diagram illustrating the configuration of a modification example of the solid-state image sensor of the embodiments of the present invention.

(200) A solid-state image sensor 1A illustrated in FIG. 27 is different from the solid-state image sensor 1 illustrated in FIG. 1 in that the solid-state image sensor 1A includes a negative voltage generation circuit 29 which generates a negative voltage and applies the generated negative voltage to the intermediate voltage generation circuit 25. In this case, the intermediate voltage generation circuit 25 is capable of generating the intermediate voltages M.sub.1, M.sub.2, M.sub.11, M.sub.12, . . . M.sub.51, and M.sub.52 which are negative voltages in correspondence with the magnitude of a gain.

(201) The low voltage L applied to pixel circuits P.sub.N and P.sub.OB by the vertical scan circuit 21 may be a negative voltage. An example of the configuration of a solid-state image sensor in this case will be described with reference to the accompanying drawings. FIG. 28 is a block diagram illustrating the configuration of another modification example of the solid-state image sensor of the embodiments of the present invention.

(202) A solid-state image sensor 1B illustrated in FIG. 28 is different from the solid-state image sensor 1 illustrated in FIG. 1 in that the solid-state image sensor 1B includes the negative voltage generation circuit 29 which generates a negative voltage and applies the generated negative voltage to the intermediate voltage generation circuit 25 and the vertical scan circuit 21. In this case, the intermediate voltage generation circuit 25 is capable of generating the intermediate voltages M.sub.1, M.sub.2, M.sub.11, M.sub.12, . . . M.sub.51, and M.sub.52 which are negative voltages in correspondence with the magnitude of a gain. The vertical scan circuit 21 applies the negative voltage, which is applied from the negative voltage generation circuit 28, to the pixel circuits P.sub.N and P.sub.OB as the low voltage L.

(203) As in the modification examples, if the vertical scan circuit 21 is configured to apply the intermediate voltages M.sub.1, M.sub.2, M.sub.11, M.sub.12, . . . M.sub.51, and M.sub.52 or the low voltage L, which are negative voltages (voltages having a polarity different from that of the high voltage H) to the pixel circuits P.sub.N and P.sub.OB, the concentration of charges (positive holes) having a polarity opposite to that of charges (electrons) accumulated in the photodiode PD can be increased under the transfer gate 11 or the gate of the discharge transistor 15. Accordingly, charges generated due to dark current can be inhibited from flowing into the photodiode PD.

(204) The intermediate voltages M.sub.1, M.sub.2, M.sub.11, M.sub.12, . . . M.sub.51, and M.sub.52 or the low voltage L which are negative voltages may be applied to a gate (the gate of each of the transistors 12 to 15, the transfer gate 11, the first transfer gate 16, or the second transfer gate 17) of any transistor in the pixel circuits P.sub.N and P.sub.OB illustrated in FIGS. 2, 11, and 15. Particularly, as described above, a negative voltage is preferably applied to at least transfer gate 11 or the gate of the discharge transistor 15 because charges generated due to dark current can be inhibited from flowing into the photodiode PD.

(205) [2] The solid-state image sensor of the third embodiment of the present invention is equivalent to an example in which the low voltage L is applied to the transfer gates 11 of the pixel circuits P.sub.N and P.sub.OB of the solid-state image sensor of the second embodiment of the present invention so that the transistors including the transfer gates 11 as gates are capable of entering an OFF mode. The solid-state image sensor of the fifth embodiment of the present invention is equivalent to an example in which the low voltage L is applied to the gates of the discharge transistors 15 of the pixel circuits P.sub.N and P.sub.OB of the solid-state image sensor of the fourth embodiment of the present invention so that the discharge transistors 15 are capable of entering an OFF mode. Similarly, the solid-state image sensor of the first embodiment of the present invention may be also configured such that the low voltage L is applied to the gates of the reset transistors 13 of the pixel circuits P.sub.N and P.sub.OB to enable the reset transistors 13 to enter an OFF mode.

(206) The solid-state image sensor of the eighth embodiment of the present invention is equivalent to an example in which the low voltage L is applied to the gates 15G of the discharge transistors 15 of the pixel circuits P.sub.N and P.sub.OB of the solid-state image sensor of the seventh embodiment of the present invention so that the discharge transistors 15 are capable of entering an OFF mode. Similarly, the solid-state image sensor of the sixth embodiment of the present invention may be also configured such that the low voltage L is applied to the second transfer gates 17 of the pixel circuits P.sub.N and P.sub.OB to enable the transistors including the second transfer gates 17 as gates to enter an OFF mode. Similarly, the solid-state image sensor of the ninth embodiment of the present invention may be also configured such that the low voltage L is applied to the gates of the reset transistors 13 of the pixel circuits P.sub.N and P.sub.OB to enable the reset transistors 13 to enter an OFF mode.

(207) [3] If the upper limit amount of the charges E is excessively small, it is not possible to accumulate a sufficient amount of the charges E, and A/D converted data does not have the maximum value. If the upper limit amount of the charges E is excessively large, the reduction of the occurrence of pseudo-smear becomes difficult.

(208) It is preferable to adopt a method of setting the upper limit amount of the charges E (that is, a method of setting the intermediate voltages M.sub.1, M.sub.2, M.sub.11, M.sub.12, . . . M.sub.51, and M.sub.52) by which the upper limit amount is larger than or equal to the lower limit amount of charges at which data obtained via A/D conversion using a gain set by the A/D conversion circuit 23 has the maximum value, and is smaller than or equal to 1.5 times the lower limit amount.

(209) If the upper limit amount of the charges E is set by this setting method, A/D converted data is capable of having the maximum value, and it is possible to effectively reduce the occurrence of pseudo-smear.

(210) [4] The relationship between a set gain and an intermediate voltage generated by the intermediate voltage generation circuit 25 may be any type of relationship insofar as a relationship in which the intermediate voltage is increased to the extent of an increase in gain is satisfied. For example, an intermediate voltage may be increased linearly or non-linearly with an increase in gain (that is, the upper limit amount of the charges E is increased linearly or non-linearly). Alternatively, an intermediate voltage is increased in a stepwise manner with an increase in gain (that is, the upper limit amount of the charges E is increased in a stepwise manner).

(211) [5] In the pixel circuit illustrated in FIG. 2, the reset power supply line VR is common in each control group. Alternatively, the reset power supply line VR may be common to all the pixel circuits P.sub.N and P.sub.OB in the pixel array 10. The reset power supply line VR and the common power supply line VD may be common (the drain of the reset transistor 13 may be connected to the common power supply line VD). In a case where the reset power supply line VR is common in the pixel circuits P.sub.N and P.sub.OB, the pixel circuits P.sub.N and P.sub.OB are configured to include the selective transistors 14 as illustrated in FIGS. 11 and 15.

(212) In each of the pixel circuits illustrated in FIGS. 11 and 15, the drain of the reset transistor 13 is connected to the common power supply line VD. Alternatively, the drain of the reset transistor 13 may be connected to the reset power supply line VR that is provided separately from the common power supply line VD. The reset power supply line VR may be common in each control group (the same as in the first to third embodiments, and refer to FIG. 2).

(213) [6] Similar to the pixel circuits illustrated in FIGS. 11 and 15, the pixel circuit illustrated in FIG. 2 may be configured to include the selective transistor 14, or configured to include the selective transistor 14 and the discharge transistor 15.

(214) Similar to the pixel circuit illustrated in FIG. 11, each of the pixel circuits illustrated in FIGS. 11 and 15 may be configured so as not to include the selective transistor 14. In this case, the following modifications are preferably made: similar to the solid-state image sensor 1 of the first to third embodiments of the present invention, the pixel circuits P.sub.N and P.sub.OB in the pixel array 10 are sequentially operated in the unit of the control group (refer to FIGS. 4 to 10), and selective signal output means is provided instead of the selective transistor 14.

(215) [7] In the configurations illustrated in FIGS. 1, 27, and 28, the A/D conversion circuit 23 performs A/D conversion using a ramp wave generated by the ramp wave generation circuit 24. These configurations are merely examples, and the A/D conversion circuit 23 may perform A/D conversion using any method. As illustrated in FIGS. 1, 27, and 28, the configuration in which an A/D conversion gain can be easily changed is preferably adopted.

(216) [8] In the configurations illustrated in FIGS. 1, 27, and 28, the OB pixel circuits (light shielding film) P.sub.OB are provided only at a left end of the pixel array 10. This configuration is merely an example, and the OB pixel circuits P.sub.OB may be provided at any position in the pixel array 10. For example, the OB pixel circuits P.sub.OB may be provided at both ends of the pixel array 10. The OB pixel circuits P.sub.OB may be provided along the circumference (for example, left end, upper end, right end, and lower end) of the pixel array 10.

(217) In the configurations illustrated in FIGS. 1, 27, and 28, the pixel circuits P.sub.N and P.sub.OB are arrayed in a matrix pattern (arrayed in a vertical direction and a lateral direction in the drawings) in the pixel array 10. This configuration is merely an example, and the pixel circuits P.sub.N and P.sub.OB may be arrayed in any pattern in the pixel array 10. For example, the pixel circuits P.sub.N and P.sub.OB may be arrayed in the pixel array 10 in an oblique direction (direction inclined at ?45? with respect to the lateral direction in the drawings) of FIGS. 1, 27, and 28.

(218) [9] The pixel circuits P.sub.N and P.sub.OB in the same row which are arrayed in the lateral direction in FIG. 1 belong to the same control group. The method of setting a control group is merely an example, and a control group may be set by any method. For example, the pixel circuits P.sub.N and P.sub.OB which are not adjacent to and are spaced from each other may be contained in the same control group. Pixel circuits in multiple rows may be contained in the same control group. Pixel circuits in a certain area rather than a row may be contained in the same control group.

(219) [10] In the aforementioned example, the A/D conversion circuit performs A/D conversion on a correlated double sampled difference. Alternatively, the A/D conversion circuit 23 may directly perform A/D conversion on signals (voltages V.sub.sN and V.sub.sOB) of the output signal line VS which are acquired in a state where charges are retained in the floating diffusion areas FD of the pixel circuits P.sub.N and P.sub.OB.

(220) [11] In the aforementioned solid-state image sensors, each pixel circuit generates and accumulates electrons, and includes an N-channel FET. The solid-state image sensors to which the present invention can be applied are merely examples. For example, the present invention can be also applied to a solid-state image sensor which each pixel circuit accumulates positive holes, and includes a P-channel FET. The polarity or magnitude of a voltage applied to a transistor of each of the pixel circuits P.sub.N and P.sub.OB is suitably changed according to an application form so as to perform the same operation as in the aforementioned examples.

(221) [12] Features of the aforementioned solid-state image sensors can be combined together and realized insofar as the features are not contradictory to each other.

(222) For example, the solid-state image sensors of the first and ninth embodiments of the present invention perform an operation (first upper limit amount limiting operation) in which the charges E retained by the floating diffusion area FD are limited so as not to exceed an upper limit amount. The solid-state image sensors of the second to fifth embodiments and the seventh and eighth embodiments of the present invention perform an operation (second upper limit amount limiting operation) in which the charges E accumulated by the photodiode PD are limited so as not to exceed the upper limit amount. The solid-state image sensor of the sixth embodiment of the present invention performs an operation (third upper limit amount limiting operation) in which the charges E accumulated by the memory area MEM are limited so as not to exceed an upper limit amount. Alternatively, a solid-state image sensor may be configured to be capable of simultaneously executing any combination of these operations.

(223) <<Electronic Information Device>>

(224) An example of the configuration of an electronic information device of an embodiment of the present invention which includes the solid-state image sensor 1, 1A, or 1B will be described with reference to FIG. 29. FIG. 29 is a block diagram illustrating an example of the configuration of the electronic information device of the embodiment of the present invention. An electronic information device 50 illustrated in FIG. 29 is not limited to an imaging device such as a digital steel camera or a digital video camera in which an imaging function using the solid-state image sensor 1, 1A, or 1B is a main function. The electronic information device 50 may be various devices such as a mobile phone, a tablet device, and a laptop computer in which an imaging function using the solid-state image sensor 1, 1A, or 1B is a secondary function.

(225) As illustrated in FIG. 29, the electronic information device 50 of the embodiment of the present invention includes an imaging unit 51 that is equivalent to the solid-state image sensor 1, 1A, or 1B; an optical system 52 that is formed of optical components (a lens, an aperture, and the like) which forms an optical image on the imaging unit 51; a data processing unit 53 that is formed of a digital signal processor (DSP) and the like which generates image data by performing various processes (for example, demosaicking) on data generated by the imaging unit 51; a frame memory 54 that stores data when the data processing unit 53 processes data; a display unit 55 that displays image data generated by the data processing unit 53, an image for operation, and the like; a recording unit 56 that records image data generated by the data processing unit 53 as necessary; an operation unit 57 that is formed of buttons, a touch panel, or the like which receives an operation from a user; a power supply unit 58 that supplies power to operate the electronic information device 50; a control unit 59 that controls the operation of the electronic information device 50; and a bus 60 through which the aforementioned units are connected to each other.

(226) A portion or the entirety of the control circuit 26 of the solid-state image sensor 1, 1A, or 1B may be a portion of the control unit 59 of the electronic information device 50. An offset correction process may not be performed by the imaging unit 51 (the offset correction processing circuit 28 of the solid-state image sensor 1, 1A, or 1B), but be formed by the data processing unit 53.

(227) The electronic information device 50 illustrated in FIG. 29 is merely an application example of the solid-state image sensor 1, 1A, or 1B. The solid-state image sensor 1, 1A, or 1B can be also applied to an electronic information device having a configuration different from that of the electronic information device 50.

SUMMARY

(228) The solid-state image sensors 1, 1A, or 1B of the embodiments of the present invention can be ascertained as follows.

(229) The solid-state image sensor 1, 1A, or 1B of the embodiments of the present invention includes multiple pixel circuit units P.sub.N and P.sub.OB, each including a photoelectric conversion unit PD that generates charges E via photoelectric conversion and accumulates the generated charges E, a floating diffusion unit FD that retains the charges E transferred from the photoelectric conversion unit PD, a transfer unit 11 through which the charges accumulated by the photoelectric conversion unit PD are transferred to the floating diffusion unit FD, an output unit 12 that outputs a signal corresponding to the amount of charges retained by the floating diffusion unit FD, and a reset unit 13 that discharges the charges E retained by the floating diffusion unit FD to the outside; and an A/D conversion unit 23 that acquires a signal output from the output unit 12, and performs A/D conversion on the acquired signal using a set gain. At least one of the pixel circuit units P.sub.N and P.sub.OB is configured such that the charges E transferred from the photoelectric conversion unit PD to the floating diffusion unit FD and retained by the floating diffusion unit FD are limited so as not to exceed an upper limit amount which is set to be smaller by the extent of an increase in the gain.

(230) In the solid-state image sensor 1, 1A, or 1B, it is possible to directly reduce a fluctuation in the output of the pixel circuits P.sub.N and P.sub.OB belonging to the same control group, which is a cause of pseudo-smear, by limiting the upper limit amount of the charges E which are transferred from the photoelectric conversion unit PD to the floating diffusion unit FD and are retained by the floating diffusion unit FD. As a result, it is possible to effectively reduce the occurrence of pseudo-smear by adopting a simple configuration and operation in which the upper limit amount of the charges E eventually retained in the floating diffusion unit FD is limited.

(231) In the solid-state image sensor 1, 1A, or 1B, the upper limit amount of the charges E eventually retained in the floating diffusion unit FD is further decreased to the extent corresponding to the condition in which pseudo-smear is likely to appear due to a high A/D conversion gain. As a result, it is possible to effectively reduce the occurrence of pseudo-smear as necessary.

(232) In the solid-state image sensor 1, 1A, or 1B, at least one of the pixel circuit units P.sub.N and P.sub.OB is configured to perform at least one of a first upper limit amount limiting operation in which the charges E retained by the floating diffusion unit FD are limited so as not to exceed the upper limit amount, and a second upper limit amount limiting operation in which the charges E accumulated by the photoelectric conversion unit PD are limited so as not to exceed the upper limit amount.

(233) In the solid-state image sensor 1, 1A, or 1B, it is possible to directly reduce a fluctuation in the output of the pixel circuits P.sub.N and P.sub.OB belonging to the same control group, which is a cause of pseudo-smear.

(234) The solid-state image sensor 1, 1A, or 1B further includes a charge retaining unit MEM that temporarily retains the charges E before being transferred from the photoelectric conversion unit PD to the floating diffusion unit FD. The transfer unit includes a first transfer unit 16 through which the charges E accumulated by the photoelectric conversion unit PD are transferred to the charge retaining unit MEM, and a second transfer unit 17 through which the charges E retained by the charge retaining unit MEM are transferred to the floating diffusion unit FD. At least one of the pixel circuit units P.sub.N and P.sub.OB is configured to perform at least one of a first upper limit amount limiting operation in which the charges E retained by the floating diffusion unit FD are limited so as not to exceed the upper limit amount, a second upper limit amount limiting operation in which the charges E accumulated by the photoelectric conversion unit PD are limited so as not to exceed the upper limit amount, and a third upper limit amount limiting operation in which charges retained by the charge retaining unit MEM are limited so as not to exceed the upper limit amount.

(235) In the solid-state image sensor 1, 1A, or 1B, it is possible to directly reduce a fluctuation in the output of the pixel circuits P.sub.N and P.sub.OB belonging to the same control group, which is a cause of pseudo-smear.

(236) In the solid-state image sensor 1, 1A, or 1B, at least one of the pixel circuit units P.sub.N and P.sub.OB is configured such that the second upper limit amount limiting operation is performed in such a way that the transfer unit 11 transfers the charges E exceeding the upper limit amount from the photoelectric conversion unit PD to the floating diffusion unit FD, and the reset unit 13 discharges charges which are transferred from the photoelectric conversion unit PD to the floating diffusion unit FD.

(237) Particularly, the solid-state image sensor 1, 1A, or 1B further includes an intermediate voltage generation unit 25 configured to generate intermediate voltages M.sub.11 and M.sub.12 of a magnitude between a first voltage H and a second voltage L in correspondence with the gain. In at least one of the pixel circuit units P.sub.N and P.sub.OB, the transfer unit 11 forms a control terminal 11 of a transistor which enters an ON mode if the first voltage H is applied thereto, and enters an OFF mode if the second voltage L is applied thereto, and when the second upper limit amount limiting operation is performed, the intermediate voltages M.sub.11 and M.sub.12 are applied to the transfer unit.

(238) In the solid-state image sensor 1, 1A, or 1B, it is possible to directly reduce a fluctuation in the output of the pixel circuits P.sub.N and P.sub.OB belonging to the same control group, which is a cause of pseudo-smear, by limiting the upper limit amount of the charges E accumulated in the photoelectric conversion unit PD.

(239) In the solid-state image sensor 1, 1A, or 1B, at least one of the pixel circuit units P.sub.N and P.sub.OB is configured such that the third upper limit amount limiting operation is performed in such a way that the second transfer unit 17 transfers the charges E exceeding the upper limit amount from the charge retaining unit MEM to the floating diffusion unit FD, and the reset unit 13 discharges the charges E which are transferred from the charge retaining unit MEM to the floating diffusion unit FD.

(240) Particularly, the solid-state image sensor 1, 1A, or 1B further includes an intermediate voltage generation unit 25 configured to generate intermediate voltages M.sub.31 and M.sub.32 of a magnitude between a first voltage H and a second voltage L in correspondence with the gain. In at least one of the pixel circuit units P.sub.N and P.sub.OB, the second transfer unit 17 forms a control terminal of a transistor which enters an ON mode if the first voltage H is applied thereto, and enters an OFF mode if the second voltage L is applied thereto, and when the third upper limit amount limiting operation is performed, the intermediate voltages M.sub.31 and M.sub.32 are applied to the second transfer unit 17.

(241) In the solid-state image sensor 1, 1A, or 1B, it is possible to directly reduce a fluctuation in the output of the pixel circuits P.sub.N and P.sub.OB belonging to the same control group, which is a cause of pseudo-smear, by limiting the upper limit amount of the charges E accumulated in the charge retaining unit MEM.

(242) In the solid-state image sensor 1, 1A, or 1B, at least one of the pixel circuit units P.sub.N and P.sub.OB is configured such that the first upper limit amount limiting operation is performed in such a way that the reset unit 13 discharges the charges E exceeding the upper limit amount from the floating diffusion unit FD, and the transfer unit 11 transfers the charges E accumulated by the photoelectric conversion unit PD to the floating diffusion unit FD.

(243) Particularly, the solid-state image sensor 1, 1A, or 1B further includes an intermediate voltage generation unit 25 configured to generate intermediate voltages M.sub.1, M.sub.2, M.sub.51, and M.sub.52 of a magnitude between a first voltage H and a second voltage L in correspondence with the gain. In at least one of the pixel circuit units P.sub.N and P.sub.OB, the reset unit 13 includes a transistor 13 which enters an ON mode if the first voltage H is applied to a control terminal of the transistor 13, and enters an OFF mode if the second voltage L is applied to the control terminal, and when the first upper limit amount limiting operation is performed, the intermediate voltages M.sub.1, M.sub.2, M.sub.51, and M.sub.52 are applied to the control terminal of the transistor of the reset unit 13.

(244) In the solid-state image sensor 1, 1A, or 1B, it is possible to directly reduce a fluctuation in the output of the pixel circuits P.sub.N and P.sub.OB belonging to the same control group, which is a cause of pseudo-smear, by limiting the upper limit amount of the charges E retained in the floating diffusion unit FD.

(245) In the solid-state image sensor 1, 1A, or 1B, at least one of the pixel circuit units P.sub.N and P.sub.OB is configured to include a discharge unit 15, which discharges the charges E accumulated by the photoelectric conversion unit PD to the outside, and the second upper limit amount limiting operation is performed in such a way that the discharge unit 15 discharges the charges E, which exceed the upper limit amount, from the photoelectric conversion unit PD.

(246) Particularly, the solid-state image sensor 1, 1A, or 1B further includes an intermediate voltage generation unit 25 configured to generate intermediate voltages M.sub.21, M.sub.22, M.sub.41, and M.sub.42 of a magnitude between a first voltage H and a second voltage L in correspondence with the gain. In at least one of the pixel circuit units P.sub.N and P.sub.OB the discharge unit 15 includes a transistor 15 which enters an ON mode if the first voltage H is applied to a control terminal of the transistor 15, and enters an OFF mode if the second voltage L is applied to the control terminal, and when the second upper limit amount limiting operation is performed, the intermediate voltages M.sub.21, M.sub.22, M.sub.41, and M.sub.42 are applied to the control terminal of the transistor 15.

(247) In the solid-state image sensor 1, 1A, or 1B, it is possible to directly reduce a fluctuation in the output of the pixel circuits P.sub.N and P.sub.OB belonging to the same control group, which is a cause of pseudo-smear, by limiting the upper limit amount of the charges E accumulated in the photoelectric conversion unit PD.

(248) In the solid-state image sensor 1, 1A, or 1B, all the transistors (the transistors 13 and 15, the transistor including the transfer gate 11 as a gate, and the transistor including the second transfer gate 17 as a gate) are configured such that the first voltage H, the intermediate voltages M.sub.1, M.sub.2, M.sub.11, M.sub.12, . . . M.sub.51, and M.sub.52 and the second voltage L are selectively applied to the control terminals (the gates of the transistors 13 and 15, the transfer gate 11, and the second transfer gate 17).

(249) In the solid-state image sensor 1, 1A, or 1B, the concentration of charges having a polarity opposite to that of charges accumulated in the photoelectric conversion unit PD can be increased particularly under the gate of the transistor (the gate of the transistor 15 or the transfer gate 11). Accordingly, charges generated due to dark current can be inhibited from flowing into the photoelectric conversion unit PD.

(250) The solid-state image sensor 1, 1A, or 1B further includes an offset correction processing unit 28 that performs an offset correction process on data obtained by performing A/D conversion on signal, which is output from a pixel circuit unit P.sub.N exposed to light, by the A/D conversion unit 23, based on data obtained by performing A/D conversion on a signal, which is output from a pixel circuit unit P.sub.OB shielded from light, by the A/D conversion unit 23.

(251) In the solid-state image sensor 1, 1A, or 1B, it is possible to further reduce or eliminate the pseudo-smear, which has been reduced by limiting the upper limit amount of charges transferred from the photoelectric conversion unit PD to the floating diffusion unit FD and retained by the floating diffusion unit FD, but which has remained, via an offset correction process.

(252) In the solid-state image sensor 1, 1A, or 1B, a period during which the second voltage L is applied to the control terminal of the transistor (the gates of the transistors 13 and 15, the transfer gate 11, or the second transfer gate 17) accounts for 90% or greater of a period that is the sum of the period during which the second voltage L is applied to the control terminal of the transistor (the gates of the transistors 13 and 15, the transfer gate 11, or the second transfer gate 17) and periods during which the intermediate voltages M.sub.1, M.sub.2, M.sub.11, M.sub.12, . . . M.sub.51, and M.sub.52 are applied to the control terminal of the transistor.

(253) In the solid-state image sensor 1, 1A, or 1B, dark current which increases due to the intermediate voltages M.sub.1, M.sub.2, M.sub.11, M.sub.22, . . . M.sub.52, and M.sub.52 being used instead of the second voltage L can be reduced to one tenth or less.

(254) In the solid-state image sensor 1, 1A, or 1B, the polarity of the second voltage L is different from that of the first voltage H.

(255) In the solid-state image sensor 1, 1A, or 1B, the concentration of charges having a polarity opposite to that of charges accumulated in the photodiode PD can be increased particularly under the gate of the transistor (the gate of the transistor 15 or the transfer gate 11). Accordingly, charges generated due to dark current can be inhibited from flowing into the photodiode PD.

(256) In the solid-state image sensor 1, 1A, or 1B, the intermediate voltage generation unit 25 generates the intermediate voltages M.sub.1, M.sub.2, M.sub.11, M.sub.12, . . . M.sub.51, and M.sub.52, which have a polarity different from that of the first voltage H, in correspondence with the magnitude of the gain.

(257) In the solid-state image sensor 1, 1A, or 1B, the concentration of charges having a polarity opposite to that of charges accumulated in the photodiode PD can be increased particularly under the gate of the transistor (the gate of the transistor 15 or the transfer gate 11). Accordingly, charges generated due to dark current can be inhibited from flowing into the photodiode PD.

(258) In the solid-state image sensor 1, 1A, or 1B, the upper limit amount is larger than or equal to the lower limit amount of the charges E at which data obtained via A/D conversion using the gain set by the A/D conversion unit 23 has the maximum value, and is smaller than or equal to 1.5 times the lower limit amount.

(259) In the solid-state image sensor 1, 1A, or 1B, A/D converted data is capable of having the maximum value, and it is possible to effectively reduce the occurrence of pseudo-smear.

(260) An electronic information device 50 of the present invention includes the solid-state image sensor 1, 1A, or 1B.

INDUSTRIAL APPLICABILITY

(261) The present invention can be applied to a solid-state image sensor which is represented by an amplified image sensor such as a CMOS image sensor, and to an electronic information device including the solid-state image sensor.

REFERENCE SIGNS LIST

(262) 1, 1A, 1B SOLID-STATE IMAGE SENSOR

(263) 10 PIXEL ARRAY

(264) 11 TRANSFER GATE (TRANSFER UNIT)

(265) 12 OUTPUT TRANSISTOR (OUTPUT UNIT)

(266) 13 RESET TRANSISTOR (RESET UNIT)

(267) 14 SELECTIVE TRANSISTOR

(268) 15 DISCHARGE TRANSISTOR (DISCHARGE UNIT)

(269) 15G GATE

(270) 15D DRAIN

(271) 16 FIRST TRANSFER GATE (FIRST TRANSFER UNIT)

(272) 17 SECOND TRANSFER GATE (SECOND TRANSFER UNIT)

(273) 21 VERTICAL SCAN CIRCUIT

(274) 22 PIXEL POWER SUPPLY REGULATOR

(275) 23 A/D CONVERSION CIRCUIT (A/D CONVERSION UNIT)

(276) 24 RAMP WAVE GENERATION CIRCUIT

(277) 25 INTERMEDIATE VOLTAGE GENERATION CIRCUIT (INTERMEDIATE VOLTAGE GENERATION UNIT)

(278) 26 CONTROL CIRCUIT

(279) 27 HORIZONTAL SCAN CIRCUIT

(280) 28 OFFSET CORRECTION PROCESSING CIRCUIT (OFFSET CORRECTION PROCESSING UNIT)

(281) 29 NEGATIVE VOLTAGE GENERATION CIRCUIT

(282) 50 ELECTRONIC INFORMATION DEVICE

(283) 51 IMAGING UNIT

(284) 52 OPTICAL SYSTEM

(285) 53 DATA PROCESSING UNIT

(286) 54 FRAME MEMORY

(287) 55 DISPLAY UNIT

(288) 56 RECORDING UNIT

(289) 57 OPERATION UNIT

(290) 58 POWER SUPPLY UNIT

(291) 59 CONTROL UNIT

(292) 60 BUS

(293) P.sub.N EFFECTIVE PIXEL CIRCUIT (PIXEL CIRCUIT UNIT)

(294) P.sub.OB OB PIXEL CIRCUIT (PIXEL CIRCUIT UNIT)

(295) PD PHOTODIODE (PHOTOELECTRIC CONVERSION UNIT)

(296) B EMBEDDED AREA

(297) FD FLOATING DIFFUSION AREA (FLOATING DIFFUSION UNIT)

(298) MEM MEMORY AREA (CHARGE RETAINING UNIT)

(299) TX TRANSFER CONTROL LINE

(300) TRX FIRST TRANSFER CONTROL LINE

(301) TRG SECOND TRANSFER CONTROL LINE

(302) RST RESET CONTROL LINE

(303) SEL SELECTION CONTROL LINE

(304) OFG DISCHARGE CONTROL LINE

(305) VR RESET POWER SUPPLY LINE

(306) VD COMMON POWER SUPPLY LINE

(307) VS SIGNAL OUTPUT LINE

(308) S SUBSTRATE

(309) W WELL

(310) X GATE INSULATING FILM

(311) H HIGH VOLTAGE (FIRST VOLTAGE)

(312) L LOW VOLTAGE (SECOND VOLTAGE)

(313) M.sub.1, M.sub.2, M.sub.11, M.sub.12, M.sub.21, M.sub.22 INTERMEDIATE VOLTAGE

(314) M.sub.31, M.sub.32, M.sub.41, M.sub.42, M.sub.51, M.sub.52 INTERMEDIATE VOLTAGE