Layered structure of a P-TFET

Abstract

A p-type Tunnel Field-Effect Transistor comprises a drain p-type semiconductor region, a source n-type semiconductor region, and at least one gate stack. The source n-type semiconductor region comprises a lowly doped section with a length of at least 10 nm and with a doping level of n-type dopant elements below 510.sup.18 at/cm.sup.3 and, in contact with the lowly doped section, a highly doped section with a length between 1 monolayer and 20 nm and with a doping level of n-type dopant elements above 510.sup.18 at/cm.sup.3.

Claims

1. A p-type tunnel field-effect transistor, comprising: a drain p-type semiconductor region; a source n-type semiconductor region comprising a lowly doped section and a highly doped section, wherein the lowly doped section has a length of at least 10 nm and a first n-type doping level of below 510.sup.18 at/cm.sup.3, wherein the highly doped section has a length of greater than 0 nm and up to 20 nm and has a second n-type doping level of above 510.sup.18 at/cm.sup.3, and wherein the lowly doped section is in contact with the highly doped section; a channel region between the drain p-type semiconductor region and the source n-type semiconductor region, the channel region comprising a channel portion and a layer of p-type doped semiconductor material, wherein the layer of p-type doped semiconductor layer has a length of greater than 0 nm and up to 20 nm and has a p-type doping level of above 510.sup.18 at/cm.sup.3, wherein the layer of p-type doped semiconductor material is in contact with the channel portion and is in contact with the highly doped section; and at least one gate electrode covering at least apart of the channel portion while avoiding a gate-drain overlapping and a gate-source overlapping, wherein an edge of the gate electrode is vertically aligned with a boundary between the source n-type semiconductor region and the channel region.

2. The p-type tunnel field-effect transistor of claim 1, wherein a junction between the lowly doped section and the highly doped section is a homojunction.

3. The p-type tunnel field-effect transistor of claim 1, further comprising a source contact, wherein the lowly doped section is located completely between the highly doped section and the source contact.

4. The p-type tunnel field-effect transistor of claim 1, wherein a junction between the source n-type semiconductor region and the channel region comprises a heterogeneous junction.

5. The p-type tunnel field-effect transistor of claim 1, wherein a junction between the source n-type semiconductor region and the channel region comprises a homogeneous junction.

6. The p-type tunnel field-effect transistor of claim 1, wherein the gate electrode comprises a double gate in contact with the channel region.

7. The p-type tunnel field-effect transistor of claim 1, wherein the gate electrode has a length equal to a length of the channel region.

8. The p-type tunnel field-effect transistor of claim 1, wherein the p-type tunnel field-effect transistor is a point tunneling field-effect transistor.

9. The p-type tunnel field-effect transistor of claim 1, wherein the gate electrode completely overlaps the layer of p-type doped semiconductor material.

10. The p-type tunnel field-effect transistor of claim 1, wherein the lowly doped section comprises at least 50% of the source n-type semiconductor region.

11. The p-type tunnel field-effect transistor of claim 1, wherein the lowly doped section comprises at least 70% of the source n-type semiconductor region.

12. The p-type tunnel field-effect transistor of claim 1, wherein the at least one gate electrode covers a complete length of the channel region.

13. A circuit, comprising: at least two complementary tunnel field-effect transistor devices, the at least two complementary tunnel field-effect transistor devices comprising an n-type tunnel field-effect transistor device and a p-type tunnel field-effect transistor device, wherein the p-type tunnel field-effect transistor comprises: a drain p-type semiconductor region; a source n-type semiconductor region comprising a lowly doped section and a highly doped section, wherein the lowly doped section has a length of at least 10 nm and a first n-type doping level of below 510.sup.18 at/cm.sup.3, wherein the highly doped section has a length of greater than 0 nm and up to 20 nm and has a second n-type doping level of above 510.sup.18 at/cm.sup.3, and wherein the lowly doped section is in contact with the highly doped section; a channel region between the drain p-type semiconductor region and the source n-type semiconductor region, the channel region comprising a channel portion and a layer of p-type doped semiconductor material, wherein the layer of p-type doped semiconductor material has a length of greater than 0 nm and up to 20 nm and has a p-type doping level of above 510.sup.18 at/cm.sup.3, wherein the layer of p-type doped semiconductor material is in contact with the channel portion and is in contact with the highly doped section; and at least one gate electrode covering at least a part of the channel portion while avoiding a gate-drain overlapping and a gate-source overlapping, wherein an edge of the gate electrode is vertically aligned with a boundary between the source n-type semiconductor region and the channel region.

14. The circuit of claim 13, wherein the n-type tunnel field-effect transistor device and the p-type tunnel field-effect transistor device are in a complementary metal oxide semiconductor inverter configuration.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic representation of a p-TFET with a channel, a p-type pocket and an n-type pocket in contact, near the tunneling region, according to particular embodiments.

(2) FIG. 2 shows a slight overlapping between the gate and the n-type pocket according to some embodiments.

(3) FIG. 3 shows a band diagram along the body center from source to drain, illustrative for the channel/source junction according to some embodiments.

(4) FIG. 4 shows simulations of the current vs. gate-source potential for a particular configuration according to embodiments, compared to an optimized known (prior art) TFET, and its shifted values for the same off-current.

(5) FIG. 5 schematically illustrates a particular embodiment according to a line TFET configuration.

(6) FIG. 6 schematically illustrates a transistor of which the source presents a doping profile with a gradient, according to particular embodiments.

(7) The drawings are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes.

(8) Any reference signs in the claims shall not be construed as limiting the scope.

(9) In the different drawings, the same reference signs refer to the same or analogous elements.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(10) The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention.

(11) The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

(12) Moreover, the terms top, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.

(13) It is to be noticed that the term comprising, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression a device comprising means A and B should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.

(14) Reference throughout this specification to one embodiment or an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases in one embodiment or in an embodiment in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

(15) Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

(16) Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

(17) In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

(18) When using the term tunneling field effect transistor (TFET) throughout the text, reference is made to a semiconductor device in which a gate controls a source-drain current through modulation of the so-called Band-To-Band Tunneling (BTBT). Band-to-band tunneling is a process in which electrons tunnel from the valence band through the semiconductor bandgap to the conduction band or vice versa.

(19) Where in embodiments reference is made to drain, source and gate, reference is made to the connections of the FET known in the art. The type of doping of the drain determines the type of TFET. In embodiments, the doped semiconductor corresponding to the drain has a p-type doping, hence reference will be made to a p-TFET.

(20) Drain and source are associated with a physical region, often comprising at least one type of semiconductor. In particular embodiments, the present description may make reference to a drain semiconductor region and a source semiconductor region. For sake of simplicity, the terms drain region and source region will be used throughout the description.

(21) Depending on the tunneling mechanism two types of TFETs may be distinguished: line TFET or point TFET. The tunneling mechanism of the line TFET device is dominated by so-called line tunneling which occurs inside the source region in a direction substantially orthogonal/perpendicular to the gate region, referred to as line tunneling. The tunneling mechanism of a point TFET device occurs partially inside the source region and partially inside the channel region in a direction substantially parallel to the gate region (45 degree or less), referred to as point tunneling.

(22) When using the term dielectric constant, reference is made to the so-called absolute dielectric constant (also often referred to as permittivity) which is measured in farads per meter (F/m). =r0 wherein r is the relative dielectric constant of a material and 0 is the vacuum dielectric constant; 0=8.854187817610.sup.12 F/m.

(23) While some embodiments described herein include examples of a double-gate TFET device, more specifically a TFET device comprising for example a source-channel-drain structure in the plane of a semiconductor substrate, e.g. a horizontal source-channel-drain structure, and a double gate electrode situated on the sidewalls of the channel region of the horizontal source-channel-drain structure, also other implementations of TFET devices may be applied in embodiments, such as for example a single-gate, a tri-gate TFET, an all-round gate TFET, a nanowire TFET, . . . . A tri-gate TFET comprises a source-channel-drain structure in the plane of a semiconductor substrate, e.g. a horizontal source-channel-drain structure, and a triple gate electrode comprising three gate electrode parts situated respectively on the sidewalls and on top of the channel region of the horizontal source-channel-drain structure. A gate all-around TFET comprises a horizontal or a vertical source-channel-drain structure, i.e. a source-channel-drain structure in the plane of a substrate or substantially perpendicular to the plane of the substrate, and an all-around gate electrode situated around, i.e. surrounding or encircling, the channel region of the horizontal or vertical source-channel-drain structure. A nanowire TFET comprises a nanowire which forms at least the channel region, and optionally the channel region and one or more of the source and drain regions, and an all-around gate electrode structure around, i.e. surrounding or encircling, the channel region of the nanowire TFET.

(24) Where in embodiments reference is made to a layer of n-type or p-type doped semiconductor material or to a n-type or p-type pocket, reference is made to subregions or limited zones comprised in or adjacent to the source region. Any of these subregions, or both, do not need to comprise the whole area of the device's cross section, but may do so. These subregions or doped layers comprise semiconductor material with high concentration of doping atoms, hence the layers are said to have high doping levels. A first layer, in contact with the lowly doped section of the source and having n-type doping, will be referred to as n-type pocket. An optional second layer, in contact with the highly doped section of the source and having p-type doping, will be referred to as p-type pocket.

(25) A first aspect of embodiments relates to a field-effect transistor, particularly to a p-TFET, comprising a drain region, a gate and a source region, although the transistor according to embodiments may present more parts.

(26) In embodiments, the parts of the transistor may comprise semiconductors, for example at least one element of group IV materials like C, Si, Ge, a binary or ternary compound from group III/V materials like GaAs, InGaAs, InP, InAs, GaSb or mixes thereof. The embodiments are not limited to these examples, and it may comprise elements of group III/V materials such as In, Ga, As, Sb, Al, P, B, N and binary, tertiary and quaternary compounds thereof; or group II/VI materials such as Cd, Zn, S, Se, Te, O and binary, tertiary and quaternary compounds thereof; or even carbon nanotubes. In advantageous embodiments, small-gap materials are used, for instance small bandgap III-V materials, such as for instance InGaAs, InAs, InSb, preferably with direct bandgap.

(27) A part of the transistor does not need to comprise the same elements as other parts, but may do so. For example, the source region, drain region and, if present, the channel may comprise the same composition (for instance all Si), with different types of doping in each of the parts. In particular embodiments, the drain region and the source region may comprise semiconductor materials which have opposite type of doping. In particular, the drain region may comprise a doped p-type semiconductor, and the source region may comprise a doped n-type semiconductor material.

(28) In some embodiments, the part of the transistor separating the source and drain regions may comprise a channel, which may comprise a semiconductor material with low doping level, for example but not limited thereto, a lightly doped n-type or p-type semiconductor, or an intrinsic semiconductor. For example, the doping levels may be lower than 510.sup.18 at/cm.sup.3, for example between 10.sup.10 at/cm.sup.3 (intrinsic doping) and 510.sup.18 at/cm.sup.3, preferably between 10.sup.15 at/cm.sup.3 and 10.sup.17 at/cm.sup.3, or lower than 10.sup.12 at/cm.sup.3, for instance about 10.sup.10 at/cm.sup.3. However, the presence of a channel is not an essential feature in every embodiment.

(29) In certain embodiments, the TFET channel separates the drain region from the source region. In some embodiments the drain region, gate and source region may further comprise contacts, for example ohmic contacts, degenerated semiconductor (n or p) contacts, contact electrodes formed by deposition, buried electrodes, and may be part of an integrated circuit. The embodiments are not limited by any particular type of contact.

(30) In embodiments, the drain region may comprise a p-type doped semiconductor. In particular embodiments, the doping level in the drain region may be low enough near the channel/drain interface to avoid ambipolar current. for example, the doping level of the drain region may be at least 10.sup.16 at/cm.sup.3 and at most 510.sup.20 at/cm.sup.3, for example between 510.sup.16 at/cm.sup.3 and 510.sup.18 at/cm.sup.3, for example 510.sup.17 at/cm.sup.3. In some embodiments, it may have a similar doping level as the source. The embodiments are not limited by these values, and the range may be different for particular applications.

(31) In some embodiments, the source region may comprise the same basic composition as the channel, for instance both source region and channel may comprise the same semiconductor material. The junction between source region and channel would be a homogeneous junction. The difference between source region and channel would lie in the doping level: the source region may have a higher doping level than the channel, for instance the source region may be doped and the channel may be an intrinsic semiconductor. A homogeneous junction presents several disadvantages over a heterogeneous junction. It may affect the characteristics of the TFET. For instance, the relation between the on-current and the off-current (the I.sub.ON/I.sub.OFF coefficient, which is closely related to the subthreshold swing) can be several orders of magnitude lower than for a TFET comprising a typical heterogeneous junction under the same conditions. This depends on the particular case and composition, but the lower I.sub.ON/I.sub.OFF is usually due to the requirement of a certain bandgap to obtain a low BTBT leakage (from source to drain e.g., or low ambipolar current). This bandgap may be too high to create sufficiently high on-currents. An advantage over heterostructure, which favors the performance of homogeneous junction devices, is the lower defect and dislocation density. However, the embodiments are not limited by any particular type of junction. For example, in some embodiments, source region and channel may comprise different semiconductor materials as basis materials, hence providing a heterogeneous junction at the tunneling region. Heterogeneous structures may present certain advantages, for example a bigger freedom of choice and tailoring of TFET characteristics. The materials may be chosen and, for instance, grown in order to reduce doping degeneracy, for instance by the use of a material with large bandgap for the source in combination with a relatively low doping level, while retaining a small effective bandgap at the tunnel junction, reducing tunnel distance and hence increasing the on-current.

(32) In embodiments, the source region comprises an n-type doped semiconductor with low doping level, for example lower than 510.sup.18 at/cm.sup.3, for example between 10.sup.16 and 510.sup.18 at/cm.sup.3. The doping concentration of the source is kept low, such that the electron Fermi level E.sub.FN does not move too deeply into the conduction band. The strong reduction in doping degeneracy prevents the SS degradation seen in p-TFETs with a heavily doped source. For example, in embodiments comprising a channel, the SS degradation is prevented because around the condition where tunneling is allowed (this is: when conduction band in the source aligns with valence band in the channel), the Fermi-Dirac distribution in the source is such, that empty positions are available for electrons to tunnel from the channel into the source (or equivalently, for holes to tunnel from the source into the channel).

(33) In accordance with embodiments, this low source doping is then combined with a highly-n-doped source pocket. The doping levels of the highly-n-doped source pocket are higher than 510.sup.18 at/cm.sup.3, preferably even not smaller than 210.sup.19 at/cm.sup.3. As the highly-n-doped source pocket has a large doping concentration, and as the highly-n-doped source pocket is depleted during the operation regime of the transistor, a large electric field builds up at the tunnel junction, which is stronger than it would be in the case with only a lowly doped source and no pocket. The stronger electric field hence enables a short tunnel path and hence a larger on-current.

(34) In certain embodiments, the junction between the channel and the source region comprises two layers comprising doped semiconductor materials, the doped layers having opposite doping types. The layer in contact with the source region is the highly-n-doped source pocket as disclosed above, hence having the same type of doping as the source region, but at higher doping level. The second layer (in between the highly-n-doped source pocket and the channel) is a highly-p-doped pocket which has opposite, p-type, doping. In embodiments, also this p-type doped layer has a high doping level. For instance, the doping level may be higher than 510.sup.18 at/cm.sup.3, preferably higher than 210.sup.19 at/cm.sup.3. Due to the additional presence of the highly-p-doped pocket, which is also partially depleted during device operation, a large electric field exists at the junction of the two pockets. The large field ensures efficient tunneling due to a short tunnel path and so an improved on-current.

(35) Ideally, the highly-n-doped source pocket or, if present, the highly-p-doped pocket, or each of them, may be a layer with thickness between 1 monolayer and 20 nm, for instance a layer with thickness between 1 nm and 5 nm. The width of the pocket may be smaller if the doping level is higher. The minimum size and doping levels of the pockets should be enough to be able to produce a strong electric field, but the pockets should not be as wide as to generate carriers at an energy below the conduction band edge energy in the lowly doped region of the source, e.g. far from the source channel interface in those embodiments in which a channel is present. These carriers would degrade the SS, which would return to similar disadvantageous values as a highly doped conventional source configuration. The source may typically be longer than the n-type pocket, as the lower doping requires a longer thickness to regain the equilibrium band alignment with respect to the Fermi level and return to a state of non-accumulation and non-depletion (hence to a state of a semiconductor in equilibrium). For example, in some embodiments the source may be longer than 5 nm, for example longer than 10 nm, for example between 10 nm and 100 nm, the embodiments not being limited to such range.

(36) In particular embodiments, the n-type pocket or n-type and p-type pockets completely cover the junction area between the source region and the channel. Hence, the lowly doped part of the source region is separated from the channel by the first (n-type) or by the first (n-type) and second (p-type) pockets. The embodiments are not limited thereto; for instance, the source region may be in direct contact with the channel, while limited zones of the junction comprise the one or two pockets, the n-type pocket being at least partially in contact with the source region. For example, in particular embodiments, the p-type pocket may be at least partially in contact with the channel.

(37) A tunnel field effect transistor (TFET) according to embodiments may further comprise a gate stack, the gate stack being in direct contact with the channel region. The gate stack may comprise a gate electrode and a gate dielectric, for instance an oxide, the gate dielectric being located between the gate electrode and the channel. The gate stack may be aligned with the channel region, or there may be an overlap or an underlap with the regions neighboring the channel region. In particular embodiments, the gate stack extends along at least one of the sides of the channel, between the drain and the source regions. For example, the gate stack may overlap most of the channel except for a small part of the channel next to the drain, avoiding a gate-drain overlapping (providing gate-drain underlap). This may reduce the ambipolar current through the drain. In particular embodiments, the gate stack may partially or completely overlap the p-type pocket or/and the n-type pocket in between the channel and the source region. In particular advantageous embodiments, the gate stack overlaps about 1 nm with the n-type pocket, but also embodiments where the gate stack stops up to 5 nm before the pocket-channel interface are acceptable. In particular embodiments, the gate stack may even overlap a few nm with the lowly doped source region. In some embodiments, the gate stack may extend along the channel and also slightly overlap the source region. In particular embodiments, the gate stack does not extend along the complete length of the channel.

(38) It is known that in p-type TFETs, high doping level in the source improves the effectiveness of the tunneling effect, hence keeping the on-current high. The negative effect of highly doped sources is the source degeneration: the Fermi level changes, and the difference between the Fermi level and the conduction band edge increases. Source degeneration produces subthreshold swing degradation in p-TFETs. One solution of this problem may be reducing the source doping, but this causes a drastic reduction of the on-current I.sub.ON. Embodiments present a compromise between low source doping (avoiding subthreshold swing degradation) and effective tunneling (avoiding on-current degradation). Some embodiments may comprise a source comprising low doping, improving subthreshold swing, without the disadvantage of a reduced I.sub.ON, due to the existence of the highly doped n-type and p-type pockets. These degenerate n- and p-type pockets are thin enough to have a minimal impact on the energetic distance between the Fermi level (determined by the external voltage applied) and the conduction band edge (determined by the doping levels), because the pockets will be nearly or fully depleted.

(39) The general operation principles of a transistor according to embodiments will now be described.

(40) In general, a TFET may comprise, according to embodiments, a drain comprising a p-type semiconductor material, a source comprising n-type semiconductor material in contact with a highly doped n-type semiconductor region, layer or section (highly doped n-type pocket), the n-type pocket situated in the region where tunneling is expected, and a gate. As a general outline, a voltage is applied to the TFET so the conduction band in the source changes and facilitates electron tunneling. Thanks to the low doping level of the source combined with the high doping level of the n-type pocket, the tunneling is effective due to the high electric field, and the degeneration is low, obtaining an improved SS. The interface between the n-type pocket and the source may be homogeneous (for instance, only differing in the level of doping, whereas the materials comprising both are the same), which facilitates manufacture.

(41) The tunneling can be further improved by adding a highly doped p-type pocket in contact with the n-type pocket. When the voltage is applied, due to reduction of the concentration of free carriers in the pockets, the electric field is improved.

(42) The basics of the embodiments may be applied to a diverse type of TFETs with different variations. For example, in case of TFETs with a channel separating the drain and the source, the source and the n-pocket may comprise a homogeneous junction, while the junction with the channel may be homogeneous or heterogeneous. The p-type pocket, if present, may be for example in the channel, or alternatively in the source, in contact with the n-type pocket. Hence, the embodiments may be easily implemented in standard manufacturing processes and circuit configurations, making integration in circuits straightforward.

(43) The general principles of operation of embodiments comprising a channel are explained as follows.

(44) When voltages are applied to the TFET, the band structure changes. In tunneling conditions, the conduction band in the source should align with the valence band in the channel. In a highly doped source region, there is a certain degeneration, and the distribution of carriers may impede effective tunneling of electrons from channel to source. On the other hand, due to the low source doping in case of embodiments, the Fermi-Dirac distribution still allows a large amount of empty positions in the source available for electrons immediately at onset, enhancing tunneling at the onset condition. A typical operation regime would result in partial depletion of the n-type and optionally p-type highly doped pockets, reducing the concentration of free carriers in the pockets. This depletion enhances electric field between the two pockets, and promotes tunneling at or near the junction between the channel and the source region. Additionally, the band energy suffers a limited potential dip due to the remaining carriers in the n-type pocket if not fully depleted. Due to the thin dimension of the pocket, the potential dip is narrow enough to allow quantized energy levels, such that even upon partial depletion, the carrier concentration at an energy below the conduction band far from the interface (carrier concentration in the potential dip) is very limited, preventing a re-establishment of the reduced SS associated with highly doped sources. The combination of these two factors (high doping of n- and optionally p-type pockets, and limited thickness) advantageously allows for a large on-current and steep SS.

(45) The doping level of the n-type and optional p-type pockets is very high (degenerate), so the electric field between the two pockets during operation is also very high and may promote tunneling precisely in the region where this may be needed (e.g. near the junction between source region and channel, in some embodiments. Despite the degeneration of the pocket layers, the size of the pocket is limited and the subthreshold swing is not affected as negatively as in known devices. This enables a fabrication of source regions with doping levels which may be lower than in other known p-TFET devices.

(46) Particular embodiments will now be described with reference to the figures.

(47) A basic p-TFET according to some embodiments is shown in the schematic drawing of FIG. 1. The TFET 100 comprises a p-type doped drain region 101, a channel 102 separating the drain region from an n-type doped source region 103, and a double gate 104 in contact with the channel, the gate 104 comprising a gate dielectric layer 105, which for example may comprise an electric isolator like an oxide layer, and a gate electrode 106. The embodiments are not limited by this configuration, for instance, the TFET may comprise a triple gate or a gate all around the channel. The source region 103 comprises a lowly n-doped section 109, and in contact therewith a highly n-doped section 111. In the particular embodiment shown in FIG. 1, both a highly-n-doped pocket 111 and a highly-p-doped pocket 112 are provided. Both the n-type pocket 111 and the p-type pocket 112 extend over the complete interface surface between source region and channel. The doping profile of the TFET illustrated would be, in this particular example, n n+p+i p. In the embodiment illustrated, a source contact 107 is provided in contact with the source region 103, and a drain contact 108 is provided in contact with the drain region 101. The embodiments are not limited by these examples, in particular it may be not limited by the presence of a p-type pocket or a channel.

(48) The cross-section of the transistor (the area formed by the Y direction and the Z direction, the Z direction being perpendicular to the drawing plane in FIG. 1) can have any suitable shape; for instance it can be squared, rectangular, circular, oval, or the like.

(49) The height of the device (Y-direction in FIG. 1) may for example be at least 3 nm, for instance between 3 nm and 1 m, e.g. between 3 nm and a few 100 nm such as e.g. 300 nm, preferably between 3 nm and 100 nm, for example 10 nm. The embodiments may not be limited by these exemplary values, for example it may reach 1 micrometer.

(50) The length of the drain region (X-direction in FIG. 1) may for example be at least 5 nm, for instance between 5 nm and 100 nm, for example 15 nm.

(51) The channel, if present, can have a length (X-direction in FIG. 1) of at least 1 nm, for instance between 1 nm and 100 nm, such as between 5 nm and 100 nm, for example 30 nm. In some embodiments, for example, the channel can have a length of 50 nm. The minimal length of the channel is determined by the type of material used.

(52) The lowly n-doped section 109 of the source region 103 can have a length (X-direction in FIG. 1) of at least 10 nm, for instance between 10 nm and 100 nm, for example 20 nm.

(53) In advantageous embodiments, the length (X-direction in FIG. 1) of the n-type pocket 111 or the p-type pocket 112, or each of them, may range from the thickness of one monolayer to lower than 20 nm, for example up to 5 nm. Both pockets, if present, may have the same length or a different length, depending on the particular application and the characteristics needed. In some embodiments, the lowly doped source may be longer than the n-type pocket.

(54) In the embodiment illustrated in FIG. 1, the gate electrode stack has a length (X-direction in FIG. 1) substantially equal to the length of the channel 102. In this embodiment, the gate electrode 106 and the gate dielectric 105 have a same length. This, however, is not limiting for the embodiments. In particular embodiments, the gate dielectric 105 may extend beyond the gate electrode 106. In particular embodiments, the length of the gate electrode 106 may be between 5 nm and 100 nm, for example 22 nm. In alternative embodiments the gate electrode 106 may have a length smaller or larger than the length of the channel 102. This means that the gate electrode 106 does not need to cover the complete length of the channel 102, but may do so and may even cover more than the length of the channel 102. The gate electrode 106 may also cover other parts of the transistor, for instance it may overlap with one or more (if present) of the pockets 111, 112, or even with the lowly doped section 109 of the source region 103, and this both in cases where it covers or does not cover the complete length of the channel 102. In one direction, the gate electrode 106 may extend up to the drainchannel interface, or up to a distance from the drainchannel interface in the direction of the channel. In the other direction, the gate electrode 106 extends at least up to a distance not more than 5 nm from the pocketchannel interface, but in embodiments it may extend up to the pocketchannel interface, beyond the pocketchannel interface, or even up to a few nm beyond the pocketsource region interface. In some embodiments, depending for example on manufacturing process, or depending on particular applications, it may be advantageous not to have an overlap between the gate electrode 106 and the n-type pocket 111. For example, in certain embodiments the gate electrode 106 may overlap the p-type pocket completely, but the edge of the gate electrode 106 may be situated at the level of the interface between the p-type pocket and the n-type pocket, not overlapping the n-type pocket.

(55) In other embodiments, as illustrated in FIG. 2, the gate electrode 106 (in the embodiment illustrated the gate stack 104) may slightly overlap the n-type pocket. The detail of the junction 200 shows that the gate electrode 106 may partially or completely overlap the channel 102, and the edge of the gate electrode 106 may be situated at a certain distance of the p-type pocket 112, completely overlapping said layer, but only partially overlapping the n-type pocket 111. The optimal overlapping depends on the relative thickness of the pockets and the body. In the embodiments with dimensions shown in the Table I, the gate electrode may extend about 1 nm over the n-type pocket.

(56) Band structure simulations have been performed using the architecture of FIG. 2, using a homogeneous pocket length of 10 nm and the values of doping levels and region lengths enumerated in Table I. The embodiments are not limited by the thickness of the device, which may be chosen according to the material to obtain an optimal confinement, for example confined down to a distance in which the optimal I.sub.ON/I.sub.OFF ratio is achieved.

(57) TABLE-US-00001 TABLE I Simulated configuration details N.sub.SOURCE [at/cm.sup.3] .sup.10.sup.18 N.sub.CHANNEL [at/cm.sup.3] .sup.10.sup.10 P.sub.DRAIN [at/cm.sup.3] 5 10.sup.17 N.sub.POCKET [at/cm.sup.3] 5 10.sup.19 P.sub.POCKET [at/cm.sup.3] 5 10.sup.19 L.sub.SOURCE [nm] 20 L.sub.CHANNEL [nm] 50 L.sub.DRAIN [nm] 15 L.sub.GATE [nm] 22 L.sub.GN [nm] 1 EOT [nm] 0.6 WF [eV] 5

(58) For this particular simulation, the drain, source and channel comprise InGaAs. The channel is slightly doped with n-type doping, with similar behavior as an intrinsic semiconductor. Also the type and level of doping (N or P) in each of the regions is indicated in the Table I. The length of each region is indicated, as well as the overlap L.sub.GN between the gate electrode 106 and the n-type pocket (which corresponds to the embodiment of FIG. 2). EOT means Equivalent Oxide Thickness of the gate dielectric 105 and WF represents the Work Function.

(59) The results of the simulated band structure can be seen in FIG. 3. The gate-source and drain-source voltages are 0.3 V and 0.5 V respectively. There is a potential dip 301 due to the existence of the highly doped, but relatively thin (few nm), n-type and p-type pockets 111, 112 between the lowly doped section 109 of the source region 103 and the channel 102. This potential dip 301 is narrow, so the available levels are quantized, hence advantageously retaining a low carrier concentration in the n-type pocket.

(60) Tunneling of holes follow the arrow from the conduction band in the lowly doped section 109 of the source region 103 to valence band of the channel 102.

(61) It can also be seen in FIG. 3 that the difference between the conduction band edge E.sub.C and the Fermi level E.sub.FN is approximately 100 meV for the values of Table I and the applied voltages of gate-source and drain-source voltages are 0.3 V and 0.5 V, respectively. If the doping level of the source was 510.sup.19 at/cm.sup.3 instead of 10.sup.18 at/cm.sup.3, this difference would have been about 500 meV, degrading subthreshold swing. This is an example of the advantage of a source with low doping levels in accordance with embodiments.

(62) The simulations also provide substantial information regarding the on-current and the subthreshold swing for a TFET with the configuration of FIG. 2, for different sizes of the layers and for an on-current defined according to an off-current of 1 nA/m (one nano-ampere per micrometer) and a supply voltage of 0.5 V. The results of a) the on-current (I.sub.ON) and b) the largest current for which the subthreshold swing is lower than 60 mV/dec (I.sub.60) are shown in Table II, and the last row provides with comparison with an existing TFET with the same p-pocket doping level as the examples.

(63) The obtained results take into account a size of 5 nm for the n-type pocket and sizes of 3 and 4 nm for the p-type pocket. These I.sub.ON values are, not only comparable with optimized TFETs known in the art, but the existing and large I.sub.60 also indicates an improvement of the on-current for smaller supply voltages over existing TFETs (last row table), for which the I.sub.60 current is typically negligible or non-existing, (hence SS is higher than 60 mV/dec for the TFET known in the art).

(64) TABLE-US-00002 TABLE II Comparison of I.sub.ON and I.sub.60 Configuration/L.sub.SOURCE/L.sub.N/L.sub.P I.sub.ON [A/m] I.sub.60 [A/m] n n+ p+ i p/10 nm/5 nm/ 4 nm 75 5 n n+ p+ i p/10 nm/5 nm/3 nm 60 2 n+ p+ i p/10 nm/0 nm/3 nm 75

(65) The input characteristics are plotted in FIG. 4 as a function of the gate-source voltage (I.sub.DS vs V.sub.GS). The graphs in part (a) of FIG. 4 show the simulated unshifted I-V currents 401 for an optimized known TFET (last entry in Table II), compared to two TFETs according to embodiments, with features an in Table I and FIG. 1 with an n-type pocket size of 5 nm, one plot 402 corresponding to a TFET having a p-type pocket of 4 nm, and another plot 403 corresponding to a TFET having a p-type pocket of 3 nm. The graphs in part (b) of FIG. 4 are the same as the graphs in part (a), with shifted voltage characteristics such that an off-current of 1 nA/m is obtained at the same voltage for the three cases. Analogously as in the unshifted graphs, the shifted graphs show a comparison between the plots 411 for the optimized prior art TFET and two TFETs according to embodiments, one plot 412 corresponding to a TFET having a p-type pocket of 4 nm, and another plot 413 corresponding to a TFET having a p-type pocket of 3 nm. The subthreshold swing is improved in the two cases according to embodiments. The marks 414, 415 in the plots 412, 413 correspond to the values of I.sub.60 shown in Table II (these values are only existing in the TFETs according to embodiments).

(66) The graphs show that a preferred choice of p-type pocket size would be 4 nm, for the configuration of FIG. 1 with an n-type pocket size of 5 nm.

(67) As it can be seen from the simulations, the embodiments may advantageously provide a p-TFET with a large on-current, comparable to that of previously known TFETs (TFETs with heavily doped source), in addition to avoiding the deterioration of subthreshold swing caused by large doping degeneracy.

(68) Despite the simulations relate to embodiments shown in previous drawings, the embodiments may also be applied to other transistor configurations.

(69) FIG. 5 is a schematic illustration of a TFET 500 according to embodiments following a line TFET configuration. The line TFET configuration increases the electric field near the junction, facilitating the tunneling event from the conduction band to the valence band. The presence of a p-type pocket also reduces field-induced quantum confinement.

(70) As before, a drain region 101, possibly with a drain contact (not illustrated in FIG. 5), is in contact with a channel 502, but in this case the n-type pocket 511 and p-type pocket 512 do not occupy the complete area in which the channel 502 and the lowly doped section 509 of the source region 503 may be in direct contact. This is different from the embodiment of FIG. 1, where there was no direct contact between the lowly doped section 109 of the source region 103 and the channel 102, as both pockets 111, 112 occupied the whole area between them. In both the embodiments of FIG. 1 and FIG. 5, the tunneling takes place partially inside the n-type pocket 511, and the dominant electric field is mainly perpendicular to the pocket layers, but this configuration does not limit the embodiments, and other configurations may show different behaviors.

(71) While the dominant electric field could be defined in FIG. 1 as parallel to the gate 104 (the gate being perpendicular to the n-type and p-type pockets 111, 112), in the configuration of FIG. 5, the electric field can be defined as perpendicular to the gate 504 (and the pockets 511, 512 parallel to the gate 504). The tunneling effect may be described as being orthogonal to the gate 504. In some embodiments following the line TFET configuration, the lowly doped section 509 of the source region 503 may present a low doping level, not higher than 510.sup.18 at/cm.sup.3, and the junction with the channel 502 comprises at least one pocket layer comprising a highly doped semiconductor material.

(72) The gate electrode 506 may extend over the n-type and optionally present p-type pockets, and it may extend over at least part of the channel 502, up to the drain region 101, which may also be overlapped, or may advantageously not be overlapped. In alternative embodiments, the gate electrode 506 may not overlap the channel 502, extending over only at least part of the n-type pocket 511 and, if present, the p-type pocket 512. In the particular configuration illustrated in FIG. 5, the gate electrode 506 extends (X-direction in FIG. 5) along a portion of the channel 502. The length (in the X-direction in FIG. 5) of the pockets 511, 512 may extend over a substantial length (in the X-direction in FIG. 5) of the source region 503, for example about 5 nm, or for example about 10 nm. In certain embodiments, the pockets may not extend completely up to the source contact, but they may extend over a substantial part thereof, for instance at least 90% of the total length of the source, or even more, for example at least 95% thereof. The height (in the Y-direction in FIG. 5) of the pockets 511, 512 may be, as before, less than 20 nm, for example it may be about 5 nm (measured from the gate towards the center of the device). The p-type pocket 512 may be partially embedded within the n-type pocket 511, but other configurations are possible. The p-type pocket 512 may be smaller than 20 nm, for example 5 nm or less. The p-type pocket 512 is in contact with the gate stack 504, with the n-type pocket 511, and over a small surface with the channel 502. The n-type pocket 511 is in contact with the lowly doped section 509 of the source 503, the p-type pocket 512, and over a small surface with the channel 502 and optionally with the gate 504. The n-type pocket 511 can be at least partially, or even completely, as shown in the FIG. 5, overlapped by the gate 504.

(73) In particular embodiments, the doping profile of the source and drain regions can be advantageously manipulated according to each particular application. For example, the source region may comprise a highly doped (e.g. degenerated) zone with the functionality of a contact, hence effectively creating a n+ n n+ p+ i p doping profile.

(74) In particular embodiments, schematically illustrated in FIG. 6, a TFET 600 comprises a source 603 which may be prepared so the doping level increases across its length towards the channel 102. At the point in which the source region 603 is in contact with the p-type pocket 112, the source region 603 has a high doping level, higher than 510.sup.18 at/cm.sup.3, creating effectively a highly-doped n-type pocket 611. Alternatively, in those embodiments in which the p-type pocket or channel is not present, the source region has a high doping level in the in zone in which the tunneling effect is expected. The increment of doping level across the length of the source region 603, indicated by the hatched line 620, may be linear, or in advantageous embodiments, exponential, asymptotic or may have any other profile which may keep a low doping level, below 510.sup.18 at/cm.sup.3, in a lowly doped section 609, wherein the lowly doped section 609 corresponds to most of the source region 603, for instance in at least 50% of the source region, or at least 70% of the source region (these exemplary values not limiting the embodiments), while having a high doping level, e.g. higher than 510.sup.18 at/cm.sup.3, in the zone 611 closer to the channel 102 where tunneling is expected. The scale 621 relates to the hatched lines 622, 620 in drain region 101 and source region 603, respectively, and indicates the doping levels in these regions, either p or n doping. The source region 603 has n-type doping, and the drain region 101 has p-type doping.

(75) Additionally, in some embodiments, for instance illustrated in the embodiment of FIG. 6, but not limited thereto, the source region 603 may comprise a highly doped area 604 with the functionality of a contact, as explained before. This is optional and not limiting to the embodiments.

(76) The embodiments are not limited by any particular configuration shown in these particular examples and embodiments, and it can be applied to other transistor configurations like raised-buried oxide TFETs, gate-all-around TFETs, single or multi-gate TFETs, FinFETs, horizontal or vertical TFETs, etc. The cross section may be cylindrical, planar, oblong, etc.

(77) Another aspect of embodiments relates to a circuit which may comprise at least two transistors, at least one of them being a p-TFET according to embodiments of the first aspect of the embodiments. In particular embodiments, the circuit may be an integrated circuit, for example comprising the architecture of a CMOS design, with applications in logic, although the embodiments are not limited thereby, and the embodiments can be equally applied to memory devices, like 3T or 4T memories. It is an advantage of the CMOS design according to embodiments that the transistors show good complementarity, as the p-TFET according to embodiments may present characteristics (for example, subthreshold swing and on-current) similar to those found in n-TFETs. Thus, integrated circuits with CMOS structure based on MOSFET technology can be substituted by TFET, which shows lower subthreshold swing SS than the limited MOSFET SS. Because of improved complementarity, CMOS circuits comprising p-TFETs according to embodiments would use less power and show less leakage current and higher on-current than existing TFET-based CMOS circuits. Existing CMOS processes can advantageously be used for complementary TFET circuit manufacture, making technology transfer easy.

(78) All references cited herein are incorporated herein by reference in their entirety. To the extent publications and patents or patent applications incorporated by reference contradict the disclosure contained in the specification, the specification is intended to supersede and/or take precedence over any such contradictory material.

(79) Unless otherwise defined, all terms (including technical and scientific terms) are to be given their ordinary and customary meaning to a person of ordinary skill in the art, and are not to be limited to a special or customized meaning unless expressly so defined herein. It should be noted that the use of particular terminology when describing certain features or aspects of the disclosure should not be taken to imply that the terminology is being re-defined herein to be restricted to include any specific characteristics of the features or aspects of the disclosure with which that terminology is associated. Terms and phrases used in this application, and variations thereof, especially in the appended claims, unless otherwise expressly stated, should be construed as open ended as opposed to limiting. As examples of the foregoing, the term including should be read to mean including, without limitation, including but not limited to, or the like; the term comprising as used herein is synonymous with including, containing, or characterized by, and is inclusive or open-ended and does not exclude additional, unrecited elements or method steps; the term having should be interpreted as having at least; the term includes should be interpreted as includes but is not limited to; the term example is used to provide exemplary instances of the item in discussion, not an exhaustive or limiting list thereof; adjectives such as known, normal, standard, and terms of similar meaning should not be construed as limiting the item described to a given time period or to an item available as of a given time, but instead should be read to encompass known, normal, or standard technologies that may be available or known now or at any time in the future; and use of terms like preferably, preferred, desired, or desirable, and words of similar meaning should not be understood as implying that certain features are critical, essential, or even important to the structure or function of the invention, but instead as merely intended to highlight alternative or additional features that may or may not be utilized in a particular embodiment of the invention. Likewise, a group of items linked with the conjunction and should not be read as requiring that each and every one of those items be present in the grouping, but rather should be read as and/or unless expressly stated otherwise. Similarly, a group of items linked with the conjunction or should not be read as requiring mutual exclusivity among that group, but rather should be read as and/or unless expressly stated otherwise.

(80) Where a range of values is provided, it is understood that the upper and lower limit, and each intervening value between the upper and lower limit of the range is encompassed within the embodiments.

(81) With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity. The indefinite article a or an does not exclude a plurality.

(82) All numbers expressing dimensions, amounts, and so forth used in the specification are to be understood as being modified in all instances by the term about. Accordingly, unless indicated to the contrary, the numerical parameters set forth herein are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, and not as an attempt to limit the application of the doctrine of equivalents to the scope of any claims in any application claiming priority to the present application, each numerical parameter should be construed in light of the number of significant digits and ordinary rounding approaches.

(83) Furthermore, although the foregoing has been described in some detail by way of illustrations and examples for purposes of clarity and understanding, it is apparent to those skilled in the art that certain changes and modifications may be practiced. Therefore, the description and examples should not be construed as limiting the scope of the invention to the specific embodiments and examples described herein, but rather to also cover all modification and alternatives coming with the true scope and spirit of the invention.