OPTICAL SENSOR DEVICE AND VOLTAGE REGULATOR APPARATUS WITH IMPROVED NOISE REJECTION CAPABILITY

Abstract

A voltage regulator apparatus with a rejection capability for high frequency power noise includes a low dropout linear regulator and a noise rejection circuit. The low dropout linear regulator has at least one operational amplifier which is powered by a power source, and the low dropout linear regulator is configured for receiving and regulating an input voltage signal to provide an output voltage signal for a load. The noise rejection circuit is coupled between the power source and the low dropout linear regulator, and is configured for providing a power noise rejection capability upon a high frequency part of a power signal of the power source to generate the power signal with less high frequency noise to the at least one operational amplifier.

Claims

1. A voltage regulator apparatus with a rejection capability for high frequency power noise, comprising: a low dropout linear regulator having at least one operational amplifier which is powered by a power source, the low dropout linear regulator being configured for receiving and regulating an input voltage signal to provide an output voltage signal for a load; and a noise rejection circuit, coupled between the power source and the low dropout linear regulator, configured for providing a power noise rejection capability upon a high frequency part of a power signal of the power source to generate the power signal with less high frequency noise to the at least one operational amplifier; wherein the noise rejection circuit comprises: a transistor used as a noise rejection element, having a first terminal connected to the power source, a second terminal connected to a power input of the at least one operational amplifier, and a control terminal connected to a voltage bias signal; a resistor, having a first terminal connected to the power source and a second terminal connected to the control terminal of the transistor; and a capacitor, having a first terminal connected to the control terminal of the transistor and a second terminal connected to a ground level; wherein the voltage bias signal is generated from an intermediate node between the resistor and the capacitor.

2-7. (canceled)

8. The voltage regulator of claim 1, wherein the transistor is a MOS transistor with a low voltage threshold.

9. An optical sensor device comprising the voltage regulator apparatus of claim 1.

10. A voltage regulator apparatus with a rejection capability for high frequency power noise, comprising: a low dropout linear regulator having at least one operational amplifier which is powered by a power source, the low dropout linear regulator being configured for receiving and regulating an input voltage signal to provide an output voltage signal for a load; and a noise rejection circuit, coupled between the power source and the low dropout linear regulator, configured for providing a power noise rejection capability upon a high frequency part of a power signal of the power source to generate the power signal with less high frequency noise to the at least one operational amplifier; wherein the noise rejection circuit comprises: a transistor used as a noise rejection element, having a first terminal connected to the power source, a second terminal connected to a power input of the at least one operational amplifier, and a control terminal connected to a voltage bias signal; and a bias circuit, coupled to the control terminal of the transistor, configured for providing the voltage bias signal to the control terminal of the transistor, the bias circuit being powered by the power signal and the voltage bias signal generated from the bias circuit being irrelevant to the input voltage signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a diagram of an optical sensor device according to an embodiment of the invention.

[0009] FIG. 2 is a diagram illustrating an example of optical sensor device as shown in FIG. 1.

[0010] FIG. 3 is a diagram showing a simplified example of the power supply rejection ratio (PSRR) frequency response of low dropout linear regulator as shown in FIG. 2.

[0011] FIG. 4 is a diagram showing a simplified example of the PSRR frequency response of noise rejection circuit as shown in FIG. 2.

[0012] FIG. 5 is a diagram showing a simplified example of the PSRR frequency response of voltage regulator apparatus of FIG. 2.

[0013] FIG. 6 is a diagram illustrating another example of optical sensor device as shown in FIG. 1.

[0014] FIG. 7 is a diagram showing a simplified example of the PSRR frequency response of noise rejection circuit as shown in FIG. 6.

[0015] FIG. 8 is a diagram showing a simplified example of the PSRR frequency response of voltage regulator apparatus of FIG. 6.

DETAILED DESCRIPTION

[0016] Refer to FIG. 1, which is a diagram of an optical sensor device 100 according to an embodiment of the invention. The optical sensor device 100 such as an image sensor device comprises a voltage regulator apparatus 105. The voltage regulator apparatus 105 has a noise/ripple rejection capability for decreasing or avoiding/rejecting power noise/ripple such as high frequency power noise. The voltage regulator apparatus 105 comprises a linear regulator such as a low dropout linear regulator 110 and a noise rejection circuit 115. The voltage regulator apparatus 105 employs the low dropout linear regulator 110 to receive and regulate an input voltage signal VIN to generate/provide an output voltage signal VOUT for a load 125. The power of low dropout linear regulator 110 is provided by the power source 120 through the noise rejection circuit 115, and the noise rejection circuit 115 is arranged to avoid or reject power noise from the power source 120, e.g. high frequency power noise, affecting the signal, operation, and/or performance of the low dropout linear regulator 110,

[0017] In this embodiment, the low dropout linear regulator 110 has at least one operational amplifier (but not limited) which is powered by a power source 120. For example, in the embodiment, the low dropout linear regulator 110 has an operational amplifier OP1 having an input for receiving and regulating the input voltage signal VIN to generate/provide the output voltage signal VOUT for the load 125 which is connected between the output of operational amplifier OP1 and the ground level. The operational amplifier OP1 is powered by the power source 120. The performance of operational amplifier OP1 is easily affected by power noise such as high frequency power noise. Thus, the noise rejection circuit 115 is arranged to be placed/configured between the power source 120 and low dropout linear regulator 110, to reject or avoid the high frequency power noise from power source 120 so as to avoid the performance of low dropout linear regulator 110 be affected by the high frequency power noise.

[0018] Specifically, in practice, the noise rejection circuit 115 comprises a transistor 115A and a bias circuit 115B wherein the transistor 115A is used as a noise rejection element which is placed/configured between the power source 120 and low dropout linear regulator 110. The bias circuit 115B is used for generating and providing a bias signal such as a voltage bias signal VB to the control terminal of transistor 115A to maintain conductance of transistor 115A so as to provide noise rejection capability. The transistor 115A such as an MOS transistor (e.g. NMOS transistor) with a regular voltage threshold (RVT), a low voltage threshold (LVT) or a zero voltage threshold has a first terminal connected to power source 120, a second terminal connected to a power input of the operational amplifier OP1, and the control terminal such as the gate connected to the voltage bias signal VB. The bias circuit 115B in an example is arranged to provide a band gap reference voltage to the gate of transistor 115A. In other examples, the bias circuit 110B may be implemented by using an R-C filter. These modifications all fall within the scope of the invention.

[0019] The bias circuit 115B can be implemented using a set of resistor and capacitor. FIG. 2 is a diagram illustrating an example of optical sensor device 100 as shown in FIG. 1. The bias circuit 115B comprises a resistor R1 and capacitor C1. A first terminal of resistor R1 is connected to the power source and a second terminal of resistor R1 is connected to an intermediate terminal N1 of bias circuit 115B. The first terminal of capacitor C1 is connected to the intermediate terminal N1, and the second terminal of capacitor C1 is connected to the ground level. The intermediate terminal N1 is connected to the control terminal of transistor 115A, and the voltage bias signal VB is generated at the intermediate terminal N1 and provided for the gate of NMOS transistor 115A.

[0020] Refer to FIG. 3 in conjunction with FIG. 4 and FIG. 5. FIG. 3 is a diagram showing a simplified example of the power supply rejection ratio (PSRR) frequency response of low dropout linear regulator 110 as shown in FIG. 2. FIG. 4 is a diagram showing a simplified example of the PSRR frequency response of noise rejection circuit 115 as shown in FIG. 2. FIG. 5 is a diagram showing a simplified example of the PSRR frequency response of voltage regulator apparatus 105 of FIG. 2. The PSRR value is used to describe the capability of an electronic circuit to suppress any power supply variations to its output signal. As shown in the example of FIG. 3, the low dropout linear regulator 110 has the comparatively large negative PSRR (e.g. 60 dB) at lower frequency e, g. 0-1 KHz. The low dropout linear regulator 110 has comparatively small negative PSRR at higher frequency. The low dropout linear regulator 110 has a better noise rejection capability for power noise at a specific frequency if the negative PSRR value at the specific frequency is larger. In addition, the PSRR at 1 GHz above becomes zero. This indicates that the low dropout linear regulator 110 does not have the noise rejection capability for power noise at the frequency above 1 GHz.

[0021] As shown the example of in FIG. 4, the noise rejection circuit 115 is employed. The noise rejection circuit 115 has a comparatively small negative PSRR (e.g. 0 dB-40 dB) at lower frequency such as 0-1 KHz. For the power nose at higher frequency such as above 1 KHz, the noise rejection circuit 115 has and provides 40 dB rejection capability. Thus, as shown in FIG. 5, the improved PSRR frequency response of voltage regulator apparatus 105 shows that the using the noise rejection circuit 115 can further provide 40 dB rejection capability for the higher frequency such as 1 KHz-1 GHz. For example, for the frequency at 1 KHz, the voltage regulator apparatus 105 provides 100 dB noise rejection capability.

[0022] Further, in another embodiment, the bias circuit 115B can be implemented using a set of resistor, capacitor, and a current source circuit. FIG. 6 is a diagram illustrating another example of optical sensor device 100 as shown in FIG. 1. The bias circuit 115B comprises resistor R1, capacitor C1, and a current source circuit I1. The current source circuit I1 such as a reference current source or band-gap current source has a terminal connected to the power source 120 and another terminal connected to the intermediate terminal of bias circuit 115B, and is used for providing a specific reference current. The resistor R1 and capacitor C1 are connected in parallel. The first terminal of resistor R1 is connected to the intermediate terminal N1 of bias circuit 115B and the second terminal of resistor R1 is connected to the ground level. Also, the first terminal of capacitor C1 is connected to the intermediate terminal N1 of bias circuit 115B and the second terminal of capacitor C1 is connected to the ground level. The intermediate terminal N1 is connected to the control terminal (i.e. gate) of transistor 115A. The voltage bias signal VB is generated at the intermediate terminal N1 and provided for the gate of NMOS transistor 115A.

[0023] Refer to FIG. 3 again and in conjunction with FIG. 7 and FIG. 8. FIG. 7 is a diagram showing a simplified example of the PSRR frequency response of noise rejection circuit 115 as shown in FIG. 6. FIG. 8 is a diagram showing a simplified example of the PSRR frequency response of voltage regulator apparatus 105 of FIG. 6. As shown in the example of FIG. 3, the low dropout linear regulator 110 has the comparatively large negative PSRR (e.g. 60 dB) at lower frequency e, g. 0-1 KHz. The low dropout linear regulator 110 has comparatively small negative PSRR at higher frequency. The low dropout linear regulator 110 has a better noise rejection capability for power noise at a specific frequency if the negative PSRR value at the specific frequency is larger. In addition, the PSRR at 1 GHz above becomes zero. This indicates that the low dropout linear regulator 110 does not have the noise rejection capability for power noise at the frequency above 1 GHz. As shown the example of in FIG. 7, the PSRR of the noise rejection circuit 115 is 40 dB for any frequency. That is, the noise rejection circuit 115 of FIG. 6 provides 40 dB noise rejection capability for any frequency. Thus, as shown in FIG. 8, the improved PSRR frequency response of voltage regulator apparatus 105 shows that the using the noise rejection circuit 115 can provide 100 dB rejection capability for the lower frequency from zero to 1 KHz and at least greater than 40 dB rejection capability for the frequency from 1 KHz to 1 GHz. Also, the noise rejection circuit 115 can provide 40 dB noise rejection capability for the frequency higher than 1 GHz.

[0024] Compared to the conventional schemes which are limited due to the operation of operational amplifier, the above embodiments can provide better power noise rejection capability for the higher frequency such as frequency from 1 KHz to 1 GHz. Particularly, for an optical sensor device/application such an image sensor device implemented with such power noise rejection capability, the quality of generated/sensed images will not be degraded.

[0025] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.