Abstract
A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.
Claims
1. A method of forming a transient voltage suppressing (TVS) device comprising: forming an epitaxial layer of a first conductivity type on top of a semiconductor substrate wherein the semiconductor substrate comprises a heavily doped bottom layer of the first conductivity type; forming a trench gate padded with a gate insulation layer and filled with a gate material in the trench gate in the epitaxial layer; forming a body region with a second conductivity type in the epitaxial layer next to the trench gate and forming a drain contact region and an epitaxial contact region of the first conductivity type with the drain contact region encompassed in the body region and the epitaxial contact region disposed in the epitaxial layer, forming a body contact region of the second conductivity type near a top surface of the body region disposed at a distance from the drain contact region; and forming a bottom source/emitter/anode electrode layer beneath the semiconductor substrate and forming on a top surface of the epitaxial layer a drain/collector/cathode electrode to contact the trench gate and the drain contact region and further forming a body to source short to electrically short the body contact region to the epitaxial contact region thus forming a TVS structure comprises a TVS diode, a vertical bipolar transistor and a bottom-source metal-oxide-semiconductor field effect transistor (BS-MOSFET) as three parallel connected vertical circuits between the drain/collector/cathode electrode disposed on top of the epitaxial layer and the bottom source/emitter/anode electrode layer.
2. The method of claim 1 wherein: the forming the drain/collector/cathode electrode to contact the trench gate and the drain region is a step of making the trench gate and the drain/collector/cathode electrode to have a same potential.
3. The method of claim 1 wherein: the forming the trench gate further comprising a step of forming the trench gate with a predesignated width according to a ratio of an area occupied by the drain contact region to an area occupied by the BS-MOSFET.
4. The method of claim 3 wherein: the forming the trench gate further comprising a step of forming the trench gate with a predesignated width according to a current flow through the BS-MOSFET required to trigger the vertical bipolar transistor.
5. The method of claim 1 wherein: the forming the epitaxial layer further comprising forming the epitaxial layer to have a predesignated resistance for adjusting a current flow through the BS-MOSFET to trigger the vertical bipolar transistor.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1A is a circuit diagram for showing a conventional TVS device and FIG. 1B is an I-V diagram, i.e., a current versus voltage diagram, for illustrating the reverse characteristics of the TVS device of FIG. 1A.
(2) FIG. 2A is a circuit diagram for showing another conventional TVS device and FIG. 2B is an I-V diagram for illustrating the reverse characteristics of that TVS device with the voltage showing a sudden snap-back voltage drop at the time when a current conduction over the NPN bipolar transistor is triggered.
(3) FIG. 3A is a circuit diagram for depicting a MOS triggered TVS of a prior art for triggering and protecting a device operated at a voltage below 5 Volts.
(4) FIG. 3B is a prior art diagram for showing the variation of the input voltage versus output voltage of the trigger circuit with three and four stacked PMOS transistors.
(5) FIGS. 4A and 4B are respectively a cross sectional view and an equivalent circuit diagram of a TVS device structure of this invention.
(6) FIG. 4C is the I-V diagram for showing the performance of the TVS structure of FIGS. 4A and 4B in suppressing a transient voltage.
(7) FIG. 5A is a perspective view for showing the TVS device structure of FIG. 4A.
(8) FIGS. 5B, 5C, and 5D are a perspective view, a cross sectional view, and a perspective view, respectively, for showing the configurations of alternate embodiments of this invention.
(9) FIGS. 6A and 6B are respectively a cross sectional view and an equivalent circuit diagram of a TVS device structure of this invention having reversed conductivity types as FIGS. 4A and 4B.
DETAILED DESCRIPTION OF THE INVENTION
(10) FIGS. 4A and 4B show a cross sectional view and the corresponding equivalent circuit elements respectively of a TVS device 100 of this invention. FIG. 4C is an I-V diagram that shows the current conduction and voltage characteristics of the TVS device 100. The TVS device 100 is formed in a N+ substrate 105 supporting a N-epitaxial layer 110 thereon with a anode terminal 115 disposed on the bottom and an cathode terminal 120 disposed on the top surface of the substrate that is contacted to a N+ drain/collector region 130. In addition to a TVS diode 150, the device also contains a NMOSFET 160 and a NPN bipolar transistor 170, as shown in the equivalent circuit 100. The connectivity of the terminals of the NMOS 160 and NPN bipolar transistor 170 in this structure are explained next. The TVS device-structure 100 includes a surface P+ body contact region 135 on top of a P-body region 125. The surface P+ body contact region 135 is connected to the anode/source/emitter terminal using a body to source short 145 that ties the P body 125 to the cathode potential, by shorting P+ body contact 135 to N+ epi contact region 112 located in the N-epitaxial layer 110. The connection of the body to the anode terminal also includes a series resistance formed by the low doped N-epitaxial layer 110, which is shown in the equivalent circuit as R.sub.epi. A diode 150 is also formed from the anode terminal 115 to the cathode terminal 120 at the PN junction of the P-body 125 and drain region 130. This diode 150 turns on when there is a negative voltage transient on the cathode terminal, and provides a path for current.
(11) The TVS structure 100 further includes trench gates 140 padded with trench gate oxide layer 142 to function with the anode 115, i.e., source, and the cathode 120, i.e., drain, electrodes and P-body region 125 as a bottom source (BS) NMOS transistor 160 for triggering the NPN Zener clamping circuit 170 formed between the N+ drain regions 130, the P-body regions 125 and the N-epitaxial layer 110 (and N+ substrate 105). As opposed to typical vertical MOSFETs, the source of NMOS 160 is on the bottom, at the N+ substrate 105, the source being shorted to the body 125 through the body to source short 145, body contact 135, N+ epi contact region 112 and epitaxial layer 110. The cathode terminal 120 shorts the trench gate 140 to the N+ drain region 130, which makes the gate and drain have the same potential.
Vgs=Vds
where Vgs is gate-to-source voltage and Vds is drain-to-source voltage. As is well known in the art, a MOSFET is in saturation mode when:
VdsVgsVt
And
Vgs>Vt
where Vt is the threshold voltage of the MOSFET 160. Therefore, whenever the MOSFET 160 is turned on (i.e., Vgs>Vt), it is always operating in saturation mode. Shorting the gate 140 to the drain 130 essentially configures the MOSFET 160 into a two terminal device and gets a stable and adjustable trigger voltage.
(12) The N+ drain region 130 also acts as the collector region for the NPN transistor. Likewise, the P body region 125 also acts as the base, and the N-epi 110 and N+ substrate 105 act as the emitter of the NPN transistor.
(13) FIG. 4C is an I-V diagram for showing the operation of the TVS circuit 100. The device turns on for a cathode bias larger than the NMOS threshold voltage Vt, and shows two modes of current conduction, Since the gate voltage Vgs is tied to the drain voltage Vds by the anode electrode 120, the bottom source NMOS 160 is off for cathode bias Vds smaller than the NMOS threshold voltage Vt, and gets triggered when the voltage on the cathode electrode 120 reaches a threshold voltage Vt. The triggering voltage of the TVS device 100 may be easily adjusted by changing the threshold voltage Vt of the NMOS. This way, a very low triggering voltage can be attained. In the first mode of current conduction, current flow happens through the MOS channel created along the trench gate 140 sidewall in P body region 125 and connecting the drain N+ region 130 to the N-epitaxial region 110. In this mode all the current is drain current, I.sub.D, of the NMOS 160. The presence of the low doped N-epitaxial region 110 provides series resistance R.sub.epi to the current flow, resulting in voltage drop V.sub.epi=I.sub.D*R.sub.epi across the N-epi 110 during the current flow. The I-V profile of the first mode of current conduction depends on both the drain current I.sub.D, and the R.sub.epi. This results in the forward biasing of the PN junction formed by the P base region 125 of the NPN transistor 170 and the N+ source 105 (and N-epi 110), and when this voltage drop V.sub.epi reaches the typical value of 0.7 Volts, it turns on the NPN transistor 170. At this point, the device enters the second mode of current conduction, as shown in the I-V curve, during which current conduction is shared by the NMOS 160 and the NPN bipolar transistor 170. In this mode of operation, the device achieves excellent clamping voltage with a small differential Rds due to minority carrier injection in the low doped N-epitaxial layer 110 by the NPN transistor 170 resulting in conductivity modulation. As a side note, all MOSFETs inherently have a parasitic bipolar transistor (formed by the Source-Body-Drain). In typical MOSFETs, it is highly undesirable to trigger this parasitic bipolar transistor. However in the current invention, the MOSFET is purposely used to trigger a bipolar transistor.
(14) A perspective view of the TVS device 100 is shown in FIG. 5A. The top oxides are not shown in this view for simplicity. The ratio of the NMOS vs NPN area can be modified by breaking the NMOS channel in the 3.sup.rd dimension, as shown in the TVS device 100 of FIG. 5B which illustrates an alternate embodiment of this invention. This technique can be used to adjust the current I.sub.D allowed by the NMOS 160. The amount of NMOS area determines the channel width of the NMOS 160, which in turn determines the current flow I.sub.D. TVS device 100 is the same as TVS device 100 of FIG. 5A, except that the width of the trench 140 is truncated to provide more area for the NPN bipolar transistor 170, and to decrease the area of the NMOS 160. This extra area for the NPN bipolar transistor 170 is indicated by the dashed line 101. Decreasing the area of the NMOS 160 will lower the current needed to trigger the NPN bipolar transistor 170. The different I-V curves shown in FIG. 4C demonstrate such a change. Another technique to tweak the I-V characteristics is to change the epi series resistance R.sub.epi, which can be done by adjusting the doping concentration of the epitaxial region 110.
(15) This invention is not limited to trench gate devices, but can also be applied to any type of bottom source device, as shown in the cross sectional figure of TVS device 100 in FIG. 5C. TVS device 100 has a planar gate electrode 140 and gate oxide 142 structure, rather than a trench gate. The gate electrode 140 and the drain 130 may be connected in the third dimension. FIG. 5D shows another alternative embodiment of this invention in which the body-source short 145 of TVS device 100 is located in the third dimension rather than in each cell like FIG. 4A. The body-source short 145 shorts the P+ body contact 135 to the N+ epi contact region 112 in the third dimension.
(16) Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. For example, though the descriptions above describes a TVS device using a NMOSFET and a NPN transistor, the invention could also be extended to a TVS device having opposite polarity, e.g., a PMOSFET and a PNP transistor. The conductivity types of each region would simply be reversed, as shown in TVS device 200 of FIG. 6A. TVS device 200 is the same TVS device 100 of FIG. 4A, but the conductivity type of each region is reversed. FIG. 6B shows an equivalent circuit diagram of the TVS device 200. Various alterations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.
