Dual-gain single-slope ADC with digital CDS

Abstract

A column-parallel dual-gain single-slope ADC comprises an input for receiving a signal V.sub.in, a sample-and-hold stage which receives V.sub.in and outputs sampled signal V.sub.in,samp, a comparator, a counter, and a ramp generator which generates high-gain (HG) and low-gain (LG) ramps, with the ratio of the LG ramp slope to the HG ramp slope being greater than 1. During a coarse conversion phase, V.sub.in,samp is compared with a threshold voltage V.sub.thresh, and a flag is set to a first or second state depending on the comparison. During a fine conversion phase, if the flag is in the first state, the HG ramp is provided to the comparator and its output toggles when the ramp voltage becomes equal to V.sub.in,samp. If the flag is in the second state, the LG ramp is provided to the comparator and its output toggles when the LG ramp voltage becomes equal to V.sub.in,samp.

Claims

1. A column-parallel dual-gain single-slope analog-to-digital converter (ADC), said ADC comprising: an input node for receiving an input signal V.sub.in, said input signal V.sub.in having an associated maximum input swing V.sub.in,max; a sample-and-hold (S/H) stage having an input coupled to said input node and arranged to sample V.sub.in and provide sampled signal V.sub.in,samp at an S/H output; a comparator having first and second inputs and an output; a threshold voltage V.sub.thresh; a counter, which steps through a predefined range of count values in a count time; a global ramp generator, that is common to multiple ADC columns and generates a high-gain (HG) ramp and a low-gain (LG) ramp, such that: said HG and LG ramps ramp up or down simultaneously; the ratio G of said LG ramp slope to said HG ramp slope is G>1; the swing of said LG ramp during said count time is V.sub.ramp,LGV.sub.in,max; the swing of said HG ramp during said count time is V.sub.ramp,HG=V.sub.ramp,LG/G; said ADC arranged such that: during a sampling phase, input signal V.sub.in is sampled by said S/H stage and the sampled voltage V.sub.in,samp is provided to said comparator's first input; during a coarse conversion phase, V.sub.in,samp is compared with V.sub.thresh and a flag hg_flag is set to either a first state or a second state depending on the comparison; during a fine conversion phase, which follows said coarse conversion phase and includes said count time, if said hg_flag is in said first state, said HG ramp is provided to said comparator's second input and said comparator output toggles when the HG ramp voltage becomes equal to V.sub.in,samp, and if said hg_flag is in said second state, said LG ramp is provided to said comparator's second input and said comparator output toggles when the LG ramp voltage becomes equal to V.sub.in,samp.

2. The ADC of claim 1, wherein said sampling phase occurs simultaneously with said coarse and fine conversion phases.

3. The ADC of claim 1, further arranged such that: said input signal V.sub.in varies between a constant reset level V.sub.rst and a signal level V.sub.sig=V.sub.rstV.sub.sig, where V.sub.sig is signal amplitude, which is either positive or negative depending on the application; during said count time said LG ramp swings from V.sub.ramp,LG,start to V.sub.ramp,LG,end=V.sub.ramp,LG,startV.sub.ramp,LG, where V.sub.ramp,LG has the same polarity as V.sub.sig, and V.sub.rst and V.sub.sig are between V.sub.ramp,LG,start and V.sub.ramp,LG,end; during said count time said HG ramp swings from V.sub.ramp,HG,start to V.sub.ramp,HG,end=V.sub.ramp,HG,startV.sub.ramp,HG, where V.sub.ramp,HG has the same polarity as V.sub.sig, and V.sub.rst is between V.sub.ramp,HG,start and V.sub.ramp,HG,end; said threshold voltage V.sub.thresh=V.sub.ramp,HG,end+V, where V has the same polarity as V.sub.sig and 0<|V|<|V.sub.ramp,HG|; if V.sub.sig>0, said hg_flag is in said first state if V.sub.in,samp>V.sub.thresh, and said hg_flag is in said second state if V.sub.in,sampV.sub.thresh; if V.sub.sig<0, said hg_flag is in said first state if V.sub.in,samp<V.sub.thresh, and said hg_flag is in said second state if V.sub.in,sampV.sub.thresh.

4. The ADC of claim 3, wherein said input signal V.sub.in is equal to said reset level V.sub.rst during a first reset read portion of a row time, and said input signal V.sub.in is equal to said signal level V.sub.sig during a second signal read portion of said row time.

5. The ADC of claim 4, said ADC operated to perform two conversions per row time and further arranged such that: the ADC digitizes said signal level V.sub.sig (signal conversion) and then said reset level V.sub.rst (reset conversion) in this order within said row time thereby performing digital correlated double sampling (CDS); said coarse conversion phase is present during said signal conversion and is not present during said reset conversion; the state of said hg_flag is established during said signal conversion and the same value is used during said reset conversion.

6. The ADC of claim 4, said ADC operated to perform one conversion per row time and further arranged such that: said reset read precedes said signal read; said sampling phase occurs during said signal read; and the ADC digitizes said signal level V.sub.sig.

7. The ADC of claim 5, wherein said reset read precedes said signal read.

8. The ADC of claim 1, wherein: said counter is an n-bit counter, the ADC quantization step is V.sub.ramp,LG/2.sup.n and the ADC resolution is n when said hg_flag is in said second state, the ADC quantization step is V.sub.ramp,LG/(G.Math.2.sup.n) and the ADC resolution is n+log.sub.2 G when said hg_flag is in said first state.

9. The ADC of claim 1, wherein G is a power of 2.

10. The ADC of claim 5, said ADC further arranged such that: said input signal V.sub.in is a pixel output having an associated pixel reset level and pixel signal level, said pixel reset level being the pixel output with no integrated photocurrent and said pixel signal level being the pixel output with integrated photocurrent; said reset level V.sub.rst is equal to said pixel reset level; and said signal level V.sub.sig is equal to said pixel signal level.

11. The ADC of claim 1, further comprising digital memory, said ADC arranged such that the value of said counter is latched and stored in said digital memory when said comparator output toggles during said fine conversion phase.

12. The ADC of claim 11, wherein said ADC is arranged to provide an output consisting of the counter value stored in said digital memory and the state of said hg_flag.

13. The ADC of claim 1, further comprising a multiplexer having at least three inputs and an output, said voltage V.sub.thresh, said HG ramp, and said LG ramp provided to respective multiplexer inputs and said output coupled to said comparator's second input, said ADC arranged to operate said multiplexer such that V.sub.thresh is selected and thereby connected to said multiplexer output during said coarse conversion phase, said HG ramp is selected and thereby connected to said multiplexer output during said fine conversion phase if said hg_flag is in said first state, and said LG ramp is selected and thereby connected to said multiplexer output during said fine conversion phase if said hg_flag is in said second state.

14. The ADC of claim 13, wherein said multiplexer comprises a local ramp buffer interposed between its inputs and its output.

15. The ADC of claim 14, wherein said local ramp buffer is a source follower.

16. The ADC of claim 1, further comprising an analog CDS stage interposed between said ADC input node and the input to said S/H stage.

17. The ADC of claim 16, wherein said analog CDS stage comprises: a capacitor connected in series between said CDS input and a first node; a clamp switch connected between said first node and a fixed voltage V.sub.clamp; and a buffer connected between said first node and said CDS output; said analog CDS stage further arranged such that: said clamp switch is closed during said reset read and the voltage at said CDS input is equal to a voltage V.sub.in1, said clamp switch is open during said signal read and the voltage at said CDS input is equal to a voltage V.sub.in2, said reset level V.sub.rst is substantially equal to said fixed voltage V.sub.clamp, and said signal amplitude V.sub.sig is substantially equal to (V.sub.in1V.sub.in2).

18. The ADC of claim 17, said ADC further arranged such that: said CDS input is a pixel output having an associated pixel reset level and pixel signal level, said pixel reset level being the pixel output with no integrated photocurrent and said pixel signal level being the pixel output with integrated photocurrent; said voltage V.sub.in1 is equal to said pixel reset level; and said voltage V.sub.in2 is equal to said pixel signal level.

19. The ADC of claim 17, wherein said buffer is a source follower.

20. The ADC of claim 7, wherein said S/H stage comprises: a first reset capacitor connected between a first reset node and a constant potential; a first reset sampling switch connected between said input node and said first reset node; a first reset select switch connected between said first reset node and said S/H output; a second reset capacitor connected between a second reset node and said constant potential; a second reset sampling switch connected between said input node and said second reset node; a second reset select switch connected between said second reset node and said S/H output; a signal capacitor connected between a signal node and said constant potential; a signal sampling switch connected between said input node and said signal node; and a signal select switch connected between said signal node and said S/H output.

21. The ADC of claim 20, wherein said first and second reset capacitors are used in alternate row times such that: in a first row time: during said reset read, the reset level for the current row is sampled on said first reset capacitor while the signal level sampled in the previous row is converted; and during said signal read, the signal level for the current row is sampled on said signal capacitor while the reset level sampled in the previous row is converted; and in a second row time: during said reset read, the reset level for the current row is sampled on said second reset capacitor while the signal level sampled in the previous row is converted; and during said signal read, the signal level for the current row is sampled on said signal capacitor while the reset level sampled in the previous row is converted.

22. The ADC of claim 1, wherein said global ramp generator is comprised of a HG ramp generator circuit and a LG ramp generator circuit, each ramp generator circuit comprising: an output node; a buffered output node; a ramp buffer connected between said output node and said buffered output node; a reset switch connected between said output node and a reset voltage; an integer number k unit capacitors, the top plate of each capacitor connected to said output node, and the bottom plate of each capacitor switched to either a first or a second reference level.

23. The ramp generator circuit of claim 22, further arranged such that: outside of said count time, said reset switch is closed and the bottom plates of said k unit capacitors are switched to said first reference level; during said count time said reset switch is open; said count time is divided into an integer number c clock cycles such that during each clock cycle an integer number m (1<m<k) unit capacitors are simultaneously switched from said first reference level to said second reference level; and at the end of said count time, the bottom plates of c.Math.m (c.Math.mk) unit capacitors are switched to said second reference level, and kc.Math.m unit capacitors are still switched to said first reference level.

24. The ramp generator circuit of claim 23, wherein said counter is an n-bit counter, and c=2.sup.p, where p is an integer and pn.

25. The ramp generator circuit of claim 23, further arranged such that: G is an integer; total unit capacitors k=G.Math.c; for said HG ramp, m=1 and at the end of said count time the bottom plates of k/G unit capacitors are switched from said first reference level to said second reference level; for said LG ramp, m=G and at the end of said count time k unit capacitors are switched from said first reference level to said second reference level.

26. A method of performing an analog-to-digital conversion, comprising: providing a high gain (HG) ramp; providing a low gain (LG) ramp, the slope of said LG ramp being greater than that of said HG ramp; providing a threshold voltage V.sub.thresh; during a sampling phase, sampling an input signal V.sub.in, said sampled input signal being V.sub.in,samp; during a coarse conversion phase: comparing V.sub.in,samp to V.sub.thresh and setting a flag hg_flag to either a first state or a second state depending on the comparison; and during a fine conversion phase which follows said coarse conversion phase: if hg_flag is in said first state: comparing said HG ramp to V.sub.in,samp; and toggling an output flag when the HG ramp voltage becomes equal to V.sub.in,samp; and if hg_flag is in said second state: comparing said LG ramp to V.sub.in,samp; and toggling said output flag when the LG ramp voltage becomes equal to V.sub.in,samp.

27. The method of claim 26, further comprising: providing a counting means which steps through a predefined range of count values in a count time; triggering said counting means to begin counting at the beginning of said fine conversion phase; and storing the present count when said output flag toggles.

28. The method of claim 27, wherein said analog-to-digital conversion operates over an associated input swing, the swing of said LG ramp covering said input swing in said count time.

29. The method of claim 28, wherein the slope of said LG ramp is G times that of said HG ramp, such that the swing of said HG ramp covers 1/G of said input swing in said count time.

30. The method of claim 27, further arranged such that: said input signal V.sub.in varies between a constant reset level V.sub.rst and a signal level V.sub.sig=V.sub.rstV.sub.sig, where V.sub.sig is signal amplitude, which is either positive or negative depending on the application; during said count time, said LG ramp swings from V.sub.ramp,LG,start to V.sub.ramp,LG,end=V.sub.ramp,LG,startV.sub.ramp,LG, where V.sub.ramp,LG has the same polarity as V.sub.sig, and V.sub.rst and V.sub.sig are between V.sub.ramp,LG,start and V.sub.ramp,LG,end; during said count time, said HG ramp swings from V.sub.ramp,HG,start to V.sub.ramp,HG,end=V.sub.ramp,HG,startV.sub.ramp,HG, where V.sub.ramp,HG has the same polarity as V.sub.sig, and V.sub.rst is between V.sub.ramp,HG,start and V.sub.ramp,HG,end; said threshold voltage V.sub.thresh=V.sub.ramp,HG,end+V, where V has the same polarity as V.sub.sig and 0<|V|<|V.sub.ramp,HG|; if V.sub.sig>0, said hg_flag is in said first state if V.sub.in,samp>V.sub.thresh, and said hg_flag is in said second state if V.sub.in,sampV.sub.thresh; and if V.sub.sig<0, said hg_flag is in said first state if V.sub.in,samp<V.sub.thresh, and said hg_flag is in said second state if V.sub.in,sampV.sub.thresh.

31. The method of claim 30, wherein said input signal V.sub.in is equal to said reset level V.sub.rst during a first reset read portion of a row time and said input signal V.sub.in is equal to said signal level V.sub.sig during a second signal read portion of said row time, said analog-to-digital conversion performing two conversions per row time and further comprising: digitizing said signal level V.sub.sig (signal conversion) and then said reset level V.sub.rst(reset conversion) in this order within said row time thereby performing digital correlated double sampling (CDS); wherein said coarse conversion phase is present during said signal conversion and is not present during said reset conversion; and the state of said hg_flag is established during said signal conversion and the same state is used during said reset conversion.

32. The method of claim 27, wherein: said counting means is an n-bit counter, the analog-to-digital quantization step is V.sub.ramp,LG/2.sup.n and the analog-to-digital conversion resolution is n when said hg_flag is in said second state, the analog-to-digital quantization step is V.sub.ramp,LG/(G.Math.2.sup.n) and the analog-to-digital conversion resolution is n+log.sub.2 G when said hg_flag is in said first state.

33. The method of claim 26, wherein G is a power of 2.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a block diagram of one possible embodiment of a DGSS ADC in accordance with the present invention.

(2) FIG. 1B is a timing diagram illustrating the principle of operation of the ADC shown in FIG. 1A.

(3) FIG. 2 is a schematic diagram of a possible implementation of a DGSS ADC with analog and digital CDS.

(4) FIG. 3A is a schematic diagram of a possible implementation of several of the circuit blocks shown in FIG. 2.

(5) FIG. 3B is a timing diagram illustrating the operation of the circuitry shown in FIG. 3A.

(6) FIG. 4 is a timing diagram of the signals used in the DGSS ADC implementation shown in FIGS. 2 and 3A.

(7) FIG. 5 is a schematic diagram illustrating the basic operating principles of a ramp generator as might be used with a DGSS ADC per the present invention.

(8) FIG. 6 is a schematic diagram illustrating one possible embodiment of the HG and LG ramp generators as might be used with a DGSS ADC per the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(9) One possible embodiment of a dual-gain single-slope analog-to-digital converter (DGSS ADC)suitably a column parallel DGSS ADCin accordance with the present invention is shown in FIG. 1A.

(10) The ADC 10 has an input node 12 for receiving an input signal V.sub.in having an associated maximum input swing V.sub.in,max, which would typically originate from a column bus of a pixel array. The input signal V.sub.in at input node 12 is optionally passed through an analog CDS stage 38, which drives a sample-and-hold (S/H) stage 14. Alternatively, the input node 12 is coupled directly to the S/H stage 14. The S/H stage 14 is arranged to provide sampled signal V.sub.in,samp at an S/H output 16, which is connected to the first input of comparator 18. The second input of comparator 18 is connected to the output of multiplexer 36, which selects one of three voltages: a DC threshold voltage V.sub.thresh, a high-gain (HG) ramp V.sub.ramp,HG, and a low-gain (LG) ramp V.sub.ramp,LG. The HG and LG ramp voltages are generated by a global ramp generator 22. The ADC also includes a 1-bit digital storage called hg_flag 24 and an 11-bit digital storage called fine data 32. The ADC also includes an 11-bit counter 20 which steps through a predefined range of count values (for example, from 0 to 2047) in a count time. In this ADC embodiment, all aforementioned circuit blocks with the exception of the ramp generator 22 and counter 20, are located in an ADC column 34. The counter 20 is preferably global: its output forms an 11-bit counter bus, which is shared among multiple ADC columns 34. Similarly, the ramp generator 22 is preferably global: the HG and LG voltage ramps are shared among multiple ADC columns 34. The stored values of the 1-bit hg_flag 24 and the 11-bit fine data 32 form the ADC output and are read out on a 12-bit data bus 28.

(11) The principle of operation of the DGSS ADC is better understood with the help of FIG. 1B. The ADC operation consists of three phases: sampling phase, coarse conversion phase and fine conversion phase. For simplicity, in this example the sampling phase precedes the other two phases although this is not necessary; in order to increase the ADC conversion rate, the sampling phase may be concurrent with the coarse and fine conversion phases as will be shown later. The HG and LG ramp signals have substantially the same start voltage and ramp up or (in this case) down simultaneously during the count time. The ratio G of the LG ramp slope to the HG ramp slope must be greater than one; G=8 in the example shown, and is preferably a power of 2. The swing of the LG ramp during the count time is V.sub.ramp,LG, with V.sub.ramp,LG required to be greater than or equal to the input swing V.sub.in,max. The swing of the HG ramp during the count time is V.sub.ramp,HG, which is given by: V.sub.ramp,LG/G.

(12) ADC 10 is arranged such that:

(13) During the sampling phase, input signal V.sub.in is sampled by S/H stage 14 and the sampled voltage V.sub.in,samp is provided to the first input of comparator 18.

(14) During the coarse conversion phase, multiplexer 36 is configured such that DC threshold voltage V.sub.thresh is routed to the second input of comparator 18 such that V.sub.in,samp is compared with V.sub.thresh. For descending HG and LG ramps (as in this example), V.sub.thresh is positioned to be slightly higher than the value of the LG ramp at the end of the count time. The comparator output signal 26 (called latch) during the coarse phase establishes the state of hg_flag: hg_flag=1 if V.sub.in,samp>V.sub.thresh and hg_flag=0 otherwise. In the example of FIG. 1B, V.sub.in,samp<V.sub.thresh and hg_flag is set to 0 during the coarse conversion phase.

(15) During the fine conversion phase, which follows the coarse conversion phase and includes the count time:

(16) multiplexer 36 routes either the HG ramp or the LG ramp to the second input of comparator 18 depending on hg_flag: if hg_flag=1, V.sub.ramp,HG is provided to the second input of comparator 18 and the comparator output 26 toggles when the HG ramp voltage becomes equal to V.sub.in,samp, and if hg_flag=0, V.sub.ramp,LG is provided to the second input of comparator 18 and comparator output 26 toggles when the LG ramp voltage becomes equal to V.sub.in,samp.

(17) When the latch signal toggles, the current counter value is latched and stored as the fine data. In the example of FIG. 1B, hg_flag=0 and hence during the fine conversion phase, V.sub.in,samp is compared against V.sub.ramp,LG. When V.sub.ramp,LG=V.sub.in,samp, the comparator toggles and the counter value (638 in this example) is latched and stored as the fine data.

(18) The ADC quantization step is obtained by dividing the ramp swing during the count time by the number of counter steps. The ramp swing, and hence the quantization step, is different depending on whether the HG or LG ramp is selected. Assuming the counter is an n-bit counter, the ADC quantization step is V.sub.ramp,LG/2.sup.n and the ADC resolution is n when the hg_flag=0, and the ADC quantization step is V.sub.ramp,LG/(G.Math.2.sup.n) and the ADC resolution is n+log.sub.2 G when hg_flag=1. As an example, the ADC embodiment shown in FIG. 1B has an 11-bit counter and ramp slope ratio G=8. Thus the ADC quantization step is V.sub.ramp,LG/2048 and the ADC resolution is 11 bits when hg_flag=0, and the ADC quantization step is V.sub.ramp,LG/16384 and the ADC resolution is 14 bits when hg_flag=1.

(19) As seen, the DGSS ADC has a variable quantization step. Accordingly, the ADC quantization noise is

(20) $\frac{1}{\sqrt{12}}$
counts when the HG ramp is used and

(21) $\frac{G}{\sqrt{12}}$
counts when the LG ramp is used. This property makes the DGSS ADC particularly well suited to image sensors converting a pixel output signal that represents the integrated photocurrent on a capacitor. It is desirable that the pixel dark level (the pixel output when there is no integrated photocurrent) falls within the swing of the HG ramp. Thus in low illumination conditions (when the pixel output is close to the dark level), the ADC uses the HG ramp and the quantization step is small. For higher illumination the integrated photocurrent increases and so does the resulting photon shot noise. If the photon shot noise is the dominant noise source, then the ADC quantization step can be relaxed. Assuming that the pixel full well capacity in electrons is N.sub.max and the LG ramp swing spans the full well capacity, it can be shown that the shot noise (expressed in ADC counts) at the end of the HG ramp swing is

(22) $\frac{2^n}{\sqrt{\frac{N_{max}}{G}}}.$
The ADC counter resolution n and ramp slope ratio G should be chosen such that the ADC quantization noise when switching to the LG ramp is much less than the shot noise:

(23) $\frac{G}{\sqrt{12}}\frac{2^n}{\sqrt{\frac{N_{max}}{G}}}.$

(24) The ADC implementation of FIG. 1B has descending HG and LG ramps and is compatible with a pixel output signal that decreases with illumination. In the case when the pixel output signal increases with illumination, the DGSS ADC preferably uses ascending HG and LG ramps. Below is a more precise definition (which is equally applicable to (ascending and descending ramps) of the HG and LG ramp swings, the position of the threshold voltage V.sub.thresh and the condition for establishing the value of hg_flag. The input signal V.sub.in to the DGSS ADC varies between a constant reset level V.sub.rst and a signal level V.sub.sig=V.sub.rstV.sub.sig, where V.sub.sig is signal amplitude, which is either positive or negative depending on the application. During the count time, the LG ramp swings from a voltage V.sub.ramp,LG,start to a voltage V.sub.ramp,LG,end=V.sub.ramp,LG,startV.sub.ramp,LG, where V.sub.ramp,LG has the same polarity as V.sub.sig, and V.sub.rst and V.sub.sig are between V.sub.ramp,LG,start and V.sub.ramp,LG,end. Similarly, during the count time, the HG ramp swings from a voltage V.sub.ramp,HG,start to a voltage V.sub.ramp,HG,end=V.sub.ramp,HG,startV.sub.ramp,HG, where V.sub.ramp,HG has the same polarity as V.sub.sig, and V.sub.rst is between V.sub.ramp,HG,start and V.sub.ramp,HG,end.

(25) The threshold voltage V.sub.thresh is preferably given by V.sub.ramp,HG,end+V, where V has the same polarity as V.sub.sig and 0<|V|<|V.sub.ramp,HG|. If V.sub.sig>0, hg_flag=1 if V.sub.in,samp>V.sub.thresh, and hg_flag=0 if V.sub.in,sampV.sub.thresh. If V.sub.sig<0, hg_flag=1 if V.sub.in,samp<V.sub.thresh, and hg_flag=0 if V.sub.in,sampV.sub.thresh.

(26) If V.sub.sig<V.sub.rst, the HG and LG ramps are arranged to be descending (as shown in FIG. 1B), and if V.sub.sig>V.sub.rst, the HG and LG ramps are arranged to be ascending.

(27) In CMOS image sensors targeting low read noise it is desirable to cancel the kTC reset noise stored on the pixel integrating capacitor. This is accomplished by performing correlated double sampling (CDS), i.e. reading the reset level (the pixel output without integrated photocurrent) and the signal level (the pixel output with integrated photocurrent) sequentially within the same row time and subtracting the reset level from the signal level. This subtraction is often performed in the column circuitry outside of the pixel array. The CDS subtraction can be carried out by an analog CDS stage 38 as shown in FIG. 1A. Alternatively, the CDS subtraction can be performed digitally if the ADC digitizes both the the signal and reset levels. Compared to analog CDS, digital CDS not only cancels the pixel kTC reset noise and reset level variation but also removes all offsets and suppresses 1/f noise in the entire analog chain. As a result, fixed-pattern noise (FPN) and gradients in the image are greatly reduced.

(28) The DGSS ADC supports three CDS methods:

(29) 1) Analog CDS, wherein the ADC performs one conversion per row time digitizing the signal level of the CDS stage, which is the difference between the pixel reset level and the pixel signal level;

(30) 2) Digital CDS, wherein the ADC performs two conversions per row time digitizing consecutively first the pixel signal level and then the pixel reset level;

(31) 3) Analog+digital CDS, in which case the ADC performs two conversions per row time digitizing consecutively first the signal level of the analog CDS stage (the difference between the pixel reset level and the pixel signal level) and then the reset level of the analog CDS stage.

(32) Sometimes the random variation of the pixel reset level from pixel to pixel is large enough that it takes a sizeable portion of the HG ramp swing, thereby limiting the pixel voltage range in which the ADC maintains the fine quantization step. This is a shortcoming of method 2, which is overcome by using method 3, for which the variation of the pixel reset level is absorbed by the analog CDS stage. While methods 2 and 3 both cancel the offsets and reduce the 1/f noise of the entire analog chain, method 3 also cancels the kTC reset noise of the CDS stage. For methods 2 and 3 it is preferable that the same voltage ramp (either HG or LG) is used in the fine conversion phase of both signal and reset conversions so that the effects of the comparator offset and delay are canceled after digital CDS. Thus, the coarse phase of the first conversion defines the value of hg_flag which is used during the fine phase of both conversions; the second conversion in fact need not have a coarse phase. Also the signal level must be digitized first in order to determine which ramp (HG or LG) to use. However, depending on the pixel architecture, the signal level may or may not be the first one to be read out of the pixel within the row time. In fact, for visible pixels using a pinned photodiode and a transfer gate the reset level is read out before the signal level. In this case the DGSS ADC must have a means to reorder the samples such that the signal level is digitized first even though it is read out after the reset level.

(33) FIG. 2 shows a preferred embodiment of a DGSS ADC that supports analog+digital CDS (method 3) and also combines the following useful features: 1) sampling and conversion occur simultaneously; and 2) the ADC reorders the input samples, i.e. it converts the signal level first even though the pixel reset level is provided to the ADC before the pixel signal level. The DGSS ADC of FIG. 2 consists of the same main building blocks as outlined in FIG. 1A: analog CDS stage 38, S/H stage 14, multiplexer 36 and comparator 18. The structure and operation of these building blocks will be described next.

(34) The analog CDS stage 38 comprises a capacitor C1 connected in series between input node 12 and a node 40. A clamp switch, which is operated with a control signal clamp, is connected between node 40 and a fixed CDS clamp voltage V.sub.clamp,cds. It should be noted that the kTC reset noise sampled on capacitor C1 when the clamp switch is opened is canceled by the digital CDS operation. Therefore, capacitor C1 can be small. A CDS buffer circuit 42 is connected between node 40 and the input to S/H stage 14. If the voltage at input node 12 is equal to V.sub.in1 during a first portion of the row time and is equal to V.sub.in2 during a second portion of the row time, the analog CDS stage is arranged such that:

(35) the clamp switch is closed during the first portion of the row time and the voltage at the CDS input is equal to a voltage V.sub.in1;

(36) the clamp switch is open during the second portion of the row time and the voltage at the CDS input is equal to a voltage V.sub.in2;

(37) the reset level V.sub.rst is substantially equal to fixed voltage V.sub.clamp,cds; and

(38) the signal amplitude V.sub.sig is substantially equal to (V.sub.in1V.sub.in2).

(39) If V.sub.in is a pixel output having an associated pixel reset level and pixel signal level, the pixel reset level being the pixel output with no integrated photocurrent and the pixel signal level being the pixel output with integrated photocurrent, then the voltage V.sub.in1 is equal to the pixel reset level, and the voltage V.sub.in2 is equal to the pixel signal level. In the presence of the analog CDS stage 38 as shown in FIG. 2, the DGSS ADC converts the CDS stage reset level (substantially equal to V.sub.clamp,cds) and the CDS stage signal level (substantially equal to V.sub.clamp,cdsV.sub.sig). If the analog CDS stage 38 is omitted, then the DGSS ADC converts the pixel reset level and the pixel signal level. In the following description reset level and signal level refer to either the CDS stage reset/signal level (in the presence of CDS stage) or the pixel signal/reset level (if the CDS stage is omitted).

(40) The exemplary implementation of S/H stage 14 shown in FIG. 2 allows input sampling and analog-to-digital (A/D) conversion to be carried out in parallel. Furthermore, it has the useful property that it reorders the input samples; i.e. it allows the ADC to convert the signal level before the reset level even though the latter is sampled before the former. The CDS stage 14 comprises three sampling capacitors: two for reset sampling (C.sub.r0 and C.sub.r1) and one for signal sampling (C.sub.s). A first reset capacitor C.sub.r0 connected between a first reset node 44 and a constant potential, suitably ground, a first reset sampling switch operated with a control signal smp_r0 connected between the stage's input node 46 and first reset node 44, and a first reset select switch operated with a control signal con_r0 connected between first reset node 44 and S/H output 16. The stage further comprises a second reset capacitor C.sub.r1 connected between a second reset node 48 and the constant potential, a second reset sampling switch operated with a control signal smp_r1 connected between input node 46 and second reset node 48, and a second reset select switch operated with a control signal con_r1 connected between the second reset node and S/H output 16. A signal capacitor C.sub.s is connected between a signal node 50 and the constant potential, a signal sampling switch operated with a control signal smp_s is connected between input node 46 and signal node 50, and a signal select switch operated with a control signal con_s is connected between the signal node and S/H output 16.

(41) A switch operated with a control signal clr is connected between S/H output 16 and the constant potential. This switch is closed momentarily to clear the charge at S/H output 16 from the previous conversion before any of the three capacitors C.sub.s, C.sub.r0 or C.sub.r1 is connected to S/H output 16. A switch operated with a control signal clr_s may be connected between node 50 and the constant potential. This switch resets node 50 to the constant potential before the smp_s switch is closed, thereby discharging capacitor C.sub.s and helping CDS buffer circuit 42 settle if it is implemented as a source follower. For example, if C.sub.s is discharged to ground and the CDS buffer is an NMOS source follower, then the settling time will be shortened because an NMOS source follower can deliver more current than its quiescent bias current on a low-to-high transition. A similar improvement in settling time can be achieved if the CDS buffer circuit 42 is a PMOS source follower, but then node 50 must be reset to a high potential. Note that resetting of nodes 44 and 48 is not needed to speed up the CDS buffer settling when driving the reset level because the reset level is essentially the same from one row time to the next and capacitors C.sub.r0 and C.sub.r1 remain charged essentially to the same level.

(42) In a preferred mode of operation, there are two ADC conversions per row time, with the pixel reset level sampled before the signal level. The ADC converts the signal level before the reset level. More specifically, first and second reset capacitors C.sub.r0 and C.sub.r1 are used in alternate row times such that, in a first row time:

(43) during the first portion of the first row time, the reset level for the current row is sampled on first reset capacitor C.sub.r0 while the signal level sampled in the previous row is converted; and

(44) during the second portion of the first row time, the signal level for the current row is sampled on signal capacitor C.sub.s while the reset level sampled in the previous row is converted. Then in a second row time:

(45) during the first portion of the second row time, the reset level for the current row is sampled on the second reset capacitor C.sub.r1 while the signal level sampled in the previous row is converted; and

(46) during the second portion of the second row time, the signal level for the current row is sampled on signal capacitor C.sub.s while the reset level sampled in the previous row is converted. This sequence of events and the pipelined operation of sampling and analog-to-digital conversion are illustrated in the table at the bottom of FIG. 2. Here R1 and S1 denote the reset level and the signal level, respectively, of sample 1. Similarly R2 and S2 denote the reset level and the signal level, respectively, of sample 2. The subscript after the reset level identifies which of the two reset capacitors (C.sub.r0 or C.sub.r1) the voltage level is sampled on. For example, R1.sub.cr0 denotes that the resel level of sample 1 is sampled on capacitor C.sub.r0. The signal level (S1, S2, etc.) is always sampled on capacitor C.sub.5. It is evident that while R1 precedes S1 during sampling, S1 precedes R1 during A/D conversion; i.e. the order is reversed.

(47) FIG. 2 also illustrates a possible implementation of multiplexer 36. Ramp signals V.sub.ramp,HG, V.sub.ramp,LG, and threshold voltage V.sub.thresh are provided to respective inputs, any one of which can be selected and conveyed to a node 52. Node 52 may be connected directly to the second input of comparator 18; a local ramp buffer circuit 54 might optionally be interposed between node 52 and comparator 18 to isolate the ramp from comparator kickback. In a preferred embodiment local ramp buffer 54 and CDS buffer 42 have an identical circuit implementation so that the buffer's input-output voltage nonlinearity is canceled. For example, local ramp buffer 54 and CDS buffer 42 may be implemented as identical source followers. During the coarse conversion phase of the signal conversion, multiplexer 36 is configured such that threshold voltage V.sub.thresh is routed to node 52. The value of single-bit hg_flag is established during the coarse conversion phase of the signal conversion depending on whether the signal at S/H output 16 V.sub.in,comp is greater than or less than V.sub.thresh. During the fine conversion phase of the signal and reset conversion, multiplexer 36 is configured such that either V.sub.ramp,HG or V.sub.ramp,LG is routed to node 52 depending on the state of hg_flag.

(48) FIG. 3a illustrates one possible implementation of multiplexer 36 and the generation of hg_flag and the comparator output signal called latch. FIG. 3B is a preferred timing diagram for the signals shown in FIG. 3A. As in FIG. 2, multiplexer 36 receives ramp signals V.sub.ramp,HG, V.sub.ramp,LG, and threshold voltage V.sub.thresh at respective inputs. During the coarse signal conversion phase signal coarse is high, and is low during the fine signal and reset conversion phases. This signal controls the operation of the multiplexer switches: while coarse is high the switches selecting V.sub.ramp,HG and V.sub.ramp,LG are open and the switch selecting V.sub.thresh is closed. The multiplexer output node 52 is preferably connected to local ramp buffer circuit 54, the output of which is provided to the second input of comparator 18. The first input of comparator 18 is the S/H output 16, the voltage at which is V.sub.in,comp. The output 26 of the comparator is preferably provided to a D-latch 24, which is an implementation of the memory element in FIG. 1A. At the end of the coarse conversion phase signal txc is pulsed high, which stores the comparator value in D-latch 24. Thus the value of hg_flag is established during the coarse conversion phase depending on whether V.sub.in,comp is less than or greater than V.sub.thresh. During the following fine signal and reset conversion phases signals txc and coarse remain low; the value of hg_flag is unchanged and either the switch selecting V.sub.ramp,HG (if hg_flag=1) or the switch selecting V.sub.ramp,LG (if hg_flag=0) is closed in multiplexer 36. The ADC also preferably includes a logic OR gate 62 whose inputs are the output 26 of the comparator and a signal set. The latter is pulsed high at the end of the count time during signal and reset fine conversion and forces the OR gate 62 output to also go high regardless of the comparator state. The set signal forces the ADC to latch the highest count value in case the comparator never trips because V.sub.in,comp is outside the range of V.sub.ramp,LG. The OR gate's output is provided to an RS latch 64, whose role is to filter out any comparator chatter. Namely, the output of the RS-latch (the latch signal) goes high as soon as the OR gate's output goes high; once the latch signal goes high, it remains high until the RS-latch is cleared by means of the rstb signal. The latch signal is provided to the DGSS digital memory, which includes 11-bit signal fine data and 11-bit reset fine data. When the latch signal goes high during the signal or reset count time, the value of the 11-bit counter bus is latched and stored as the 11-bit signal or reset fine data.

(49) FIG. 4 is one possible timing diagram of the signals used in the DGSS ADC implementation shown in FIGS. 2 and 3A. The signal waveforms are plotted over two row times where each row time includes one signal conversion and one reset conversion.

(50) FIG. 5 is a simplified schematic diagram illustrating the principle of operation of a HG or LG ramp generator as might be used with the present DGSS ADC. Such a ramp generator would typically be employed globally; i.e. it would be shared among multiple ADC columns. One of the key requirements of the ramp generator is to be monotonic, and hence a suitable solution is a capacitive digital-to-analog converter (CDAC) comprised of k unit capacitors C.sub.u. As shown in FIG. 5, the top plates of all unit capacitors 82 are connected to a summing node 72, the voltage at which is V.sub.sum. The bottom plate of each unit capacitor is switched (using respective switches controlled by signals s.sub.1, s.sub.2, s.sub.3, s.sub.4 to s.sub.k) to either a first or a second reference level (here, a buffered reference voltage V.sub.ref and ground, respectively). A reset switch 78 is connected between summing node 72 and a reset voltage V.sub.rst, preferably buffered with a buffer 80. The ramp generator 70 preferably includes a ramp buffer 74 which provides a buffered output V.sub.ramp at a buffered output node 76.

(51) The following description applies to the generation of a descending ramp; for an ascending ramp, the ramp generator operation remains the same but the first and second reference levels need to be exchanged. It is assumed that the count time is divided into an integer number c clock cycles. The ramp generator circuit is arranged such that outside of the count time, reset switch 78 is closed and switches s.sub.1-s.sub.k are operated such that the bottom plates of all k unit capacitors are switched to first reference level V.sub.ref. Then during the count time, reset switch 78 is open, and on every clock cycle an integer number m unit capacitors are simultaneously switched from V.sub.ref to ground. Due to charge conservation at the summing node 72, this operation results in a voltage step on every clock cycle

(52) $V_{\mathrm{sum}}=-\frac{{\mathrm{mC}}_u}{{\mathrm{kC}}_u+C_0}{V}_{\mathrm{ref}},$
where C.sub.0 is any additional capacitance at the summing node 78. If kC.sub.u>>C.sub.0, the voltage step at the summing node 72 on every clock cycle is

(53) $V_{\mathrm{sum}}-\frac{m}{k}{V}_{\mathrm{ref}}.$
At the end of the count time after c clock cycles have been completed the ramp swing is

(54) $V_{\mathrm{ramp}}=c{V}_{\mathrm{sum}}-\frac{c.Math.m}{k}{V}_{\mathrm{ref}},$
where c.Math.m is the total number of unit capacitors (c.Math.mk) whose bottom plates have been switched from V.sub.ref to ground. At the end of the count time the bottom plates of kc.Math.m unit capacitors remain connected to V.sub.ref.

(55) The CDAC switching frequency and the DGSS ADC counting frequency are normally related. The CDAC switching frequency is typically lower than the ADC counting frequency (for example 4 lower). This results in a CDAC voltage step V.sub.sum that is larger than the ADC quantization step (for example, 4 larger), but filtering due to limited ramp buffer bandwidth produces smooth V.sub.ramp(t) and minimum ADC differential non-linearity (DNL). If the DGSS ADC uses an n-bit counter, then the number c of CDAC steps during the count time is preferably given by c=2.sup.p, where p is an integer and pn. For example, if n=11 and p=9, then during the count time the ADC counter will go through 2.sup.11=2048 counts while the CDAC will go through 2.sup.9=512 cycles. This example illustrates a CDAC switching frequency that is 4 lower than the ADC counting frequency.

(56) As shown in FIG. 6, the HG and LG ramps as required by the DGSS ADC may be generated by two identical CDAC instances each composed of the same number of unit capacitors. In order to ensure a well defined LG-to-HG ramp slope ratio, the buffered reference voltage V.sub.ref is preferably shared between the two CDACs. Each ramp may have the same or different reset voltage; in this example, different buffered reset voltages (V.sub.rst,HG and V.sub.rst,LG, respectively) are used to define the start levels of the HG and LG ramps, respectively, for an extra degree of adjustability. If the LG-to-HG ramp slope ratio G is an integer, the total number of unit capacitors in each CDAC is k=G.Math.c. For the CDAC generating the HG ramp, m.sub.HG=1 (one unit capacitor is switched from V.sub.ref to ground on each clock cycle) and at the end of the count time the bottom plates of k/G unit capacitors are switched from V.sub.ref to ground. For the CDAC generating the LG ramp, m.sub.LG=G (G unit capacitors are switched from V.sub.ref to ground on each clock cycle) and at the end of the count time all k unit capacitors are switched from V.sub.ref to ground. In the example of FIG. 6, it is assumed that m.sub.LG=G=8. The HG ramp swing over the count time is:

(57) $V_{\mathrm{ramp},\mathrm{HG}}=c{V}_{\mathrm{sum},\mathrm{HG}}=-\frac{c.Math.m_{\mathrm{HG}}{C}_u}{{\mathrm{kC}}_u+C_0}{V}_{\mathrm{ref}}=-\frac{\frac{k}{G}{C}_u}{{\mathrm{kC}}_u+C_0}{V}_{\mathrm{ref}}.$
The LG ramp swing over the count time is:

(58) $V_{\mathrm{ramp},\mathrm{LG}}=c{V}_{\mathrm{sum},\mathrm{LG}}=-\frac{c.Math.m_{\mathrm{LG}}{C}_u}{{\mathrm{kC}}_u+C_0}{V}_{\mathrm{ref}}=-\frac{k{C}_u}{{\mathrm{kC}}_u+C_0}{V}_{\mathrm{ref}}.$
The HG and LG ramp slopes are entirely dependent on capacitor ratio and are insensitive to process, supply voltage, and temperature (PVT) variation. As can be seen, the ratio of the LG ramp slope to the HG ramp slope:

(59) 0$\frac{V_{\mathrm{ramp},\mathrm{LG}}}{V_{\mathrm{ramp},\mathrm{HG}}}=G$
and is independent of C.sub.u, C.sub.0 and V.sub.ref.

(60) As an example of a ramp generator as might be used with the present DGSS ADC: For LG ramp generation:

(61) the CDAC uses 4096 total unit capacitors (4096C.sub.u)

(62) 8 unit capacitors (8C.sub.u) switched per clock cycle

(63) 512 clock cycles (T.sub.c)

(64) 8512=4096 total switched unit capacitors

(65) When so arranged, V.sub.ramp,LG is given by:

(66) $V_{\mathrm{ramp},\mathrm{LG}}=V_{\mathrm{rst}}-\frac{t}{512T_c}{V}_{\mathrm{ref}}$

(67) For HG ramp generation:

(68) DAC uses 4096 total unit capacitors (4096C.sub.u)

(69) 1 unit capacitor (C.sub.u) switched per clock cycle

(70) 512 clock cycles (T.sub.c)

(71) 512 total switched unit capacitors

(72) When so arranged, V.sub.ramp,HG is given by:

(73) $V_{\mathrm{ramp},\mathrm{HG}}=V_{\mathrm{rst}}-\frac{t}{512T_c}\frac{V_{\mathrm{ref}}}{8}$

(74) To summarize, the DGSS ADC described herein preferably uses two simultaneous global ramps of different slopesa low-gain (LG) ramp spanning the full input range and a high-gain (HG) ramp spanning a fraction of the input rangepreferably near the pixel dark level. If G is the ratio of the LG and HG ramp slopes, the resulting ADC quantization step when the HG ramp is selected is G-times smaller than when the LG ramp is selected. The ADC therefore has a variable quantization step depending on the input voltage. This approach effectively increases the ADC dynamic range by a factor of G while preserving the same conversion time. As a result, it is possible to design a DGSS ADC combining, for example, 14-bit dynamic range with the conversion speed of an 11-bit ADC. The HG and LG ramps are preferably generated by CDACs, with the HG ramp selected when digitizing input signals close to the pixel dark level, and the LG ramp selected when digitizing input signals away from the pixel dark level. The HG/LG ramp selection is performed during a coarse conversion phase. The sampled signal is compared against a threshold voltage positioned towards the end of the HG ramp swing. During the following fine conversion phase, the comparator is connected to either the HG ramp or the LG ramp. When the ramp becomes equal to the input, the comparator toggles and the current counter value is stored. A single comparator is used for selection between the HG and LG ramps during the coarse conversion phase, and for HG/LG conversion during the fine conversion phase. Using the same comparator for both HG and LG is preferred in order to achieve no discontinuity at the HG/LG switch point. The DGSS ADC may be used to implement digital CDS, in which case it performs two conversions (one of the signal level and one of the reset level) per row time. The same ramp (either HG or LG) is used for both signal and reset conversion. This cancels the comparator delay and all offsets in the analog chain after digital CDS.

(75) Also note that the present DGSS ADC requires a small layout area and fits in a small column pitch, for example 2.8 m. In addition, it does not require capacitor matching, is inherently monotonic, and has no column-to-column gain errors (if using a shared voltage ramp). The design eases the resolution-speed tradeoff and is ideal for image sensors that have a relatively small well capacity. With an 11-bit counter and an LG-to-HG ramp slope ratio of 8, the DGSS ADC can be arranged to behave as a 14-bit ADC in terms of quantization step near the pixel dark level, and an 11-bit ADC in terms of speed.

(76) The embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.