DC/DC RESONANT CONVERTERS AND POWER FACTOR CORRECTION USING RESONANT CONVERTERS, AND CORRESPONDING CONTROL METHODS

Abstract

Various improvements are provided to resonant DC/DC and AC/DC converter circuit. The improvements are of particular interest for LLC circuits. Some examples relate to self-oscillating circuit and others relate to converter circuits with frequency control, for example for power factor correction, driven by an oscillator.

Claims

1. An AC/DC PFC converter, comprising: an AC input; a rectifier; a half bridge inverter comprising a first switch and a second switch, wherein an output is defined from a node between the first and second switches; a self-oscillating LLC circuit coupled to the output, the LLC circuit being arranged to provide an electrical feedback parameter; and a control circuit for generating a gate drive signal for controlling the switching of the first and second switches in dependence on the electrical feedback parameter, wherein a high gate drive signal turns on the first switch and turns off the second switch and a low gate drive signal turns off the first switch and turns on the second switch, wherein the control circuit is for determining a first time duration corresponding to an on-time of the first switch and for determining a second time duration corresponding to an on-time of the second switch, the first time duration and the second time duration together defining a duty cycle of the second switch, the duty cycle of the second switch having a defined value, and wherein the control circuit further comprises an integrator for: integrating a first constant value until the control circuit detects that the electrical feedback parameter reaches a threshold value defining the first time duration; and subsequently integrating a second constant value of opposite sign to the first constant value defining the second time duration.

2. The converter as claimed in claim 1, wherein the constant values are derived from the gate drive signal.

3. The converter as claimed in claim 2, wherein the integrator has a reference input set to a fixed voltage within the range of the gate drive signal.

4. The converter as claimed in claim 3, wherein the integrator has the reference input set to the mid-point of the gate drive signal.

5. The converter as claimed in claim 1, further comprising an RC output filter at the output of the integrator.

6. The converter as claimed in claim 5, further comprising a shorting transistor at the output of the RC output filter, which is turned on when the integrator output is a falling slope and is turned off when the integrator output is a rising slope.

7. The converter as claimed in claim 1, wherein the electrical feedback parameter comprises a voltage across a capacitor of the LLC circuit.

8. The converter as claimed in claim 1, comprising a transformer between the self-oscillating LLC circuit and an output load.

9. An apparatus comprising the converter as claimed in claim 1; and the output load.

10. The apparatus as claimed in claim 9 where the output load is an LED arrangement of one or more LEDs.

11. An AC/DC PFC conversion method, comprising: rectifying an AC input; operating a half bridge inverter comprising a first switch and a second switch using a gate drive signal and providing an output from a node between the switches, wherein a high gate drive signal turns on the first switch and turns off the second switch and a low gate drive signal turns off the first switch and turns on the second switch; providing an electrical feedback parameter from a self-oscillating LLC circuit coupled to the output, wherein an electrical feedback parameter is provided by the LLC circuit; controlling the switching of the first and second switches by: determining a first time duration corresponding to an on-time of the first switch and determining a second time duration corresponding to an on-time of the second switch, and integrating a first constant value until the electrical feedback parameter reaches a threshold value defining the first time duration; and subsequently integrating a second constant value of opposite sign to the first constant value defining the second time duration.

12. An LED driving method comprising providing conversion using the method of claim 11, and driving an LED load using the converted DC voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0205] Examples of the invention will now be described in detail with reference to the accompanying drawings, in which:

[0206] FIG. 1 shows an example of a resonant AC/DC converter which forms a PFC stage;

[0207] FIG. 2 shows the voltage gain with respect to the normalized switching frequency for different powers;

[0208] FIG. 3 shows the mains current versus the normalized switching frequency for different input AC voltage levels;

[0209] FIG. 4 shows the general task of a power factor correction required by an LLC converter;

[0210] FIG. 5 shows how the gain ratio problem can be relaxed if instead of the switching frequency a threshold for an LLC state variable is used;

[0211] FIG. 6 shows an example of AC/DC LLC converter circuit;

[0212] FIG. 7 shows the controller in FIG. 6 in more detail for a single threshold voltage implementation;

[0213] FIG. 8 shows a circuit for controlling the on-transition of a half-bridge in a Voff-Toff control scheme;

[0214] FIG. 9 shows the output of the integrator in FIG. 8;

[0215] FIG. 10 shows the operating range for the circuit of FIG. 8 for a certain set of parameter values;

[0216] FIG. 11 shows waveforms to show unwanted, false triggering in the detection circuitry;

[0217] FIG. 12 shows a circuit with a blanking function to address the problem of false triggering;

[0218] FIG. 13 shows the circuit operation for the circuit of FIG. 12;

[0219] FIG. 14 shows an alternative embodiment to the circuit of FIG. 12 which uses a buffer;

[0220] FIG. 15 shows an LLC power converter connected to the rectified mains, and designed to deliver a high power factor without measurement of the input current;

[0221] FIG. 16 shows the structure of a first PFC control that uses the LLC converter of FIG. 18 in a first known manner, namely using the frequency as the manipulating variable and feeding back the mains current;.

[0222] FIG. 17 shows an approach which uses frequency control but controls the resonant capacitor switching voltage to be proportional to the mains voltage;

[0223] FIG. 18 shows a control implementation including the known approach of feeding back the mains input current but using the capacitor voltage of a self-oscillating LLC;

[0224] FIG. 19 shows an approach that combines the use of the capacitor voltage as the reference signal and self-oscillating switching as used in FIG. 21;

[0225] FIG. 20 shows the capacitor voltage and the threshold voltages;

[0226] FIGS. 21 to 23 show mains current waveforms of a design resulting from the control of FIG. 17 or 19 as well as the set point for the resonant capacitor voltage;

[0227] FIG. 24 shows a modification to the control scheme of FIG. 19, having a correction block;

[0228] FIG. 25 shows an alternative modification to the control scheme of FIG. 17, having a correction block;

[0229] FIG. 26 shows an alternative modification to the control scheme of FIG. 19 having a correction block;

[0230] FIGS. 27 and 28 show the mains current waveforms of a design resulting from the control of FIG. 17 or 19 as modified using the correction approach together with the modifications implemented by the correction functions;

[0231] FIG. 29 shows an approach based on average threshold control;

[0232] FIG. 30 shows an implementation that uses a modified VCO drive signal to implement the approach of FIG. 29;

[0233] FIG. 31 shows a possible set-up of the phase detector used in FIG. 30;

[0234] FIGS. 32 and 33 show timing diagrams to explain the operation of the circuits of FIGS. 29 to 31;

[0235] FIGS. 34 and 35 show waveforms for high voltage and part load operation; and

[0236] FIG. 36 shows a timeout control circuit.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0237] The invention provides various improvements to resonant DC/DC and AC/DC converter circuits, and is of particular interest for LLC circuits which implement power factor correction. Some examples relate to self-oscillating circuits and others relate to converter circuits with frequency control driven by an oscillator.

[0238] A first aspect relates to the use of an LLC resonant converter circuit as an AC/DC converter, and thus functioning as a front end PFC circuit.

[0239] The front end PFC application of an LLC converter poses several problems for the feedback control of the inverter switch arrangement, which cannot be mastered by the conventional frequency control approach. This mainly has to do with the high gain ratio requirements. The gain ratio is the ratio between the maximum and the minimum gain.

[0240] FIG. 2 shows the voltage gain versus the normalized switching frequency for different output powers and FIG. 3 shows the mains input current versus the normalized switching frequency for different input AC voltage levels.

[0241] Problems which arise are: [0242] (i) The extremely high variation of the input current vs. frequency gain, d(im)/d(fs), which can vary over two to three orders of magnitude, compared to the typically less than one order of magnitude gain variation that the LLC control has to cover in case of an LED driver output stage, when controlling the output current. FIG. 2 shows the mains input current versus the switching frequency for unity power factor operation. This plot would correspond to the LLC transfer function if the switching frequency was the manipulating variable. This transfer function varies over a too wide range for using the frequency as the control variable. The gain range further increases if the AC/DC stage has to cover the Intellivolt mains range (108V<V(AC)<305V). [0243] (ii) Setting a minimum frequency in the conventional manner is not possible, which usually sets a maximum power, because unlike the conventional set-up, the minimum frequency does not correspond to the maximum but to the minimum load, as shown in FIG. 3. [0244] (iii) These issues also render impractical the capacitive mode protection that typically comes with LLC frequency control and which requires the setting of a minimum current prior to the switching event, and where the highest load is expected at the lowest frequency.

[0245] FIG. 4 shows the general task of a power factor correction function required by the LLC converter. The left image shows the normalized mains voltage versus the phase angle, and the right image shows the normalized inverse gain versus the switching frequency.

[0246] At a low mains signal (at phase angle t1) a high gain is required (i.e., a low inverse gain (Vmains/Vo) as depicted in right image. The load however is low since for unity power factor, the load is proportional to the square of the input voltage. As a result, the LLC converter is running a light load with an extremely high gain and thus at its minimum switching frequency (fs1).

[0247] When approaching a high mains signal (at phase angle t6) the LLC converter operates at peak load. At this load it is only able to cover a small gain range around the low end of the range. Therefore, the LLC is running at its highest switching frequency (fs6).

[0248] FIG. 5 shows how the gain ratio problem can be relaxed if instead of the switching frequency a threshold for an LLC state variable is used as the manipulating variable for controlling the input current. FIG. 5 shows the mains current versus a threshold switching voltage for three mains AC input voltages (108V, 230V, 305V).

[0249] The threshold voltage in this case is the capacitor voltage vC across the capacitor of the LLC tank. Alternatively, the transformer voltage, or the transformer input current can also be used.

[0250] FIG. 6 shows the AC/DC LLC converter circuit.

[0251] As in FIG. 1, the circuit has an AC mains input 10 followed by a rectifier 12. The switches 28, 30 of the half bridge inverter are controlled by a gate driver 60 which is controlled by a controller 62. The controller outputs a gate drive signal GS.

[0252] The controller is provided with a threshold value which in this example is the threshold (or reference) capacitor voltage vC_ref. The controller 62 receives the measured quantity i.e., the actual resonant capacitor voltage vC, and processes the switching scheme for the gate driver 60 that in turn controls the inverter 28, 30 and the switch node voltage vx, i.e. the voltage at the output of the half bridge inverter.

[0253] The controller is thus a control circuit having an outer control loop 64 for setting a threshold level for the electrical feedback parameter (the capacitor voltage) in dependence on the output voltage vo in this example and the input voltage and current vm, im, and an inner control loop 62 for comparing the electrical feedback parameter with the threshold to derive the gate drive signal.

[0254] The outer control loop 64 implements output control as well as implementing PFC, and the inner control loop 62 derives the switching control signal.

[0255] FIG. 7 shows the controller 62 in more detail. The measured capacitor voltage vC is compared with the reference vC_ref by comparator 70, and the comparison result is used to reset a flip flop 72 which generates the output for the gate driver 60. A delay element 74 provides a delayed set pulse so that the reset operation has a fixed duration (which is a function of the clocking speed of the flip flop).

[0256] This feedback system comprises a high frequency control loop implemented by the inner control loop 62.

[0257] The outer low frequency controller 64 receives the mains voltage vm, the actual mains current im and output voltage vo and its set point vo_ref and processes, in accordance with the power factor needs, the manipulating value of vC_ref for the switching unit.

[0258] In this example, there is only one threshold value (vC_ref) that is compared to a state variable (here vC). If the state variable exceeds the threshold, the flip-flop 72 in the controller 62 is reset and the inverter is switched off via the gate driver, i.e., the switch node voltage is set to its minimum value.

[0259] The inverter is switched on again a certain time after the switch off event. This time adapted to result in a symmetric operation i.e., at a duty cycle of the switch node of 0.5.

[0260] The capacitor voltage is one example of state variable which is used as a control input for the control of the inverter switching. An alternative state variable is the transformer voltage. The scheme is similar but signs have to be changed. For example, if a threshold is exceeded the flip flop 72 in the controller 62 has to be switched on.

[0261] In another scheme, there are two thresholds. The inverter is switched off (on) once the state variable exceeds a first upper threshold and the inverter is switched on (off) if the state variable passes a second threshold. Here, the second threshold is a function of the first threshold and the input voltage.

[0262] In this way, the control circuit is adapted to set a first threshold of the electrical feedback parameter for turning on the gate drive signal and a second threshold of the electrical feedback parameter for turning off the gate drive signal.

[0263] These thresholds are shown in FIG. 20 and discussed further below. One threshold is between the mid-value of the signal vC and the peak value and the other is between the mid-value of the signal vC and the valley value.

[0264] The two threshold values are symmetric with respect to the average value of the signal (vC in this example). The first (upper) threshold is a certain value above the average, and the second (lower) threshold is the same value below the average.

[0265] Thus, in one implementation, there is only one threshold. In another implementation, the inverter is switched off (on) once the state variable exceeds a first upper threshold and the inverter is switched on (off) when the state variable passes a second threshold. The outer control loop can either control the output voltage or the output current with respect to a given set point. For example, for a PFC pre-regulator, the output voltage will be controlled whereas for a single stage driver the output current may be controlled.

[0266] Instead of using a transformer as isolation means as shown in FIG. 6, isolating capacitors may be used as well. For example, by using an extra isolating (e.g. DC blocking) capacitor between the inverter switch node and the transformer, and another between the other primary side winding terminal and the midpoint of the resonant capacitors.

[0267] Alternatively, in order to save components, the resonant capacitors can also be designed for isolating from the mains voltage (y-capacitors). Here the above mentioned state variable (vC) cannot be accessed directly any longer but can be derived by measuring and integrating the current into the isolating capacitors.

[0268] In any of these configurations, the transformer need not to be isolating and can be simplified, depending on the end use of the circuit.

[0269] A second aspect relates to a Von-Ton (or Voff-Toff) drive scheme. As explained above, after a switching event, the switching state is retained for a pre-determined time duration.

[0270] This aspect provides a single threshold together with control based on the duty cycle itself. In this way, the complexity and sensitivity to threshold variations is reduced.

[0271] The duty cycle may be controlled to a defined value that may change dynamically during converter operation.

[0272] For certain types of threshold-based switching scheme, the Von-Voff control has previously been used (as described above as case A). In such a case, two symmetric thresholds are defined for determining the on and off transitions of the half-bridge. However, the duty cycle is extremely sensitive to the exact positioning of the two thresholds. Moreover, even small deviations from 50% of only 1% or 2% can result in strong asymmetries in the output current of 25% or more.

[0273] This aspect is based on integrating a constant value while the controller is waiting for the voltage threshold to be achieved, and then to integrate another constant (with the opposite sign) in order to define the on or off time.

[0274] In a first embodiment, a controller defines the on-transition of the half-bridge in a Voff-Toff control scheme as described above as case C. This is performed via the circuit shown in FIG. 8.

[0275] The circuit comprises an integrator comprising amplifier IC 80 having an amplifier 81 used by the circuit, an integrating capacitor 82 (C19) in a negative feedback loop of the amplifier 81, and an input resistor 84 (R25). The gate driver signal GS is received as input. A buffer IC 86 is at the output, and each IC has decoupling capacitors 88, 90 (C20, C22).

[0276] In order to ensure a 50% duty cycle, the non-inverting input of the amplifier 81 is connected to one-half of the peak value of GS. This is performed via a peak-detector comprising diode 92 (D16), and capacitor 96 (C18), followed by a voltage divider 98 comprised of two resistors 100 (R26) and 102 (R27). Resistor 100 (R26) is slightly smaller than resistor 102 in order to account of the voltage drop across the diode 92.

[0277] There is also a current limiting resistor 94 (R24) in series with the diode 92 as part of the peak detector, which may be eliminated depending on the peak current handling capability of the other components in the circuit.

[0278] At the output of the integrator, a MOSFET 102 couples the output to ground. The transistor 102 is controlled by the gate driver signal GS, via a gate resistor 104 (R29).

[0279] When GS is high, the drain of MOSFET 102 is pulled down, and consequently the output symout is held at a high level (as a result of the inverting buffer 86). When GS transitions to low, this blanking is removed, and an output capacitor 106 (C21) at the output of the integrator begins to charge via a charging resistor 108 (R28). This voltage is then divided down by a divider circuit 110 (of two resistors 112 (R30) and 114 (R31)). in order to achieve a suitable input voltage range for the inverter 86. This voltage divider may not be necessary depending on the voltage range expected on the output of the integrator.

[0280] When the capacitor 106 is sufficiently charged, this triggers the inverting buffer 86 and then the output symout becomes low.

[0281] The other components are bias elements.

[0282] The output of the integrator 80, 82, 84 is depicted in FIG. 9.

[0283] The GS signal reflects the on or off state of the half-bridge. When the GS signal is high, the half-bridge is on, the high side switch is on, the integrator input is high, and the integrator output is decreasing linearly (because of the inverting nature). When the GS signal is low, the half-bridge is off, and the integrator output is increasing linearly.

[0284] In this way, a first constant value is integrated until the electrical feedback parameter reaches a threshold value, and a first time duration during which the integration takes place defines the duration of the GS high signal (which may be an on-time or an off-time of the high side switch or the low side switch). A second constant value of opposite sign to the first constant value is integrated to define a second time duration for setting the subsequent off-time or on-time, respectively. This then determines the duration of the GS low signal.

[0285] The output signal (symout) is usually high, and in this embodiment, the indication that the appropriate time interval has elapsed is provided by a short, low pulse on the symout node.

[0286] In this example of implementation, this symout pulse than signals the end of the GS low signal. The signal symout is the set signal for the flip flop 72 which sets the flip flop high, and the threshold crossing resets the flip flop to low.

[0287] Thus, the duration of the GS high signal is controlled by threshold control, and the duration of the subsequent GS low signal is internally calculated to correspond (if a 50% duty cycle is desired).

[0288] Asymmetric duty cycles may also be implemented by changing the voltage-division factor of the voltage divider 98 with an additional pull-up or pull-down resistor attached to the non-inverting input of the amplifier 81.

[0289] For proper operation, it is important to ensure that the output of the amplifier 81 does not hit its rails for the designed frequency range that the control should work within. If the frequency is too low, the lower rail will be hit, and if the frequency is too high, the upper rail will be hit.

[0290] The operating range is depicted in FIG. 10 for a certain set of parameter values.

[0291] It shows the output of the gate-symmetry integrator as a function of frequency. The solid black curves are for the valley (plot 120), peak (plot 122) and average (plot 124) of the triangular waveform. Plot 122 also corresponds to the effect of delay in the switch-off action. The dashed lines show various asymptotes to the plots 120 and 122.

[0292] At low frequency, the peak of the triangular waveform shown in FIG. 9 saturates at:

[00001]$V_{\mathrm{intpk},\mathrm{LF}}=\frac{V_{\mathrm{ref}}.Math.R.Math..Math.28.Math.C.Math..Math.21.Math.\left(R.Math..Math.30+R.Math..Math.31\right).Math.}{R.Math..Math.25.Math.C.Math..Math.19.Math.\left(R.Math..Math.30+R.Math..Math.31+R.Math..Math.28\right)}+V_t.Math.\frac{R.Math..Math.30+R.Math..Math.31+R.Math..Math.28}{R.Math..Math.31}$

where Vref is the voltage on the non-inverting input of the amplifier 81, and Vt is the threshold voltage that triggers a high-to-low transition on the output of the inverter 86. Typically, the term involving the threshold voltage dominates this expression.

[0293] Note that this expression includes the loading effect of the voltage divider 110 (due to R30 and R31). Simpler expressions result if this divider is not present; however, due to the different supply voltages for the amplifier and inverter, this divider may be necessary. The voltage divider resistors are chosen such that a voltage across the output capacitor 106 that is slightly less than half of the opamp supply will trigger the inverter.

[0294] The time constants associated with resistor 84 (R25) and inverting capacitor 82 (C19) and with the output filter 108 (R28) and 106 (C21) are then chosen to give the proper bandwidth for the control. Resistor 84 and capacitor 82 primarily affect the low-frequency cutoff (where the lower rail of the amplifier is encountered), and resistor 108 and capacitor 106 primarily affect the high-frequency cutoff (where the high rail of the amplifier is encountered).

[0295] The low-frequency cutoff may be approximately computed by solving the equation for the low-frequency asymptote to the plot 120 shown in FIG. 10. Explicitly, this is:

[00002]$V_{\mathrm{ref}}\left(\frac{R.Math..Math.28.Math.C.Math..Math.21.Math.\left(R.Math..Math.30+R.Math..Math.31\right)}{R.Math..Math.25.Math.C.Math..Math.21.Math.\left(R.Math..Math.30+R.Math..Math.31+R.Math..Math.28\right)}-\frac{t_{\mathrm{off}}}{R.Math..Math.25.Math.C.Math..Math.21}\right)+V_t.Math.\frac{R.Math..Math.30+R.Math..Math.31+R.Math..Math.28}{R.Math..Math.31}=0$

[0296] where f.sub.off=(1D)/f.sub.SW, D is the desired duty cycle of 0.5 in this case, and f.sub.SW is a lower bound on the switching frequency. The high-frequency cutoff may be approximately computed by solving the equation for the high-frequency asymptote or by simply plotting the analytic expression for the peak voltage of the triangular waveform shown in FIG. 9.

[0297] If using the asymptote, it is advisable to leave significant headroom as the accuracy of this expression is limited; nevertheless, it is often still sufficient. The asymptotic equation to solve is:

[00003]$V_{\mathrm{ref}}.Math.\frac{t_{\mathrm{off}}}{R.Math..Math.25.Math.C.Math..Math.21}+V_t\left(\frac{R.Math..Math.30+R.Math..Math.31+R.Math..Math.28}{2.Math.R.Math..Math.31}+\frac{R.Math..Math.28.Math.C.Math..Math.21.Math.\left(R.Math..Math.30+R.Math..Math.31\right)}{t_{\mathrm{off}}.Math.R.Math..Math.31}\right)=V_{P.Math..Math.14.Math..Math.V}$

[0298] Other embodiments to this aspect will be apparent to those skilled in the art. For example, symmetry control may be applied to the high or to the low side switch (or to provide a control signal for full-bridge switching), Duty cycles other than 50% may be derived by simple changes to the voltage dividers (98 or 142). There may be other means of deriving the reference signal applied to the non-inverting input of the opamp apart from the peak detector or voltage divider described above.

[0299] The reference signal for the symmetry may also be derived from other waveforms in the circuit (other than the GS signal or the switch node voltage); for example, from the output current, i.e., by comparing the average current through the rectifier diode arrangements 32 and 34, or by assessing the resonant capacitor voltage in terms of comparing its positive and negative peak to the average value.

[0300] A third aspect is directed to the problem that when using threshold detection in a resonant converter, however, the relevant state variable(s) (such as the capacitor voltage used in the example above) may continue to rise (or fall) above (or below) the relevant threshold for some time after the threshold has been reached.

[0301] This aspect relates to an approach by which the relevant state variable may be blanked for some time after the detected threshold crossing in order to avoid unwanted, false triggering in the detection circuitry.

[0302] In order to show this problem, control scheme C (Voff-Toff) is considered where the voltage-threshold is based upon the resonant capacitor voltage, i.e., the voltage across capacitor 26 in FIG. 1 (labeled as node C).

[0303] Some example waveforms are shown in FIG. 11, in particular the resonant capacitor voltage V.sub.C, the output current I.sub.OUT through the diode arrangements 32 and 34 in FIG. 1 and the gate drive signals for the high side transistor (plot 150) and for the low side transistor (plot 152).

[0304] The line 154 in the top plot indicates the voltage threshold, and the arrow 156 in the bottom plot indicates the time-based threshold.

[0305] As may be seen in the top plot, the resonant capacitor voltage continues to increase for some time after the capacitor threshold voltage, and this issue is addressed in this aspect.

[0306] The issue arises in cases where the off-time is sufficiently short such that the on-transition of the half-bridge occurs while the resonant capacitor voltage is still above the threshold. This will lead to an immediate triggering of the off-transition, and is undesired.

[0307] Referring to FIG. 11, a method is used whereby the sensed resonant capacitor voltage V.sub.C is blanked such that the voltage is only detected when the half-bridge is in the appropriate state, and when the slope of the detected voltage has the correct sign (in this case, the slope should be positive). This method also applies to blanking other sensed state variables such as the voltage across the transformer, for example.

[0308] One example is depicted in FIG. 12 for the case of a sensed resonant capacitor voltage V.sub.C (at node C) in the Voff-Toff control scheme. P14V is a local supply voltage which is used to power the control circuitry. This local supply is typically in the 3-25V range.

[0309] The resonant capacitor voltage is input to the circuitry at node C. Since this voltage can be rather high in a resonant converter (hundreds or even thousands of volts), this voltage is divided down by voltage divider 160 (R4 and R6) such that the desired threshold voltage corresponds to a reasonable voltage level detected on the cs node. This node is the positive input of a comparator 162 with its negative input fed by the set point Th for the threshold. Thus, it is the processed voltage vC which is used for comparison with the threshold voltage. By blanking the voltage at node cs, the threshold comparison proceeds as if vC at the blanking voltage.

[0310] When the comparator 162 detects that the threshold has been crossed, it resets the flip flop controlling the half-bridge (for example as shown in FIG. 7).

[0311] If desired, a small offset may be added to this signal via resistor 164 (R3).

[0312] A MOSFET transistor 166 (M1) activates blanking of the cs voltage by shorting this node to ground when blanking is activated. In particular, blanking is activated when the half-bridge, in the Voff-Toff control scheme, is already in the off-state (the signal on GS is low i.e. NOT(GS) is high), which is the low side transistor gate voltage) or when the slope of the resonant capacitor voltage with respect to time is negative.

[0313] In this embodiment, an or function is implemented via diode-logic involving diodes D2, D3 and the pull-down resistor R8.

[0314] R5 and R7 are simply used for current limiting through the diodes and may be omitted if the circuitry can handle the resultant current.

[0315] The slope detection in this circuit is implemented via a slop detection circuit 168. When the slope is positive, there is a current through a capacitor 170 (C1) and diode 172 (D1), and the transistor 174 is in the off-state. A pull down resistor 176 (R2) pulls down the anode of the diode D2, and then the blanking is determined by the state of the half-bridge alone (via GS).

[0316] If the slope is negative, the current through the capacitor 170 will bias the transistor 174 in the on-state, and pull the anode of diode D2 high, which will, in turn, turn on the transistor 166 and pull the node cs low.

[0317] The circuit operation may be seen in FIG. 13. The top plot shows the resonant capacitor voltage, i.e. V.sub.C and the bottom plot shows the signal on node cs.

[0318] When the half-bridge is in the off-state, the cs signal is blanked. It is also evident that the resonant capacitor voltage vC continues to rise for some time after the switching action occurs. In addition, the blanking is not removed until the slope of the resonant capacitor voltage becomes sufficiently positive.

[0319] In this way, the signal cs only tracks the actual voltage vC when vC is approaching the threshold level and from the correct side. For an upper threshold, the voltage vC is increasing towards the threshold. For a lower threshold, the voltage vC is decreasing towards the threshold. Either approach is possible, even though only the example of an upper threshold is given. Because the upper threshold is for turning off the high side switch, it is only need when the high side switch is on.

[0320] Due to delays in the circuitry, the slope detection circuitry (via 170 and 174) may result in blanking occurring just a little bit later than really desired (as may be seen in FIG. 13). For this reason, a resistor 178 (R1) may also be added in order to shift the threshold for the zero slope detection to a new value of (VP14VVdio)/R1, where Vdio is the forward diode drop in diode 172 (which is assumed to be equal to the drop across the base-emitter junction of transistor 174), and the plus or minus signs correspond to the low-to-high and high-to-low transitions in the voltage across resistor 176. Resistor 178 causes the voltage across resistor 176 to make the low-to-high transition a bit early, and the high-to-low transition a bit late. Only the former transition is of key importance for this circuit.

[0321] This approach thus makes use of a detecting circuit 168 for detecting a slope of the electrical feedback parameter and a circuit 166 for disabling the electrical feedback parameter vC in dependence on the slope of the electrical feedback parameter and the level of the gate drive signal GS.

[0322] Other embodiments may be similarly derived using other types of logic gates in order to implement the equivalent of this or function.

[0323] An alternative embodiment uses a buffer in order to derive the slope-detection signal as shown in FIG. 14.

[0324] The same components are given the same references as in FIG. 12. A different slope detection circuit 168 is shown.

[0325] With a positive slope on node C at voltage vC, the current conducts through capacitor 170 and diode 172 as in the circuit of FIG. 12. This pulls the input of an inverter 180 (A1) high. This makes the output of the inverter 180 low, and then the blanking is determined by the state of the half-bridge alone (via GS).

[0326] With a negative slope, the current conducts through capacitor 170 and a diode 182 (D4), pulling the input of inverter 180 low, and the output high. This results in transistor 166 turning on, and the node cs is pulled low. In this case, a resistor 184 (R7) is used to pull up the inverter input in the event of no or low current as the default condition.

[0327] Other embodiments are also possible by considering similar variations corresponding to the Von-Voff and Von-Ton control schemes, variations in the slope detection circuitry, variations in the logic function to drive the gate of transistor 166, variations in the use of NMOS or PMOS MOSFETs, variations in the use of PNP or NPN bipolar transistors, and so on.

[0328] A fourth aspect relates to rendering a high power factor of a resonant PFC LLC circuit without sensing and feeding back the mains input current. It is of particular interest for use of the circuit as a pre-regulating front end, although it can again be employed in a single stage driver.

[0329] Mains input current sensing is associated with extra circuit effort and thus with extra costs and PCB area. Typically a shunt resistor is used for the current measurement which results in power losses.

[0330] Unlike a boost converter (or other buck-derived converters) a resonant LLC converter does not offer an operation like the constant on-time mode to achieve an acceptable power factor without employing a mains current measurement.

[0331] Therefore, a control scheme for the LLC power factor pre-regulator is desired that does not require measuring the input current and still enables a power factor that satisfies e.g. the mains harmonic regulations of EN 61000-3-2.

[0332] The required behavior of a front end power stage, namely to render a (virtually) resistive input impedance i.e., an operation scheme that results in the mains input current being proportional to the mains input voltage, is achieved in this aspect by controlling, in place of the actual mains input current (i_mains), the voltage of the resonant capacitor at the inverter switching instant (vC_off and/or vC_on) to be proportional to the (rectified) mains input voltage (vm).

[0333] When an LLC circuit operates at widely varying input voltages, e.g. at the rectified mains voltage, the converter (if designed correspondingly) shows an input current that is essentially proportional to the resonant capacitor voltage at the inverter switching instants vC_off or vC_on.

[0334] Thus, instead of explicitly controlling (and therefore measuring) the mains current, the voltage vC_off (or vC_on) is controlled (and measured) instead. The advantage is that a voltage measurement takes less circuit effort and is virtually loss-less.

[0335] Non-ideal components of the input current waveform can be further compensated, to approach a unity power factor over a wide input voltage and load range.

[0336] FIG. 15 shows the LLC power converter connected to the rectified mans, and designed to deliver a high power factor. Unlike in the examples described above, the mains current (im) is no longer measured and fed back.

[0337] FIG. 15 corresponds to FIG. 6, and the same reference numbers are used. Compared to FIG. 6, there is a different high frequency inner control loop 62 and a different output control loop 64.

[0338] The outer control loop 64 again processes a difference between a desired output voltage vo_ref and a measured output voltage vo, but it does not receive a measure of the input current.

[0339] Only the output voltage (or current) is controlled explicitly in the outer control loop 64, whereas in the inner control the mains current (im) is implicitly controlled, i.e. by controlling the capacitor switching voltage vC_off (or vC_on) to follow the reference vC_ref that is generated by the outer control loop 64 and that is proportional to the rectified mains voltage (vm) and to the control error (vo).

[0340] FIG. 16 shows the structure of a first PFC control that uses the LLC converter in a known manner, namely using the frequency as the manipulating variable and feeding back the mains current.

[0341] The output voltage error vo is integrated in integrator 190 and multiplied by the prevailing rectified mains voltage vm in multiplier 192 to derive the reference mains current im_ref.

[0342] At unity power factor, the instantaneous mains current is:

im=vm*vm/Rac.

[0343] In the above relation, vm is the instantaneous mains voltage and Rac is the equivalent mains resistance that depends on the load and the mains rms value Vac (e.g. Vac=240Vrms). The mains resistance can be written as

Rac=Vac*Vac/Pac.

[0344] In the above relation, Pac is the rms value of the power taken by the converter. The mains current can thus be expressed by:

im=vm*Pac/(Vac*Vac)

[0345] The integrated control error is representative for the term Pac/(Vac*Vac), which is generated by the outer control loop. The product of that term with vm represents the instantaneous reference value for the mains current (im).

[0346] In a digital implementation using e.g. a micro control unit, these parameters are represented by register values whereas voltages are most convenient in an analog PF control.

[0347] The reference mains current is provided to a frequency control unit 194 which integrates a current error using integrator 196 to provide frequency control of a voltage controlled oscillator 198.

[0348] FIG. 17 shows an approach relating to this aspect which also uses frequency control but controls the resonant capacitor switching (or threshold) voltage to be proportional to the mains voltage (vm). This approach also implements an average threshold control, as explained below in a fifth aspect.

[0349] The output voltage error vo is integrated in integrator 200 and multiplied by the current mains voltage vm in multiplier 192 202 to derive a reference capacitor voltage vC_ref. Thus, the feedback system uses the capacitor voltage as the feedback parameter.

[0350] The reference capacitor voltage is provided to a frequency control unit 204 which integrates an error signal using integrator 206 to provide frequency control of a voltage controlled oscillator 208. The error signal is representative, but not a measure of, a current error. The feedback loop comprises a sample and hold unit 209 for sampling the capacitor voltage at the switching instants. There may be one or two sampled value of vC per cycle.

[0351] This approach avoids the need for mains current measurement but still uses frequency control.

[0352] FIG. 18 shows a control implementation which also feeds back the mains input current. The control however makes use of the self-oscillating switching approach described above, in which the parameter which determines the control is the capacitor voltage.

[0353] It can be seen that this control approach makes use of a single threshold control value. The control may thus be implemented as explained with reference to FIG. 7, and it may use the timing approach explained with reference to FIGS. 8 to 10.

[0354] The first stage 190, 192 is as in FIG. 16, and the difference current is again integrated in unit 196. However the output is a reference capacitor voltage vC_ref, which is then compared with the capacitor voltage vC by comparator 210. This then controls a set and reset flip flop (as described above with reference to FIG. 7), instead of controlling an oscillator.

[0355] In FIG. 19 an approach is shown that combines the use of the capacitor voltage as the reference signal vC_ref instead of having input current measurement. This provides an even simpler circuit.

[0356] FIG. 20 shows the capacitor voltage vC and the threshold (or switching) voltages vC_on and vC_off, i.e. the voltage vC at the inverter switching instant.

[0357] The time at which the capacitor voltage is sampled is the two switching instants of the node X, as shown in FIG. 20.

[0358] For a high power factor, the PFC circuit has to emulate a constant AC-resistance (Rac0) that only depends on the mains voltage amplitude (Vm_pk) and the load (Po) divided by the power efficiency () of the converter:

Rac0=Vm_pk.sup.2/(2 Po/)=const.

[0359] When operating the LLC in as described above, the actual AC-resistance can be expressed as:

Rac=1/(fs Cs(2 vC_off/vm1)),

[0360] This is a function of the switching frequency (fs), the resonant capacitor Cs, its voltage at the switching instant (vC_off) and the instantaneous rectified mains voltage (vm). The control keeps the ratio of vC_off and vm constant. For a given converter design, this ratio only depends on the load. In the course of a mains cycle, however, the frequency varies, which principally results in a non-uniform power factor and which depends on the converter design and its operation in terms of the mains voltage amplitude and the load.

[0361] FIGS. 21 to 23 show on the left the mains current waveforms of a design resulting from the control of FIG. 17 or 19 (with the control of vC) for various input voltages. FIG. 21 is for 108V(AC), FIG. 22 is for 230V(AC) and FIG. 23 is for 305V(AC).

[0362] The solid line in the left images is the mains current as resulting from the control according to the invention. The dashed line is the rectified mains current for unity power factor (i.e. a perfect, rectified sine).

[0363] The right graph in each case shows that the set point for the resonant capacitor voltage (vC_ref, y-axis) at which switching of the inverters switches is triggered is adapted to be proportional to the mains voltage (vm, x-axis).

[0364] The corresponding total harmonic distortions (THDs) are 2.5%, 10.5% and 19.3%.

[0365] A fifth aspect builds upon the approach above of FIGS. 15 to 20 (without mains current sensing), to render a higher power factor of the resonant PFC LLC. This provides a further improvement of the power factor in order to overcome the non-unity power factor resulting from the above described approach (i.e. using the resonant capacitor switching voltage in place of (or to represent) the mains current. The approach is based on compensating for the errors that depend on the instantaneous mains voltage, the peak mains voltage and on the load (Po).

[0366] FIG. 24 shows a modification to the control scheme of FIG. 19, in which after the reference capacitor voltage vC_ref is obtained, a correction is applied as shown by block 270 before the comparison step in block 70. The correction is thus inserted into the capacitor reference path.

[0367] FIG. 25 shows a modification to the control scheme of FIG. 19 in which before the reference capacitor voltage vC_ref is obtained by the multiplier 192, a correction is applied to the measured mains voltage vm as shown by block 280. The correction is thus inserted into the mains voltage measurement path.

[0368] FIG. 26 shows an alternative modification to the control scheme of FIG. 19, in which the measured capacitor voltage vC is subjected to a correction in block 290, depending on the measured mains voltage vm, before the corrected capacitor voltage vC_cor is compared with the reference vC_ref in the comparator 70. The correction is thus inserted into the capacitor voltage feedback path.

[0369] FIGS. 27 and 28 show on the left the mains current waveforms of a design resulting from the control of FIG. 17 or 19 as modified using the correction approach described above. FIG. 27 is for 230V(AC) and FIG. 28 is for 305V(AC).

[0370] The right graphs in FIGS. 27 and 28 show the modifications implemented by the correction functions.

[0371] They show that the set point for the resonant capacitor voltage (vC_ref, y-axis) at which switching of the inverters switches is triggered is no longer proportional to the mains voltage (vm, x-axis). The effect of the correction is to slightly increase the gain (i.e. the slop of the curve shown) d(vC_ref)/d(vm) at lower and medium mains voltages with an amplitude that increases with the mains voltage amplitude (vC_pk). The gain decreases for higher mains voltages so that the reference set point is the same at the maximum mains voltage. Thus, the proportional line is bowed towards a higher reference voltage vC_ref.

[0372] The resulting harmonic distortion of the mains current can be reduced to below 4%. The total harmonic distortions (THDs) are 2.5% and 3.5% for FIGS. 27 and 28 respectively.

[0373] A sixth aspect provides a further alternative switching control approach.

[0374] A self-oscillating, switching threshold control for the LLC-PFC has been described above to overcome problems that the conventional frequency control (whereby the switching frequency is the manipulating value) of the LLC as DC/DC converter turns out to be impractical in the case of the LLC-PFC circuit, namely as an AC/DC converter. Approaches described above make use of a switching threshold (for example of the resonant capacitor voltage) in order to control the mains current without measuring it.

[0375] It is known that a self-oscillating control scheme can be applied to symmetrically and asymmetrically operate resonant DC/DC converters (U.S. Pat. No. 8,729,830B2). It is also known that the capacitor voltage can be used as a feedback signal to improve the frequency control of a symmetrically operating, resonant LLC or LCC converter, for balancing the output current (U.S. Pat. No. 6,711,034B2), and for compensating the gain variation at high-load operation (US2007/0171679A1).

[0376] This sixth aspect addresses stability issues related to the control of the AC/DC power conversion with a resonant LLC converter and provides an alternative to the self-oscillating threshold control scheme described above.

[0377] This aspect relates to the general architecture shown in FIG. 6 or FIG. 15 described above, which shows the LLC converter used as an AC/DC converter. The output voltage (vo) is controlled in an outer control loop, or alternatively, the output current. The input current is controlled to implement power factor correction.

[0378] FIG. 29 shows an implementation in schematic form. It is shown as a modification to the approach of FIG. 16 and the same components as in FIG. 16 are given the same reference numbers. In this example, the input current im is used as a controlled variable (as in FIG. 6), which is then used to derive the vC_ref signal (in the manner explained with reference to FIG. 18). The threshold voltage vC_off (shown in FIG. 20) is explicitly controlled, but this is not performed in a cycle-by cycle-manner but averaged in time. Thus, there is average threshold control as shown by unit 320.

[0379] The average threshold control unit 320 receives the reference threshold value (vC_ref) and the measured value vC and generates the gate drive signal GS.

[0380] FIG. 30 shows an implementation which does not use input current measurement and therefore suitable for the circuit of FIG. 16. The output signal GS is generated by a local oscillator 198. This implementation for PFC uses the simplified mains current control (of FIG. 19) and additionally uses an oscillator.

[0381] The system can be implemented using standard power factor controller ICs.

[0382] The phases of the VCO output signal (i.e. the signal GS provided to the gate driver 60) are compared with the resonant capacitor voltage vC by means of a phase detector 322.

[0383] FIG. 31 shows a possible set-up of the phase detector 322 in more detail.

[0384] The multiplier 192 of the outer control loop of the PFC control outputs the reference signal vC_ref proportional to the integrated output voltage error and to the mains voltage vm. The capacitor voltage vC is compared with the reference vC_ref (which in this example is vC_off) by comparator 330, which generates the reset signal for a flip-flop 332. If the resonant capacitor voltage vC exceeds the reference, the flip flop 332 is reset, and it is set again at the next rising edge of the VCO output GS.

[0385] The resulting phase error signal (DH or DL) is integrated by integrator 196 to create the error signal which controls the VCO.

[0386] In these examples, the control circuit comprises an outer control loop 190, 192 for setting a threshold level in dependence on the output voltage or current and the input voltage, and an inner control loop comprising an oscillator 198 for generating the gate drive signal, wherein the oscillator frequency is controlled by the inner control loop in dependence on the threshold level vC_ref and on the electrical feedback parameter vC. This provides an average threshold control scheme. It overcomes stability issues of direct or cycle-by-cycle threshold schemes, but maintains the advantages of threshold control in terms of relaxing the gain ratio problem associated with the frequency control.

[0387] FIG. 32 shows signals of the phase detector for an implementation example in case of a transient resulting in an (initially) too low frequency of the VCO.

[0388] FIG. 33 shows signals of the phase detector for an implementation example in case of a transient resulting in an (initially) too high frequency of the VCO.

[0389] In FIG. 32, a too high frequency of the VCO can be a result of a transient event like a load step or during start up. The threshold vC_ref causes resetting of the flip-flop 332 whereas it is set by the VCO output signal GS. This signal always has a constant duty cycle (here 50%). Now, the case is detected when the output of the flip-flop 332 (Q_FF) is low and GS is (still) high. This detection signal (DH) is used to forms the VCO input voltage and thus results in an increased frequency, which at the second event of FIG. 32 already has led to a reduced phase error, and which vanished at the third event.

[0390] FIG. 33 shows the inverted case of an initially too high frequency, which is sensed in corresponding manner in terms of a signal DL that causes the VCO input voltage to decrease.

[0391] These waveforms are simply for illustration. The output signal of the low side gate driver for example can also be used (e.g. in the absence of signal GS), which is inverted with respect to GS. Also other means to form the phase error than the implied logic gates can also result in the desired VCO control voltage. Further possible is a completely digital implementation using a micro controller unit.

[0392] The phase detector 322 can be configured to result in the half-bridge switching action before, at, or after the actual threshold crossing for example by a slight offset to the error integrator in order to cope with delays and to achieve the desired control performance.

[0393] The VCO can further be manipulated in order to run asymmetrically, i.e., at a duty cycle below or above 50%.

[0394] FIGS. 34 and 35 show waveforms which form high voltage and part load operation (305V(AC) at 20% of the rated load) of a converter that is designed to handle 108V (AC) to 305V (AV). FIG. 34 shows waveforms without duty-cycle modification resulting in a switching frequency of 312 kHz. FIG. 35 correspond to the same operation point but at a duty-cycle of 10% instead of 50% and result in a reduced switching frequency of 125 kHz.

[0395] A seventh aspect relates to stability issues.

[0396] When using the threshold detection schemes described above in a resonant converter, the relevant state variable(s) (vC in the main examples) may fail to achieve the desired threshold, and hence the converter may stop oscillating. This may occur at an initial startup or during operation, e.g., in connection with mains dips, load steps or during light load operation.

[0397] This aspect relates to a method whereby the threshold for the state variable is reset to a low value if a sufficiently long time elapses without any switching action in the inverter half-bridge.

[0398] For this purpose, during startup or if the state variable does not reach the desired threshold for some reason, a timeout condition is triggered which immediately lowers the threshold to zero so that switching may begin again.

[0399] An example of one embodiment of such a timeout circuit is shown in FIG. 36. The state of the half-bridge is indicated by the gate drive signal GS. As in the examples above, GS is high if the half-bridge is high, and is low otherwise. The control is for example based on an integration of the error in the output voltage which the controller is trying to regulate, shown as OUT in FIG. 36.

[0400] In the examples above, this signal is the output voltage (or current). However, this timeout aspect is more general, and hence the signal used as the control parameter is generally termed OUT in FIG. 39, and the reference (which is vo_ref in FIG. 6 for example) is generally termed Vref in FIG. 36.

[0401] The circuit comprises an integrator 390 (formed of input resistor 392 (R37), integrating capacitor 394 (C4) and amplifier 396). The output integrated comparison signal COMP, or some function of the signal COMP, defines the desired threshold value.

[0402] The threshold is generated by the product of the signal COMP and the instantaneous, rectified mains voltage (vm). COMP is the signal at the output of the integrator block for example as shown in FIG. 16 as unit 190.

[0403] The oscillation is restarted if too much time has elapsed since the last positive edge on the signal GS. For the restart, the target value of the threshold is reset (i.e., set to zero) in order to ensure a subsequent threshold crossing and thus re-initiating the oscillation. In particular, this aspect provides a timeout circuit for overriding the threshold if switching of the gate drive signal fails thereby to provide a restart signal for restarting switching of the gate drive signal.

[0404] In this example, the restart is implemented by shorting out the feedback capacitor 394. This is achieved via a MOSFET 398 which discharges the capacitor through a resistor 400 in order to keep current limited to reasonable values. In practice, the resistor 400 may be omitted if the other components are able to handle the resultant current.

[0405] The rising edges on the signal GS are detected via a detection circuit 402 (C23, D17, and D18). Each rising edge serves to charge a capacitor 404 (C25) by a small amount. In addition, there is a slow discharge via a discharge resistor 406 (R32) and in normal operation via the base of transistor 408 through the base resistor (R33).

[0406] In normal operation, the charging action exceeds the discharging action, and the voltage across the capacitor 404 is enough to maintain transistor 408 in the on-state. In turn, this keeps the transistor 398 in the off-state. If too much time elapses between rising edges on the signal GD, eventually the capacitor 404 will discharge to the point at which the transistor 408 finally turns off. This will pull the gate of transistor 398 up via pull up resistor 410 (R34), and capacitor 394 will be discharged. The voltage threshold for the capacitor voltage then reduces to near-zero, so the converter will begin operation once again.

[0407] The capacitor 412 (C24) provides a reset each time the supply, P14V, is ramped up.

[0408] Other embodiments may be realized by detecting negative edges on the signal GD, detecting both edges on GD or using a more complicated feedback network between the inverting input of the amplifier 396 and the output signal COMP but where the integration part is still shorted out at timeout.

[0409] The restart may be adapted to occur recurrently in the case of a light load or standby operation. In these cases, there will be expected times at which the oscillation will stop, and then the timeout will provide a means to enter a type of burst mode operation, i.e., the energy is delivered during the first switching periods after the restart until eventually a threshold is missed, and then oscillation will only begin again once the timeout is triggered (due to sufficiently re-charging the buffer). In this mode, the time constant of the timeout determines the bursting frequency.

[0410] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word comprising does not exclude other elements or steps, and the indefinite article a or an does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.