High dynamic range device for integrating an electrical current

Abstract

A device for integrating an electric current during a period T.sub.int, including an operational amplifier and a capacitor connected between a first input and an output of the amplifier, a second input of the amplifier being taken to a voltage VBUS, output voltage V.sub.out of the amplifier being saturated at a high voltage V.sub.satH and a low voltage V.sub.satH according to the charge quantity in the capacitor. The device also includes: a circuit for switching the terminals of the capacitor; and a circuit for triggering the circuit at least once during period T.sub.int when voltage V.sub.out both grows and is substantially equal to a reference voltage VREF, the voltage VREF being smaller than or equal to voltage V.sub.satH, and reference voltage VREF and voltage VBUS being selected to comply with relation 2.Math.VBUS?VREF?V.sub.satL; and a storage circuit for storing the number of triggerings having occurred between the initial time and the end time of the integration period.

Claims

1. A device for integrating an electric current received on an integration node for a period of predetermined duration T.sub.int, comprising an operational amplifier having a first and a second input and an output, and a capacitor having two terminals connected between the first input and the output of the operational amplifier, the second input of the amplifier being taken to a constant voltage VBUS, the first input of the amplifier being connected to the integration node, and the output terminal of the operational amplifier supplying an output voltage V.sub.out which varies monotonously in a predetermined variation direction according to a quantity of electric charges of predetermined polarity stored in the capacitor, output voltage V.sub.out of the operational amplifier being saturated at a high saturation voltage V.sub.satH when the quantity of electric charges of said polarity stored in the capacitor is greater than a predetermined threshold, and output voltage V.sub.out of the operational amplifier being saturated at a low saturation voltage V.sub.satL when the quantity of electric charges of said polarity stored in the capacitor is smaller than a predetermined threshold, wherein the device further comprises: a circuit for switching the capacitor terminals between a first position in which a first terminal of said capacitor is connected to said first input of said operational amplifier and a second terminal of said capacitor is connected to said output of said operational amplifier; and a second position in which said first terminal of said capacitor is connected to said output of said operational amplifier and said second terminal of said capacitor is connected to said first input of said operational amplifier; a circuit for triggering the switching circuit at least once during integration period T.sub.int when output voltage V.sub.out of the operational amplifier both varies in said variation direction and is substantially equal to a reference voltage VREF; and a storage circuit for storing the number of triggerings having occurred between the initial time and the end time of the integration period, and wherein: when said variation direction is increasing, said reference voltage VREF is smaller than or equal to high saturation voltage V.sub.satH, and reference voltage VREF and voltage VBUS of the second input of the operational amplifier are selected to comply with relation
2.Math.VBUS?VREF?V.sub.satL; or when said variation direction is decreasing, said reference voltage VREF is greater than or equal to low saturation voltage V.sub.satL, and reference voltage VREF and voltage VBUS of the second input of the operational amplifier are selected to comply with relation
2.Math.VBUS?VREF?V.sub.satH.

2. The electric current integration device of claim 1: wherein the switching circuit comprises: a first controllable switch connected between the first input of the operational amplifier and the first terminal of the capacitor; a second controllable switch connected between the output of the operational amplifier and the second terminal of the capacitor; a third controllable switch connected between the first input of the operational amplifier and the second terminal of the capacitor; a fourth controllable switch connected between the output of the operational amplifier and the first terminal of the capacitor, and wherein: the first and the second controllable switches are controlled by a first binary control signal HDinv; the third and the fourth controllable switches are controlled by a second binary control signal HDinv, the second binary signal HDinv being the complement of first binary signal HDinv.

3. The electric current integration device of claim 1, wherein the triggering circuit comprises a comparator having a first input connected to the output of the operational amplifier and a second input connected to the reference voltage VREF, the comparator generating a first voltage on an output when the voltage on its first input is lower than the voltage on its second input, and generating a second voltage, different from the first voltage, on the output when the voltage on its first input is greater than the voltage on its second input, so that a condition necessary for the triggering of the switching circuit implemented by the triggering circuit is fulfilled: on switching from the first voltage to the second voltage if said variation direction is increasing; or on switching from the second voltage to the first voltage if said variation direction is decreasing.

4. The electric current integration device of claim 1, wherein the triggering of the switching of the capacitor implemented by the triggering circuit comprises fulfilling at the same time: a first sub-condition according to which output voltage V.sub.out of the operational amplifier varies in said variation direction and is substantially equal to the reference voltage VREF; and a second sub-condition according to which the number of times when the first subcondition has been fulfilled from the initial time of integration period T.sub.int is shorter than a predetermined maximum number.

5. The electric current integration device of claim 4, wherein the triggering circuit comprises a binary counter over n bits having a counting input connected to the output of the comparator and an output supplying the number of times from the initial time of integration period T.sub.int where the output of the comparator switches from the first voltage to the second voltage when said variation direction is increasing or switches from the second voltage to the first voltage when said variation direction is decreasing.

6. The electric current integration device of claim 2, wherein the triggering circuit comprises a signal generator connected to the output of the binary counter and switching the first and second binary control signals HDinv, HDinv of the switches when the output of the binary counter is incremented.

7. The electric current integration device of claim 5, wherein the triggering circuit comprises a signal generator connected to the output of the binary counter and switching the first and second binary control signals HDinv, HDinv of the switches when the output of the binary counter is incremented.

8. An electromagnetic radiation detection system comprising: a detection element generating on an output terminal an electric current according to the electromagnetic radiation; and the device of claim 1, the first input of the operational amplifier being connected to the output terminal of the detection element for the integration of the current generated by the detection element.

9. The electromagnetic radiation detection system of claim 8, wherein the detection element comprises: a detection branch comprising a detection bolometer having a membrane suspended above a substrate and a bias circuit for setting the voltage across the detection bolometer according to a voltage set point; a compensation branch comprising a compensation bolometer substantially taken to the substrate temperature, and a bias circuit for setting the voltage across the compensation bolometer according to a voltage set point; and means for forming the difference between current i.sub.sc running through the detection bolometer and current i.sub.cm running through the compensation bolometer to form the electric current to be integrated.

10. A method of integrating an electric current during a predetermined integration duration T.sub.int in a capacitor having two terminals connected between a first input and the output of an operational amplifier, the operational amplifier comprising a second input taken to a constant voltage VBUS, output voltage V.sub.out of the operational amplifier varying monotonously in a predetermined variation direction according to a quantity of electric charges of predetermined polarity stored in the capacitor, said output voltage V.sub.out being saturated at a high saturation voltage V.sub.satH when the quantity of electric charges stored in the capacitor is greater than a predetermined threshold, and output voltage V.sub.out of the operational amplifier being saturated at a low saturation voltage V.sub.satL when the quantity of electric charges of said polarity stored in the capacitor is smaller than a predetermined threshold, the method comprising the steps of: a) before the initial time of integration period T.sub.int, initializing to zero the capacitor charge and a counting value; b) integrating during integration period T.sub.int the electric current in the capacitor; c) switching the capacitor terminals at least once during integration period T.sub.int when the output voltage of the operational amplifier both varies in said variation direction and is equal to a predetermined reference voltage VREF, said switching occurring between a first position, in which a first terminal of said capacitor is connected to said first input of said operational amplifier and a second terminal of said capacitor is connected to said output of said operational amplifier, and a second position, in which said first terminal of said capacitor is connected to said output of said operational amplifier and said second terminal of said capacitor is connected to said first input of said operational amplifier, when said variation direction is increasing, said reference voltage VREF being smaller than or equal to high saturation voltage V.sub.SatH, and reference voltage VREF and voltage VBUS of the second input of the operational amplifier are selected to comply with relation
2.Math.VBUS?VREF?V.sub.satL; or when said variation direction is decreasing, said reference voltage VREF is greater than or equal to low saturation voltage V.sub.satL, and reference voltage VREF and voltage VBUS of the second input of the operational amplifier are selected to comply with relation
2.Math.VBUS?VREF?V.sub.satH; d) incrementing by one the counting value after each switching of the capacitor during integration period T.sub.int; and e) after the end time of integration period T.sub.int, supplying the counting value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will be better understood on reading of the following description provided as an example only in relation with the accompanying drawings, where the same reference numerals designate the same or similar elements, among which:

(2) FIG. 1 is an electric diagram of an infrared bolometric detector of the state of the art comprising CTIA-type integrators for the measurement of the currents generated by the detection elements, already described hereabove;

(3) FIG. 2 is an electric diagram illustrating the reading out of a sensitive bolometer of the detector of FIG. 1 by means of a compensation structure;

(4) FIG. 3 is an electric diagram of an electric current integration device according to the invention;

(5) FIGS. 4A-C show a timing diagram illustrating the output signal of the integration stage and signals for resetting the device of FIG. 2; and

(6) FIGS. 5A-B show a timing diagram illustrating an extension of the read-out dynamic range of the device of FIG. 3 in the context of a use of this device as an integration device of an array detector.

DETAILED DESCRIPTION OF THE INVENTION

(7) Referring to FIG. 3, an integration device 60 according to the invention comprises a CTIA-type integrator comprising an operational amplifier 62 and a signal capacitor 64, of fixed capacitance C.sub.int, connected between the inverting input and the output of amplifier 62. The non-inverting input (+) thereof is connected to a constant positive voltage VBUS and the inverting input (?) is connected to the input or integration node E conducting an electric current I to be integrated.

(8) A switch 66, driven by a signal HDraz, is also provided in parallel with capacitor 64, for the discharge thereof, and thus its resetting.

(9) Device 60 is completed with a sample-and-hold circuit 68 connected at the output of operational amplifier 62 to sample and hold voltage V.sub.out at the output thereof.

(10) In addition to the above-described CTIA integrator, device 60 is completed with circuits 70 of automatic extension of the read-out dynamic range of the CTIA 62, 64. Circuit 70 comprises: a circuit 72 inverting the direction of the connection of capacitor 64 across operational amplifier 62 on reception of a control signal HD[2:0]; a circuit 74 detecting a switching condition of capacitor 64 according to output voltage V.sub.out of amplifier 62 and generating control signal HD[2:0]; and a circuit 76 storing the number of switchings of capacitor 64.

(11) Switching circuit 72 comprises: a first controllable switch 78 connected between the inverting input (?) of amplifier 62 and a first terminal 80 of capacitor 64, the first switch being driven by a first control signal HDinv; a second controllable switch 82 connected between output 84 of amplifier 62 and a second terminal 86 of capacitor 64, the second switch being driven by first control signal HDinv; a third controllable switch 88 connected between the inverting input (?) of amplifier 62 and second terminal 86 of capacitor 64, the third switch being driven by a second control signal HDinv; a fourth controllable switch 90 connected between output 86 of amplifier 62 and first terminal 80 of capacitor 64, the fourth switch being driven by second control signal HDinv; and a phase generator 92 receiving control signal HD[2:0] and generating control signals HDinv and HDinv as a function thereof.

(12) In particular, signals HDinv and HDinv are in phase opposition. For example, these signals are binary signals which are logic complements of each other. Thus, the first and second switches 78, 82, which have the same state, are off while the third and fourth switches 88, 90, which have the same state, are on, and vice versa. Two connection states of capacitor 64 are thus defined, that is: a first state having first and second terminals 80, 86 of capacitor 64 respectively connected to node E and to output 84 of amplifier 62, and a second state having first and second terminals 80, 86 of capacitor 64 respectively connected to output 84 of amplifier 62 and to node E.

(13) The switching of signal HDinv, and thus of signal HDinv, accordingly causes the inversion of the connection state of capacitor 64, that is, the switching thereof.

(14) Phase generator 92 also generates signal HDraz driving switch 66 for resetting capacitor 64 according to an initialization control signal RAZ as explained hereafter.

(15) Phase generator 92 also implements a function of activation and deactivation of the automatic extension mode of the read-out dynamic range according to a mode selection signal HD_MODE_ON, in a way which will also be described hereafter.

(16) Detection circuit 74 comprises: a comparator 94 receiving on a first terminal (+) output voltage V.sub.out of amplifier 62 and, on a second terminal (?) a reference voltage VREF greater than voltage VBUS and smaller than or equal to high saturation voltage V.sub.satH of the CTIA. Comparator 94 outputs a voltage S.sub.comp having a first value when voltage V.sub.out is smaller than voltage VREF, and having a second value, different from the first value, when voltage V.sub.out is greater than or equal to voltage VREF. In particular, the switching of voltage S.sub.comp from the first value to the second value means that voltage V.sub.out is increasing and has just crossed reference voltage VREF; a binary counter 96, having its counting input connected to the output of comparator 94. The binary counter is for example designed to count the rising pulse edges, the second voltage value of the comparator being then selected to be greater than the first voltage value. Counter 96 has a predetermined number of bits, for example 4, and receives on an initialization terminal initialization signal RAZ for its resetting. Further, counter 96 is configured to be blocked once its maximum value has been reached. Finally, the output signal of binary counter 96, which is for example delivered on 3 outputs in parallel, an output being provided for each bit of the counter, supplies control signal HD[2:0] of phase generator 92.

(17) Storage circuit 76 is for example formed of an asynchronous LATCH-type asynchronous digital memory, which receives the counter value contained in signal HD[2:0] and holds this value in its output signal HDsh[2:0]. Storage circuit 76 and sample-and-hold circuit 68 are driven by the same sampling signal FSH to keep at the output the signals received as an input.

(18) Finally, integration device 60 according to the invention advantageously comprises an autozero circuit 98 connected to the inverting input (?) of amplifier 62, to cancel the offset of amplifier 62 and the low-frequency noise thereof as known per se, and for example described in document IEEE journal of solid-state circuits, vol sc-20, n? 3, June 1985.

(19) The operation of device 60 will now be described in relation with FIGS. 4A-C.

(20) Before starting a phase of integration of an electric current I (phase A), signals HDraz and HDinv are activated to the high state by generator 92 on reception of a predetermined value of control signal RAZ, complemented signal HDinv being thus also taken to the low state by generator 92. Switches 66, 78, and 82 are thus in their on state, switches 88, 90 are in their off state, and outputs HD[2:0] of counter 96 are set to the low state. The turning on of switch 66 discharges capacitor 64, and after this resetting, output voltage V.sub.out is equal to VBUS. Voltage VREF being greater than voltage VBUS, the output of comparator 94 is thus set to its lowest value. During this initialization phase, during which signal HDraz is activated to the high state, autozero system 98 is also implemented as known by those skilled in the art.

(21) Control RAZ is then released, generator 92 triggers the turning off of switch 66 and keeps the state of signals HDinv and HDinv. The turning off of switch 66 thus marks the beginning of the phase of integration of current I received as an input (phase B), autozero system 98 is active to subtract the offset at the input of amplifier 62 during the entire integration phase. Generator 92 and switch 66 thus form an initialization circuit of the device which determines the time of the beginning of the integration period from the falling edge of signal RAZ to the rising edge of signal RAZ which marks the end time of the integration period. Due to the integration, voltage V.sub.out at the output of amplifier 62 increases from value VBUS (phase B1).

(22) If during the entire integration phase of duration T.sub.int, voltage V.sub.out remains smaller than reference voltage VREF, no new logic condition appears at the output of binary counter 96. The operation of device 60 is then identical to that of a CTIA of the state of the art, such as described in relation with FIGS. 1 and 2, and output signal HD[2:0] thus remains in the low state.

(23) However, if during the integration phase, output voltage V.sub.out reaches or exceeds value VREF, output S.sub.COMP of comparator 94 switches state, which propagates the high state at the comparator output to the input of the clock of binary counter 96, which then activates least significant bit HD0 to 1. One then has HD[2:0]=001.

(24) The switching of a bit of signal HD[2:0] from the low state to the high state is detected by phase generator 92. As a response, the latter switches control signals HDinv and HDinv respectively to the low state and to the high state. This results in the switching of the connections of capacitor 64 between amplifier 62 and autozero circuit 98.

(25) At the time when condition V.sub.out=VREF is fulfilled, the quantity of electric charges Q stored in capacitor 64 is equal to:
Q=C.sub.int.Math.(VREF?VBUS)(2)

(26) After the switching of capacitor 64, load Q across the CTIA has a reverse biasing with respect to that discussed before the switching, so that the output of amplifier 62 is equal to:
V.sub.out=2.Math.VBUS?VREF(3)

(27) The output of comparator 94 then switches to the low state since voltage V.sub.out is smaller than reference voltage VREF. The switching of capacitor 64 then takes the output of amplifier 62 to a lower level. To avoid saturating the CTIA, voltage VBUS and voltage VREF are selected to fulfill relation:
2.Math.VBUS?VREF?VsatL

(28) For example, voltage VBUS is adjusted above, and advantageously at the central point of the linear dynamic range of the CTIA, voltage VBUS thus complying with relation:

(29) $\mathrm{VBUS}?\frac{V_{\mathrm{satL}}+V_{\mathrm{satH}}}{2}$

(30) Beyond this time, the integration phase carries on (phase B2), the output of amplifier 62 resuming its growth in the linear read-out dynamic range, with no information loss.

(31) If output V.sub.out of amplifier 62 reaches or exceeds again value VREF before the end of the integration, output S.sub.COMP of comparator 94 changes polarity again and increments counter 96 once again. The binary output thereof is then set to HD[2:0]=010.

(32) On reception of the switching of a bit of signal HD[2:0], generator 92 switches signals HDinv and HDinv, in the present case respectively in the high state and the low state, which causes the switching of capacitor 64. Electric load Q across the CTIA has, again, a reverse biasing with respect to that discussed before the switching, and the output of amplifier 62 is thus taken to V.sub.out=2.Math.VBUS?VREF and the output of comparator 94 switches to the low state since V.sub.out<VREF. A new phase of growth of output V.sub.out from value 2.Math.VBUS?VREF is then implemented (phase B3). The capacitor can thus switch repeatedly with no information loss all the way to the maximum value of binary counter 96, as an example here over 3 bits, that is, maximum value HD.sub.SH[2:0]=111.

(33) Once integration duration T.sub.int has elapsed, output voltage V.sub.out (T.sub.int) is sampled and held in sample-and-hold device 68 by the sending of a pulse for signal FSH, as in the conventional integration mode, while the binary values of signal HD[2:0] are also stored in a latch-type memory stage 76 on reception of the pulse of the same signal FSH. Device 60 thus supplies at the end of an integration phase a signal HD.sub.SH[2:0] representing the number of switchings of capacitor 64 as well as voltage V.sub.outSH equal to the voltage at the output of amplifier 62. Signal FSH is for example activated to the high state by a circuit for managing the digital control signals (not shown) for a short period just before the end of the integration, that is, before the rising edge of signal RAZ, as indicated in FIGS. 4B and 4C which also specify the times of beginning and end of the integration period. Other mechanisms for adjusting the times of beginning and end of the integration period are of course possible.

(34) Capacitance C.sub.int of stage CTIA and the binary counter can then be reset by activation of control signal RAZ before a new integration cycle, as previously indicated.

(35) In the end, the total voltage V.sub.out.sup.final corresponding to the electric charges integrated by CTIA 62, 64 during the integration phase is thus equal to:
V.sub.out.sup.final=V.sub.outSH+2.Math.conv.sub.10(HD.sub.SH[2:0])?(VREF?VBUS)(4)
where conv.sub.10(HD.sub.SH[2:0]) is the conversion to a decimal value of HD.sub.SH[2:0], that is, the number of switchings of the capacitor.

(36) The equivalent read-out dynamic range can thus be automatically increased by value 2.Math.(2.sup.n).Math.(VREF?VBUS), or in other words multiplied by 2.sup.n, where n is the number of bits of binary counter 96, which may correspond to a much higher dynamic range than that of a conventional CTIA, according to the maximum value of the binary counter used and to the value of reference voltage VREF.

(37) A plurality of variations are possible for the use of signals HD.sub.SH[2:0] and V.sub.outSH.

(38) In a first variation, a conversion system and a calculation unit complete device 60. Conversion unit converts signals HD.sub.SH[2:0] and V.sub.outSH into digital values and the calculation unit calculates a final digital voltage according to the digital values of signals HD.sub.SH[2:0] and V.sub.outSH based on relation (4).

(39) In a second variation, a digital-to-analog converter and an adder complete device 60. The converter generates an analog voltage equal to 2.Math.conv.sub.10(HD.sub.SH[2:0])?(VREF?VBUS) according to signal HD.sub.SH[2:0], and the adder adds the voltage thus generated to voltage V.sub.outSH, or even directly voltage V.sub.out at the output of amplifier 62.

(40) In a third variation, a single output Video is used to implement the detector according to the invention.

(41) In a fourth variation, only signal HD.sub.SH[2:0] is supplied, it then being considered as a conversion into digital of the analog current received as an input. The device according to the invention is thus, in this context, an analog-to-digital converter. The number of bits of the counter and value VREF are then selected to define the converter quantization pitch, as well as its dynamic range.

(42) The implementation of the initial design, and then of the variable configuring or programming in operation of a detector according to the invention, is within the abilities of those skilled in the art, by means of usual architectures and protocols of digital programming of modern detectors, for example, the enabling or the inhibition on demand in a very simple and immediate way of the extended dynamic range function, or the forcing from the outside of one of the possible values of the total equivalent integration capacity (2.sup.n.Math.C.sub.int).

(43) A binary information over one or a plurality of digital bits synchronously indicating to the output signal whether a given pixel has been the object of a saturation or not is available in parallel with analog output VIDEO. This feature enables to conveniently and rapidly process all the image data, such as for example for video representation (immediate serial management data for a controlled use in the display dynamic range, for example) or any other informative use or use for an analog or digital processing of the data flow, in relation with the occurrence of a local saturation phenomenon.

(44) For example, in the context of a bolometric detector, such as described in relation with FIGS. 1 and 2, CTIAs 28 are replaced with devices 60 just described. For example, sample-and-hold circuits 68 of devices 60 are sample-and-hold circuits 36 and a second multiplexer is provided to deliver signals HD.sub.SH[2:0] in multiplexed mode. A conversion unit and a calculation unit then complete the detector to digitally restore the final voltage originating from each pixel 14.

(45) FIGS. 5A-B show an example of output of binary signals HD[2:0] in a specific case where three pixels Pix i+4, Pix i+7, and Pix i+8, in a multiplexed sequence, would have triggered the extension of the dynamic range according to the invention by causing from one to several times the switching of capacitor 46.

(46) In the context of an application to detection, the invention thus enables to keep an optimal sensitivity on the areas formed of all the pixels which do not cause the crossing of reference voltage VREF, that is, which do not saturate, VREF being selected to be smaller than or equal to saturation voltage V.sub.satH, while providing an exploitable signal on the areas of the image where the scene temperature is such that it would have made the voltage at the output of amplifier 62 saturate in the absence of the invention, that is, too high as compared with the nominal scene dynamic range (here, thermal). The output would have been deprived of information relative to the observed scene on these areas. A high sensitivity and a high scene dynamic range are thus obtained.

(47) According to an advantageous feature of the invention, the extension of the read-out dynamic range implemented by the integration device according to the invention may be activated or deactivated form the outside, for example, by means of a manual command or by software means, via a digital input HD_MODE_ON, such as illustrated in FIG. 3, transmitted by means of a programming interface, for example, the interface usually equipping the read-out circuits of detectors of the state of the art, or also directly externally programmed via a dedicated input.

(48) The read-out circuit incorporating the device according to the invention can thus be used at any moment either in normal mode, that is, in accordance with the operating mode described in relation with FIGS. 1 and 2, or in extended scene dynamic range mode. Typically, command HD_MODE_ON forces the low level at the output of comparator 94, and, thereby, counter 96 never changes state, and the switching of capacitor 64 is thus never activated. It should be noted that the setting of voltage VREF to any value greater than the maximum output voltage of the CTIA (generally greater than V.sub.satH due to the previously-specified linearity conventions) also has the effect of inhibiting the extension of the scene dynamic range of the sensor since output S.sub.COMP of comparator 94 is kept in the low state. The forcing of VREF to the same value as the power supply voltage of the amplifier will also have this inhibiting effect on the dynamic range extension device.

(49) A single capacitor 64 has been described. As a variation, a plurality of capacitors, selected in programmed fashion, are provided in parallel, to form an integration capacitor C.sub.int programmable over a plurality of values, as known per se in the state of the art. This enables to respond to different fields of application of the detector and provides the user with an external adjustment of the scene dynamic range. In this embodiment, the variation of capacitance C.sub.int is also plotted to restore the final voltage, the reconstruction being within the abilities of those skilled in the art.

(50) A 3-bit binary counter has been described. Of course, the number of bits of the counter depends on the targeted application. Further, the number of bits may be selected to be very large in order never to reach the maximum value thereof.

(51) Similarly, other types of counting circuits may be envisaged. For example, the output of comparator 62 is directly connected to the input of generator 92 which drives the different signals according to the switching of the comparator output, and the comparator output is supplied to a data processing unit which stores the number of switchings. The maximum number of switchings is thus dictated by the storage capacity of this unit and may be almost infinite.

(52) A specific application according to which the polarity of the integrated current and the architecture of the integration device cause an increase in output voltage V.sub.out of the operational amplifier according to the quantity of charge stored in the capacitor has been described. As a variation, the polarity of the current and/or the architecture of the integration device induce a decrease in voltage V.sub.out at the output of the amplifier as the quantity of charges stored in the capacitor increases. In such a variation, voltage VREF is selected to be greater than or equal to low saturation voltage V.sub.satL and voltage VBUS is selected to comply with relation 2.Math.VBUS?VREF?V.sub.satH. The comparator at the amplification output then switches from a first value to a second value when voltage V.sub.out is decreasing and equal to VREF, the switching being counted by the binary counter and causing the switching of the capacitor.

(53) A reference voltage VREF constant over time has been described. As a variation, this voltage is also programmable, its value being capable of varying even during the integration phase.

(54) According to a very simplified alternative embodiment, by adjusting the values of capacitance C.sub.int and of reference voltage VREF (according to the product) in integrated fashion in the architecture/internal wiring of the read-out circuit, the user has nothing to provide in terms of acquisition and/or data processing protocol to simultaneously have an extended dynamic range and a high sensitivity, which results in a high user friendliness.

(55) A detector using the invention to integrate the electric current originating from a critical site, for example, a bolometer, has a number of advantages over prior art reading circuits, in particular: the access to an extended scene dynamic range while keeping a high sensitivity on the image portion which can be transcribed in the nominal electric dynamic range of the CTIA alone while the linearity of the signal according to the flow is kept, conversely to certain logarithmic response systems, for example; the frame frequency (defined by the number of times when the entire array is read within one second) is kept identical to usual standards (60 Hz, for example). In other words, there is no degradation of the information time density with respect to certain forms of the state of the art in terms of dynamic range extension; the obtained scene information is kept in permanent time consistency or synchronicity with the scene. Indeed, the time interval separating any event in the scene from the forming of the signal usable by the observer or the system using the output flow of signals V.sub.out does not exceed a frame time, conversely to all detectors or systems having a data flow which is oversampled and/or processed by calculation after the forming of the raw signals to obtain the information considered as usable with an extended dynamic range; a simplification of the detector use. Indeed, in the state of the art, the user should generally himself select the operating point of the detector according to the observed scene temperature range. Generally, to give a general idea, the different operating points are necessary to cover dynamic range [?40? C.; +1,000? C.] with no saturation; as compared with methods of the technical field based on the adaptation of the integration time, the invention provides the advantage of not modifying the thermal cycle of the bolometer imposed by the self-heating by Joule effect during the integration cycle. Such a feature is particularly advantageous in terms of stability of the continuous level according to the ambient thermal operating conditions, in particular, when small scene temperature differences are searched for with a good time stability. The possible implementation efficiency of the detector with no Peltier stabilization module (so-called TEC-less operation), more and more current in the field, is thus kept; There is no resetting noise on inversion of the integration capacitance, as in certain forms of prior art, since the latter is never emptied, until after the time when signal V.sub.out is sampled; Further, the stray capacitances for example formed by the gates of the connection switches and the actual connections form an integral part of the integration capacitance and add no parasitic disturbance. The signal formed at the output is thus not altered by application of the invention.