POWER CONVERTER

Abstract

The invention provides a power converter for converting a three-phase alternating current (AC) supply to a direct current (DC) output, the power converter comprising: a first selector configured to select one of the highest, the second highest or the lowest instantaneous phase to phase voltages of the three-phase supply to provide a first power rail; a second selector configured to select a different one of the highest, the second highest or the lowest instantaneous phase to phase voltages of the three-phase supply to provide a second power rail; a first transformer coupled to the first power rail; a second transformer coupled to the second power rail; a combiner configured to combine the outputs of the first and second transformers to provide the DC output; and a duty cycle controller configured to vary duty cycles of the first and/or second transformers to thereby vary the relative contributions of the first and second power rails to the DC output.

Claims

1. A power converter for converting a three-phase alternating current (AC) supply to a direct current (DC) output, the power converter comprising: a first selector configured to select one of the highest, the second highest or the lowest instantaneous phase to phase voltages of the three-phase supply to provide a first power rail; a second selector configured to select a different one of the highest, the second highest or the lowest instantaneous phase to phase voltages of the three-phase supply to provide a second power rail; a first transformer coupled to the first power rail; a second transformer coupled to the second power rail; a combiner configured to combine the outputs of the first and second transformers to provide the DC output; and a duty cycle controller configured to vary duty cycles of the first and/or second transformers to thereby vary the relative contributions of the first and second power rails to the DC output.

2. The power converter according to claim 1 wherein the first transformer is coupled to the first power rail by way of a first inverter and wherein the second transformer is coupled to the second power rail by way of a second inverter.

3. The power converter according to claim 2 wherein the controller is configured to vary the duty cycle of the first transformer by varying the duty cycle of the first inverter and/or to vary the duty cycle of the second transformer by varying the duty cycle of the second inverter.

4. The power converter according to claim 1 wherein the first selector is configured to select the highest instantaneous phase to phase voltage of the three-phase supply to provide the first power rail.

5. The power converter according to claim 1 wherein the second selector is configured to select the second highest instantaneous phase to phase voltage of the three-phase supply to provide the second power rail.

6. (canceled)

7. The power converter according to claim 1 further comprising an input and an electromagnetic interference filter in communication with the input, wherein the electromagnetic interference filter comprises one or more capacitors, and wherein the duty cycle controller is configured to vary duty cycles of the first and/or second transformers to thereby vary the relative contributions of the first and second transformers in order to correct a power factor lead caused by the electromagnetic interference filter.

8. (canceled)

9. (canceled)

10. The power converter according to claim 7 wherein the duty cycle controller is configured to vary the duty cycles of the first and second transformers such that, for at least a portion of a phase cycle of the three phase supply, the first transformer outputs a greater amount of electrical energy than required by the DC output and a portion of the electrical energy provided by the first transformer is fed back to the electromagnetic interference filter by way of the second transformer to thereby correct the said power factor lead.

11. The power converter according to claim 10 wherein the control signals provided by the duty cycle controller to vary the duty cycles of the first and/or second transformers comprise one or more discontinuities.

12. The power converter according to claim 1 wherein the second selector comprises a plurality of bidirectional switches.

13. The power converter according to claim 12 wherein the controller is configured to control the said bidirectional switches of the second selector in phased relationship with the three phase AC supply to select the said different one of the highest, the second highest or the lowest instantaneous phase to phase voltages of the three-phase supply.

14. The power converter according to claim 1 further comprising a phase reference generator in communication with the duty cycle controller, the phase reference generator being configured to provide the duty cycle controller with a phase angle reference indicative of the instantaneous phase of the three-phase AC supply.

15. (canceled)

16. (canceled)

17. (canceled)

18. The power converter according to claim 1 wherein the power converter is configurable to convert a three-phase AC voltage supply to a DC voltage or DC current output in an AC to DC mode and to convert electrical energy from a DC voltage source to a three-phase AC current output in a DC to AC mode.

19. The power converter according to claim 1 wherein the first selector comprises a plurality of bidirectional switches.

20. The power converter according to claim 19 wherein the controller is configured to control said bidirectional switches of the first selector in phased relationship with the three phase AC supply to select the said one of the highest, the second highest or the lowest instantaneous phase to phase voltages of the three-phase supply.

21. The power converter according to claim 1 wherein the duty cycle controller is configured to vary the duty cycles of the first and/or second transformers to thereby maintain the total harmonic distortion of the line current drawn from each of one or more or each of the phases of the three-phase AC supply at less than 5%.

22. The power converter according to claim 1 wherein the second selector is configured to select the second highest instantaneous phase to phase voltage during a first portion of a 360° cycle of the three phase AC supply and to select the lowest instantaneous phase to phase voltage during a second portion of the said 360° cycle of the three phase AC supply different from the first portion.

23. The power converter according to claim 22 wherein the second selector is configured to select a phase to phase voltage between the highest instantaneous phase voltage and the second highest instantaneous phase voltage for one or more or each 360° cycle of the three phase AC supply.

24. The power converter according to claim 23 wherein the second selector is configured to select a phase to phase voltage between the second highest instantaneous phase voltage and the lowest instantaneous phase voltage for one or more or each 360° cycle of the three phase AC supply.

25. The power converter according to claim 1 wherein the duty cycle controller is configured to vary the duty cycles of the first and/or second transformers to thereby vary the relative contributions of the first and second power rails to the DC output in order to correct a power factor of each of one or more or each of the phases of the three phase supply.

26. A method of converting a three-phase alternating current (AC) supply to a direct current (DC) output, the method comprising: selecting one of the highest, the second highest or the lowest instantaneous phase to phase voltages of the three-phase supply to provide a first power rail; selecting a different one of the highest, the second highest or the lowest instantaneous phase to phase voltages of the three-phase supply to provide a second power rail; coupling the first power rail to a first transformer; coupling the second power rail to a second transformer; combining outputs of the first and second transformers to provide the DC output; and varying duty cycles of the first and/or second transformers to thereby vary the relative contributions of the first and second power rails to the DC output.

27. (canceled)

28. (canceled)

29. (canceled)

30. (canceled)

31. (canceled)

32. (canceled)

33. (canceled)

34. (canceled)

35. (canceled)

36. (canceled)

37. (canceled)

38. (canceled)

Description

DESCRIPTION OF THE DRAWINGS

[0128] An example embodiment of the present invention will now be illustrated with reference to the following Figures in which:

[0129] FIG. 1 is a schematic circuit diagram of a three-phase AC to DC power converter;

[0130] FIG. 2a shows how the instantaneous phase voltages of an exemplary three-phase supply vary with line phase;

[0131] FIG. 2b illustrates timings applied to the three switches of the second selector of FIG. 1 over a phase cycle of the three-phase AC supply;

[0132] FIG. 2c illustrates the voltages of the first and second bulk power rails over a phase cycle of the three-phase AC supply;

[0133] FIG. 3a is a simplified schematic circuit diagram of the first inverter of the power converter of FIG. 1;

[0134] FIG. 3b is a timing diagram illustrating the operation of the inverter of FIG. 3a;

[0135] FIG. 4a is a circuit diagram showing the transformers of the power converter of FIG. 1 connected to rectification and low pass filtering circuitry;

[0136] FIG. 4b is a timing diagram illustrating the operation of the transformers of FIG. 4a and the load current through the inductor of the low pass filtering circuitry;

[0137] FIG. 5 is a schematic block diagram of an exemplary implementation of the controller of the power converter of FIG. 1;

[0138] FIG. 6 is a schematic circuit diagram of a phase cross-over detection circuitry of the controller of FIG. 5;

[0139] FIG. 7 is a waveform diagram illustrating the generation of output events by the comparators of FIG. 6 and the phase angle reference generated by the phase angle reference generator of FIG. 5 taking into account the output events;

[0140] FIGS. 8a-8d are waveform diagrams showing: in phase voltage and current waveforms from a first phase of the three-phase AC supply for a portion of a phase cycle of the three-phase AC supply (FIG. 8a); the first and second power rail voltages of the power converter of FIG. 1 for that portion of a phase cycle (FIG. 8b); duty cycle control signals for the first and second transformers of the power converter of FIG. 1 for that portion of the phase cycle (FIG. 8c); and voltage and current waveforms at the DC output for that portion of the phase cycle (FIG. 8d);

[0141] FIG. 9 is a circuit diagram of an electromagnetic interference filter provided at an input of the power converter;

[0142] FIGS. 10a-10d are waveform diagrams showing: phase voltage and current waveforms from a first phase of the three-phase AC supply for a portion of a phase cycle of the three-phase AC supply (FIG. 10a), the phase current leading the phase voltage due to a leading power factor; the first and second power rail voltages of the power converter of FIG. 1 for that portion of a phase cycle (FIG. 10b); duty cycle control signals for the first and second transformers of the power converter of FIG. 1 for that portion of the phase cycle (FIG. 10c); and voltage and current waveforms of the DC output for that portion of the phase cycle (FIG. 10d);

[0143] FIGS. 11a-11d are waveform diagrams showing: phase voltage and current waveforms from a first phase of the three-phase AC supply for a portion of a phase cycle of the three-phase AC supply (FIG. 11a), the phase voltage and the phase current being in phase due to power factor correction according to the present invention; the first and second power rail voltages of the power converter of FIG. 1 for that portion of a phase cycle (FIG. 11b); adjusted duty cycle control signals for the first and second transformers of the power converter of FIG. 1 for that portion of the phase cycle in order to correct the leading power factor observed in FIG. 10a (FIG. 11c); and voltage and current waveforms at the DC output for that portion of the phase cycle (FIG. 11d);

[0144] FIG. 12 is a schematic circuit diagram of an alternative three-phase AC to DC power converter to that shown in FIG. 1 which permits electrical energy to be supplied to the capacitors of the electromagnetic interference filter from the first bulk power rail via the second transformer, inverter and rectifier connected to the second power rail to correct a leading power factor;

[0145] FIG. 13 is a schematic circuit diagram of a bi-directional three-phase AC to DC power converter having a first, AC to DC mode in which it is operable to convert a three-phase AC supply to a DC output and a second, DC to AC mode in which it is operable in reverse to convert a DC input to a three-phase AC output; and

[0146] FIG. 14 is a schematic circuit diagram of a hold-up capacitor circuit connected to, and between, the first and second power rails (and their returns) via respective switches.

DETAILED DESCRIPTION OF AN EXAMPLE EMBODIMENT

[0147] FIG. 1 is a schematic circuit diagram of a power converter 1 for converting a three-phase alternating current (AC) supply 2 to a DC output 3. The power converter 1 comprises a first selector 4 comprising a first three-phase diode bridge configured to select the highest instantaneous phase-to-phase voltage of the three-phase AC supply 2 between a first power rail portion 8 and a first return power rail portion 10 of a first power rail. The first three-phase diode bridge comprises the parallel combination of first, second and third circuit branches 11, 14, 16, each circuit branch 11, 14, 16 comprising two diodes 17 connected in series between the first power rail portion 8 and the first return power rail portion 10, both diodes 17 in each branch being connected in the same orientation (the cathode of a first diode in each branch being connected to the first power rail portion 8 and the anode of the first diode being connected to the cathode of a second diode of that branch, the anode of the second diode being connected to the return of the first power rail portion 8). A first phase 18 of the three-phase AC supply 2 is electrically connected to the anode of the first diode of the first circuit branch 11 and to the cathode of the second diode 17 of that branch; a second phase 20 of the three-phase AC supply 2 is electrically connected to the anode of the first diode 17 of the second circuit branch 14 and to the cathode of the second diode 17 of that branch 14; and a third phase 22 of the three-phase AC supply 2 is electrically connected to the anode of the first diode 17 of the third circuit branch 16 and to the cathode of the second diode 17 of that branch.

[0148] The power converter 1 further comprises a second selector 12 comprising a second three-phase diode rectifier bridge coupled to the three-phase AC supply 2 by way of first, second and third switches 26, 28, 30. The second three-phase diode rectifier bridge, together with the switches 26, 28, 30, is configured to select the second highest instantaneous phase-to-phase voltage from the three-phase AC supply between a second power rail portion 38 and a second return power rail portion 40 of a second power rail. The second three-phase diode rectifier bridge is identical to the first three-phase diode, with three circuit branches 32, 34, 36 (each comprising two series connected diodes 17 as discussed above) being connected together in parallel between the second power rail portion 38 and the second return power rail portion 40 (rather than between the first power rail portion 8 and the first return power rail portion 10). The first switch 26 is provided between the first phase 18 of the three-phase AC supply 2 and the anode of the first diode 17 and the cathode of the second diode 17 of the first circuit branch 32; the second switch 28 is provided between the second phase 20 of the three phase AC supply 2 and the anode of the first diode 17 and the cathode of the second diode 17 of the second circuit branch 34; and the third switch 30 is provided between the third phase 20 of the three phase AC supply 2 and the anode of the first diode 17 and the cathode of the second diode 17 of the third circuit branch 36.

[0149] The first, second and third switches 26, 28, 30 are independently switchable by a controller 42 between closed positions in which the respective first, second and third phases are connected to the first, second and third circuit branches 32, 34, 36 of the second diode bridge 24 respectively, and open positions in which the respective first, second and third phases are disconnected from the first, second and third circuit branches 32, 34, 36 of the second diode bridge respectively. The controller 42 is configured to open and close the switches 26, 28, 30 in phased relationship with the three-phase AC supply such that the second diode bridge selects the second highest instantaneous phase-to-phase voltage of the three-phase AC supply. For instantaneous phase voltages of the three-phase AC supply of:

V.sub.phase1=√2V.sub.rmscos (ωt)

V.sub.phase2=√2V.sub.rmscos(ωt+120°)

V.sub.phase3=√2V.sub.rmscos(ωt+240°)

[0150] where V.sub.rms is the line to neutral root-mean-square voltage of the three-phase supply and ωt is the line phase in degrees of the three-phase supply, the switch state for the first, second and third switches 26 (S1), 28 (S2), 30 (S3) are as follows:

S.sub.1state=mod(ωt+30°, 90°)<60°

S.sub.2state=mod(ωt+60°, 90°)<60°

S.sub.3state=mod(ωt, 90°)<60°

[0151] In this case, the voltages across the first and second bulk power rails (i.e. between the respective positive power rails 8, 38 and their returns 10, 40) will approximate to:

V.sub.RAIL1(ωt)=max(|V.sub.phase1(ωt)−V.sub.phase2(ωt)|, |V.sub.phase2(ωt)−V.sub.phase3(ωt)|, |V.sub.phase3(ωt)−V.sub.phase 1(ωt)|)

V′.sub.phase1=V.sub.phase1(ωt)S.sub.1state(ωt)

V′.sub.phase2=V.sub.phase2(ωt)S.sub.2state(ωt)

V′.sub.phase3=V.sub.phase3(ωt)S.sub.3state(ωt)

V.sub.RAIL2(ωt)=max(|V.sub.phase1(ωt)−V.sub.phase2(ωt)|, |V.sub.phase2(ωt)−V.sub.phase3(ωt)|, |V.sub.phase3(ωt)−V.sub.phase 1(ωt)|)

[0152] The instantaneous voltages of the first, second and third phases 18, 20, 22 of the three-phase AC supply are illustrated in FIG. 2a, with switch timings for switches 26 25 (S1), 28 (S2), 30 (S3) being illustrated in FIG. 2b. The first and second bulk power rail voltages 8, 38 are illustrated in FIG. 2c (for a phase cycle of the three-phase AC supply). In FIG. 2a, VφA is V.sub.phase1, VφB is V.sub.phase2 and VφC is V.sub.phase3.

[0153] The first power rail portion 8 and the first return power rail portion 10 are selectively coupled to a primary winding 50 of a first step-down transformer 52 by way of a first DC to AC inverter bridge 54. The first transformer 52 further comprises a secondary winding 55 magnetically coupled to the primary winding 50. The second power rail portion 38 and the second return power rail portion 40 are selectively coupled to a primary winding 56 of a second step-down transformer 58 by way of a second DC to AC inverter bridge 60. The second transformer 58 further comprises a secondary winding 61 magnetically coupled to the primary winding 56. The inverters 54, 60 act to convert the predominantly DC voltages across the respective first and second power rails (which also comprise an AC content at a (low) frequency related to the frequency of the three-phase AC supply, e.g. 50 Hz or 400 Hz) to predominantly high frequency (e.g. at least 1 kHz, at least 10 kHz or at least 100 kHz) AC voltages. By converting the predominantly DC voltages of the first and second power rails to higher frequency voltages, the physical sizes of the transformers 52, 58 (in particular the physical sizes of their cores) can be significantly reduced, thereby significantly decreasing the size and cost of the power converter 1.

[0154] The first and second inverter bridges 54, 60 are similar, so only the first inverter bridge 54 will be described in detail. However, it will be understood that the second inverter bridge 60 has similar features to the first inverter bridge 54.

[0155] As shown in FIG. 3a, the first inverter bridge comprises an H-bridge circuit comprising four switches, in this case n-channel field effect transistors (FETs) 62, 64, 66, 68, connected between the first power rail portion 8 and the first return power rail portion 10 (although it will be understood that other types of switch may be used in place of the FETs, such as insulated-gate bipolar transistors (IGBT) with anti-parallel diodes or Gallium Nitride (GaN) or Silicon Carbide (SiC) switches). The first and second FETs 62, 64 are connected in series with each other between the first power rail portion 8 and the first return power rail portion 10 in a first circuit branch 70 (the drain of the first FET 62 being connected to the first bulk power rail 8, the source of the first FET 62 being connected to the drain of the second FET 64 and the source of the second FET 64 being connected to the return 10 of the first bulk power rail), and the third and fourth FETs 66, 68 are connected in series with each other between the first power rail portion 8 and the first return power rail portion 10 in a second circuit branch 72 in parallel with the first circuit branch 70 (the drain of the third FET 66 being connected to the first power rail portion 8, the source of the third FET 66 being connected to the drain of the fourth FET 68 and the source of the fourth FET 68 being connected to the return 10 of the first power rail portion 8). The source of the first FET 62 and the drain of the second FET 64 are (electrically) connected to a first (dot) end of the primary winding 50 of the first transformer 52 and the source of the third FET 66 and the drain of the fourth FET 68 are (electrically) connected to a second (non-dot) end of the primary winding opposite the first end.

[0156] The gate terminals of the FETs 62-68 are in communication with the controller 42, which is configured to apply a voltage to the gate terminals to control whether the FETs 62-68 are in their conducting (“on”) states or their non-conducting (“off”) states.

[0157] The controller 42 is also configured to control the timings at which the FETs 62-68 are turned on and off.

[0158] As illustrated in FIG. 3b (where “TR*A ON” represents a voltage being applied between the gate and source terminals of the first FET 62 which is greater than or equal to the threshold voltage thereby causing the first FET 62 to be switched on, “TR*A OFF” represents a voltage being applied across the gate and source terminals of the first FET 62 of less than the threshold voltage to thereby cause the first FET 62 to be switched off, and similarly for the other FETs TR*B, TR*C, TR*D which correspond to FETs 64, 66 and 68 respectively), when the first FET 62 is on and the second FET 64 is off, the first end (the dot end) of the primary winding 50 of the first transformer 52 is connected to the first power rail portion 8. When the first FET 62 is off and the second FET 64 is on, the first end (the dot end) of the primary winding 50 of the first transformer is connected to the first return power rail portion 10. Similarly, when the third FET 66 is on and the fourth FET 68 is off, the second end (the non-dot end) of the primary winding 50 of the first transformer 52 is connected to the first power rail portion 8. When the third FET 66 is off and the fourth FET 68 is on, the second end (the non-dot end) of the primary winding 50 of the first transformer is connected to the first return power rail portion 10.

[0159] FIG. 3b is a timing diagram illustrating one and a half phase cycles of the first inverter bridge (which is typically much shorter than a phase cycle of the three phase supply). Initially, the first FET 62 is off and the second FET 64 is on. Accordingly, the voltage at the first (dot) end of the primary winding of the first transformer 52 is equal to the voltage of the first return power rail portion 10. At this stage, the third FET is off and the fourth FET is on. Accordingly, the voltage at the second end of the primary winding of the first transformer 52 is also equal to the voltage of the first return power rail portion 10. Accordingly, the voltages across the primary and secondary windings of the first transformer 52 are zero. After a period of time (corresponding to 90° of a 360° phase cycle of the first inverter bridge), the first FET 62 is switched on and the second FET 64 is switched off. This causes the first (dot) end of the primary winding to be connected to the first power rail portion 8. The third and fourth FETs 66, 68 remain off and on respectively. Accordingly, a positive voltage appears across the primary and secondary windings 50, 55 (albeit the voltage across the secondary winding 55 is half the voltage across the primary winding 50 because the turns ratio of the primary transformer 52 in this example is Np:Ns=4:2). After a further period of time (corresponding to 90° of a 360° phase cycle of the first inverter bridge), the third FET 66 is switched on and the fourth FET 68 is switched off. This causes the second end of the primary winding to be connected to the first power rail portion 8. The first and second FETs 62, 64 remain on and off respectively. Accordingly, the voltage across the primary and secondary windings 50, 55 reverts to zero. After a further period of time (corresponding to 90° of a 360° phase cycle of the first inverter bridge), the first FET 62 is switched off and the second FET 64 is switched on. This causes the first (dot) end of the primary winding 50 to be connected to the first return power rail portion 10. The third and fourth FETs 66, 68 remain on and off respectively. Accordingly, the voltage across the primary winding 50 is the negative of the voltage across the first power rail (and the voltage across the secondary winding 55 is half of this). This cycle then repeats to generate the AC waveform output by the first inverter bridge.

[0160] As shown in FIGS. 1 and 4a, the voltage and current outputs from the secondary windings 55, 61 of the first and second transformers 52, 60 are combined before being rectified by a rectifier 79 and low pass filtered by an LC low pass filter 80 to provide the DC output 3. The outputs from the secondary windings 55, 61 of the first and second transformers 52, 61 are combined by way of a series electrical connection. As the secondary windings 55, 61 are in series with each other, the electrical currents flowing through them must be equal. In the example of FIG. 4a, the rectifier is implemented as a diode bridge rectifier comprising four diodes 17. A first diode 17 is connected between the dot end of the secondary winding 55 of the first transformer 52 and an inductor L1 of the LC low pass filter (the anode being connected to the secondary winding and the cathode being connected to the inductor). A second diode 17 is connected between the inductor L1 and the non-dot end of the secondary winding 61 of the second transformer 58 (the anode being connected to the secondary winding 61 and the cathode being connected to the inductor L1). A third diode 17 is connected between the capacitor C of the LC filter and the non-dot end of the secondary winding 61 of the second transformer 58 (the anode being connected to the capacitor C and the cathode being connected to the secondary winding 61). A fourth diode 17 is connected between the anode of the third diodes 17 and the anode of the first diodes 17 (the anode of the fourth diode 17 being connected to the anode of the third diode 17 and the cathode of the fourth diode 17 being connected to the anode of the first diode).

[0161] FIG. 4b provides exemplary waveforms illustrating over one and a half phase cycles of the inverters 54, 60: the voltage across the secondary winding 55 of the first transformer 52 (top waveform); the voltage across the secondary winding 61 of the second transformer (second top waveform); the combined rectified voltages of the secondary windings 55, 61 of the first and second transformers 52, 58 (third top waveform); the DC voltage output from the low pass filter 80 (fourth top waveform); and the current through the inductor L1 (bottom waveform).

[0162] From a comparison of the voltage across the secondary winding 55 of the first transformer 52 (top waveform) and the voltage across the secondary winding 61 of the second transformer (second top waveform), it can be seen that a non-zero voltage appears across the secondary winding 61 of the second transformer 58 for less time than a non-zero voltage appears across the secondary winding 55 of the first transformer 52 over a phase cycle of the first and second inverters 54, 60. This is because the second transformer 58 has been provided with a lower duty cycle that the first transformer 52 by the controller 42. The duty cycle of the first transformer 52 can be defined as the percentage of a phase cycle of the first inverter 54 for which the first transformer 52 is active (i.e. the percentage of a phase cycle for which a non-zero voltage is applied across the primary winding 50). The duty cycle of the first transformer 52 may be defined as:

Duty1=(φ.sub.PWM1_2−φ.sub.PWM1_1)/180°

[0163] where φ.sub.PWM1_1 is the period of time from the beginning of a phase cycle until the rising edge occurs when the voltage across the primary winding of the first transformer 52 goes high (corresponding to when the first FET 62 is closed and the second FET 64 is opened) and φ.sub.PWM1_2 is the period of time from the beginning of a phase cycle until the falling edge which occurs when the voltage across the primary winding of the first transformer 52 reverts to zero.

[0164] Similarly, the duty cycle of the second transformer 58 can be defined as the percentage of a phase cycle of the second inverter 60 for which the second transformer 58 is active (i.e. the percentage of a phase cycle for which a non-zero voltage is applied across the primary winding 56 of the second transformer 58). Using similar notation to that provided above, the duty cycle of the second transformer can be defined as:

Duty2=(φ.sub.PWM2_2−φ.sub.PWM2_1)/180

[0165] where φ.sub.PWM2_1 is the period of time from the beginning of a phase cycle until a rising edge occurs when the voltage across the primary winding of the second transformer 58 goes high and φ.sub.PWM2_2 is the period of time from the beginning of a phase cycle until the falling edge which occurs when the voltage across the primary winding of the second transformer 58 reverts to zero.

[0166] In prior art power converters (such as the one described in EP2067246), the duty cycles of the first and second transformers are fixed and equal.

[0167] When the duty cycles of the first and second transformers are fixed and equal (as is the case in EP2067246), the currents drawn from the primary windings 50, 56 (and thus the secondary windings 55, 61) of the first and second transformers 52, 58 to provide the DC output are determined by the turns ratios (Ns:Np) of the first and second transformers 52, 58 (which are illustrated in FIG. 1 as being equal, but need not be). The average voltage across the DC output is also determined by the turns ratios of the first and second transformers 52, 58. Accordingly, the turns ratios of the first and second transformers are typically carefully chosen to optimise the power factor.

[0168] For an ideal power factor, the current flowing into or out of one of the three phases of the three-phase AC supply should be proportional to the sum of instantaneous voltages between the said phase and the two other phases. In addition, the ratio of the magnitude of the current drawn (e.g. by the DC output) from the second power rail to the magnitude of the current drawn (e.g. by the DC output) from the first power rail should be equal to the ratio of the sine of the instantaneous line phase angle to the sine of a compensated instantaneous line phase angle, the compensated instantaneous line phase angle being the instantaneous phase angle compensated for a phase difference between the phase voltage of the second power rail not in common with the first power rail and the phase voltage of the first power rail not in common with the second power rail (by adding a leading phase difference between them or subtracting a lagging phase difference between them). For example, at 0°, the first power rail is provided by the phase to phase voltage between the first and third phases 18, 22 and the second power rail is provided by the phase to phase voltage between the first and second phases 18, 20. The sine of the instantaneous phase angle (0°) is equal to 0, while the sine of the compensated instantaneous phase angle (0°+120°=120°) is equal to 0.866, the said ratio being 0. Accordingly, the current drawn from the second power rail should be 0 A. At 15°, the ratio is (sine(15°)/sine(135°)=)0.366. Therefore, the current drawn from the second power rail should be 0.366 times that drawn from the first power rail. At a phase angle of 30°, the current drawn from the second power rail should be equal to that drawn from the first power rail and so on.

[0169] As shown in FIG. 2c, during a phase cycle of the three-phase AC supply the voltages across both the first bulk power rail 8, 10 and the second bulk power rail 38, 40 rise and fall six times, with mirror symmetry about the peaks and troughs. Accordingly, other than at the peaks and troughs, specific ideal ratios of the current drawn from the first power rail 8, 10 to the current drawn from the second power rail 11 38, 40 are each repeated twelve times for each AC cycle. Between those twelve design points, the currents drawn from the first and second bulk power rails 8, 10 and 13 38, 40 (and thus from the first, second and third phases of the three-phase supply) are constrained to the design currents, leading to a stepped load profile. This in turn increases the harmonic content of the phase currents and increases the voltage ripple on the output DC voltage. In EP2067246, additional pairs of secondary windings having different numbers of turns may be connected in parallel with the series combination of the secondary windings 55, 61. Although this alleviates the constraints on the currents drawn from the first and second bulk power rails 8, 38 to an extent, thereby reducing the harmonic content of the phase currents and output voltage ripple, the addition of secondary winding pairs increases the cost and size of the power converter. There is also a practical limit to the benefit that can be achieved by this approach (e.g. a maximum of 3 or 4 additional pairs of secondary windings can realistically be added).

[0170] The inventor has realised that the relative contributions of the first and second transformers 52, 58 to the DC output (and thus the currents drawn from the first and second bulk power rails 8, 10 and 38, 40) can be adjusted by varying the duty cycles of the first and second transformers 52, 58. This is achieved, in the present exemplary embodiment, by the controller 42 adjusting the timings of the switching on and off of the FETs of the first and second inverter bridges 54, 60 through which the first and second bulk power rails 8, 10 and 38, 40 are coupled to the first and second transformers 52, 58. The duty cycles of the first and second transformers can thus be varied with a much finer granularity by the controller 42 (e.g. the duty cycles of the first and second transformers 52, 58 may be adjusted once per magnetic cycle of the first and second transformers respectively). Accordingly, the currents drawn from the first and second bulk power rails 8, 38 can be selected in the ideal ratio for each magnetic cycle of the first and second transformers 52, 58 (i.e. for more than 12 discrete values of line phase per phase cycle of the three phase AC supply without requiring additional pairs of transformers).

[0171] To achieve minimum output voltage ripple and minimum line current harmonic content of the three phases of the three phase supply, the duty ratios as a function of the line phase are given by the following expressions, Duty1 being the duty cycle of the first transformer 52 and Duty2 being the duty cycle of the second transformer 58:

Duty1=Ksin(60°−|30°−mod(ωt, 60°)|−φ)

Duty2=Ksin(|30°−mod(ωt, 60°)|−φ) N.sub.T2p/N.sub.T2s, N.sub.T1s/N.sub.T1p

[0172] where N.sub.T1p is the number of turns in the primary winding 50 of the first transformer 52 [0173] N.sub.T1S is the number of turns in the secondary winding 55 of the first transformer [0174] N.sub.T2p is the number of turns in the primary winding 56 of the second transformer 58 [0175] N.sub.T2s is the number of turns in the secondary winding 61 of the second N.sub.T2S transformer 58 [0176] K is a constant (or in some cases a slowly varying) term provided by a feedback network (where provided) from the DC output to the controller 42 [0177] φ is phase shift compensation.

[0178] It will be understood that the feedback provided from the DC output to the controller 42 is optional.

[0179] Other useful relations are as follows:

K=K.sub.1δ.sub.T (where K.sub.1 is the gain factor for Duty 1)

[0180] where δ.sub.T is the sum of Duty 1 and Duty 2 and, where the input voltages of the three phase supply and the output load are constant, δ.sub.T can be treated as a constant.

K.sub.2=K.sub.1N.sub.T2p/N.sub.T2s, N.sub.T1s/N.sub.T1p (where K.sub.2 is the gain factor for Duty 2)

[0181] K.sub.1, K.sub.2 and K can be derived from the knowledge that only the first power rail contributes to the output when ωt=30° (assuming φ=0):

Duty1=Ksin(60°)

δ.sub.T=K.sub.1δ.sub.Tsin)(60°)

K.sub.1=1/sin(60°)=b 1.155

K.sub.2=K.sub.1N.sub.T2p/N.sub.T2s, N.sub.T1s/N.sub.T1p

K=.sub.1Kδ.sub.T

[0182] In an example where N.sub.T1p=16, N.sub.T1s=10, N.sub.T2P=13, N.sub.T2S=6 and δ.sub.T=0.643, K=0.743 and K.sub.2=1.56.

[0183] Neglecting losses (such as the forward voltage of the rectifier diodes), the voltage across the DC output will be given by:

[00001]$V_{\mathrm{outDC}}=K\surd 6\frac{N_{T1S}}{N_{T1p}}{\mathrm{Vin}}_{\mathrm{rms}}\left[\mathrm{Duty}1\frac{\mathrm{NT}1S}{\mathrm{NT}1P}+\mathrm{Duty}2\frac{\mathrm{NT}2S}{\mathrm{NT}2P}\right]$

[0184] where Vin.sub.rms is the root mean squared voltage of one of the phases of the three phase AC supply.

[0185] The duty cycles of the first and second transformers 52, 58 are typically different from each other for at least a portion (typically for the majority of) a phase cycle of the three-phase AC supply.

[0186] To ensure that the average currents in the first and second inverters 54, 60, and therefore the current drawn from the first and second bulk power rails 8, 10 and 38, 40 respectively, are proportional to the duty cycles of the first and second transformers 52, 58, the active drive periods of the first and second transformers are centrally nested, that is:

φ.sub.PWM1_2+φ.sub.PWM1_1=φ.sub.PWM2_2+φ.sub.PWM2_1

[0187] This is illustrated in FIG. 4b by the fact that the rectified voltage pulses provided by the secondary winding 61 of the second transformer 58 are superimposed on the centres of the corresponding rectified voltage pulses output by the secondary winding 55 of the first transformer 52.

[0188] This can be implemented as:

[00002]$\mathrm{If}\mathrm{Duty}1\ge \mathrm{Duty}2:{\phi }_{\mathrm{PWM}1\_1}=0°{\phi }_{\mathrm{PWM}1\_2}=180°\mathrm{Duty}1{\phi }_{\mathrm{PWM}2\_1}=180°\frac{\mathrm{Duty}1-\mathrm{Duty}2}{2}{\phi }_{\mathrm{PWM}2\_2}=180°\frac{\mathrm{Duty}1+\mathrm{Duty}2}{2}\mathrm{If}\mathrm{Duty}1<\mathrm{Duty}2:{\phi }_{\mathrm{PWM}1\_1}=180°\frac{\mathrm{Duty}2-\mathrm{Duty}1}{2}{\phi }_{\mathrm{PWM}1\_2}=180°\frac{\mathrm{Duty}1+\mathrm{Duty}2}{2}{\phi }_{\mathrm{PWM}2\_1}=0°{\phi }_{\mathrm{PWM}2\_2}=180°\mathrm{Duty}2$

[0189] For optimum reduction in line current harmonic content of the three phases of the three phase AC supply, the power converter should operate in continuous conduction mode, i.e. the current in the filter inductor L1 remains greater than 0 A at all times when the power converter is in use.

[0190] The required drive waveforms for electronic switches S1, S2, S3 and the FETs of the first and second inverters 54, 60 are typically derived by the controller 42, which may for example comprise a digital signal processing integrated circuit. There are numerous devices which are optimised for switched mode power supply control which would be suitable, such as a Microchip Technology Inc. dsPIC33FJ32GS406. An exemplary implementation of the controller 42 is illustrated in FIG. 5, and described below.

[0191] In the exemplary embodiment of FIG. 5 the controller 42 comprises a digital signal processor 90 comprising a pulse width modulator 92 configured to request and receive an input from a sine-wave lookup table 94 and to provide outputs to first, second, third and fourth pulse width modulation (PWM) modules 96, 98, 100, 102. The first PWM module 96 is coupled to the gate terminals of the first and second FETs 62, 64 of the first inverter 54 and the second PWM module 98 is coupled to the third and fourth FETs 66, 68 of the first inverter to thereby control φ.sub.PWM1_1 and φ.sub.PWM1_2 based on signals provided by the pulse width modulator 92 (which are based, in turn, on signals received from the sine-wave look up table 94). Similarly, the third PWM module 100 is coupled to the gate terminals of the first and second FETs of the second inverter 60 and the fourth PWM module 102 is coupled to the gate terminals of the third and fourth FETs of the second inverter to control φ.sub.PWM2_1 and φ.sub.PWM2_2 based on signals provided by the pulse width modulator 92 (which are based, in turn, on signals received from the sine-wave look up table 94). The pulse width modulator 92therefore controls the duty cycles Duty1 and Duty2 of the first and second transformers 52, 58 by way of the sine look up table 94, the PWM modules 96-102 and the first and second inverters 54, 60.

[0192] The pulse width modulator 92 is configured to receive feedback from the DC output 3 by way of a feedback network 104. In this case the feedback network 104 comprises a voltage divider comprising first and second resistors R1 and R2 connected in series with one another between the DC output 3 and ground. Line 106 extends from between R1 and R2 of the voltage divider to an inverting input of an operational amplifier 108, and a voltage reference 109 is provided to the non-inverting input of the operational amplifier 108. The voltage reference 109 is the desired DC output scaled down by a factor of R.sub.2/(R.sub.1+R.sub.2). The amplifier 108 will act to force the voltage between R1 and R2 to a value equal to the voltage reference 109, to thereby generate a DC output 3 in accordance with the desired DC output by way of line 106. This section of the controller 42 thus provides a DC output voltage control loop. The output of the operational amplifier 108 provides the pulse width modulator 92 with the constant or slowly varying term K discussed above.

[0193] The pulse width modulator 92 is also configured to receive a phase angle reference from a phase reference generator 110. The phase angle reference provided by the phase reference generator is indicative of the instantaneous phase of the three-phase AC supply at any given time. The phase angle reference is fed to and used by the pulse width modulator 92 together with the signals from the sine-wave look up table 94 (and optionally the feedback signal from the DC output) to control the timings of the signals applied to the FETs of the first and second inverters by way of the PWM modules 96-102 to thereby control the duty cycles of the first and second transformers 52, 58.

[0194] The phase angle reference generator 110 comprises a phase cross-over detect module 112, which may be implemented by way of computer program instructions executed by the digital signal processor or by hardware circuitry external to the digital signal processor, configured to receive instantaneous voltages of each of the three phases 18, 20, 22 of the three-phase AC supply as inputs and to determine cross-over points when one of the phases 18, 20, 22 becomes greater than or equal to another within a phase cycle of the three phase AC supply. As illustrated in FIG. 2a, this occurs six times per phase cycle of the three-phase supply, and the phase interval between cross-over points is 60° (for an ideal three-phase AC supply 2). An exemplary phase cross-over detect module 112 is illustrated in more detail in FIG. 6. In this case the phase cross-over detect module 112 comprises first, second and third comparators 113, 114, 115: the first comparator 113 being configured to compare the instantaneous voltages of the first and second phases 18, 20; the second comparator 114 being configured to compare the instantaneous voltages of the first and third phases 18, 22; and the third comparator 115 being configured to compare the instantaneous voltages of the second and third phases 20, 22. The comparators 113-115 each output a positive voltage when the instantaneous voltage of a first one of the phase inputs becomes greater than or equal to the other of the phase inputs, thereby outputting a rising edge, and a zero voltage when the instantaneous voltage of the said other of the phase inputs becomes greater than or equal to the first one of the said phase inputs, thereby outputting a falling edge. This is shown in FIG. 7, the top waveform showing an analogue representation of a digital phase angle count provided by a phase angle counter of the phase locked loop (PLL) control module 120 of the controller 42 representing line phase over two complete phase cycles of the three-phase AC supply (although it will be understood that the phase angle count is virtual in practice), and the bottom three waveforms of which correspond to the outputs from the comparators 113-115 during the said two complete phase cycles of the three-phase AC supply. The first (top) of these waveforms shows the output of comparator 113, which is high (digital output ‘1’) when the instantaneous voltage of phase 1 is greater than the instantaneous voltage of phase 2 and low (digital output ‘0’) when the instantaneous voltage of phase 2 is greater than the instantaneous voltage of phase 1. The second (middle) of these waveforms shows the output of comparator 114, which is high when the instantaneous voltage of phase 2 is greater than the instantaneous voltage of phase 3 and low when the instantaneous voltage of phase 3 is greater than the instantaneous voltage of phase 2. The third (bottom) of these waveforms shows the output of comparator 115, which is high when the instantaneous voltage of phase 3 is greater than the instantaneous voltage of phase 1 and low when the instantaneous voltage of phase 1 is greater than the instantaneous voltage of phase 3.

[0195] The rising and falling edges of the outputs of the comparators 113-115 can be considered as output events generated by the phase cross-over detect module 112. These output events are detected (e.g. by respective edge detectors) and fed to the PLL control module 120, the PLL control module 120 being galvanically isolated from the phase cross-over detection module 112 by a galvanic isolation module 117. The PLL control module 120 generates a repeating sawtooth waveform, the lowest amplitude of which indicates a 0° phase angle and the maximum amplitude of which indicates a 360° phase angle of the 3-phase AC supply. A counter within the digital signal processor 90 counts from 0 to 2″, each count of which digitally represents a phase angle value. N is the number of bits used in the counter. The count 0 to 2″ repeats each time a count of 2″ is reached.

[0196] Over time, the sawtooth waveform generated by the counter is adjusted by the PLL control module 120 taking into account the relative phases of the detected cross-over points (which are of known phase). This ensures that the phase angle reference stays in phase with the three-phase AC supply 2. The six output events of known phase detected within each phase cycle of the three-phase supply provide the phase locked loop with accurate reference information which helps to ensure the accuracy of the phase angle reference. The accuracy of the phase angle reference is particularly important for ensuring that the pulse width modulator 92 and PWM modules 96-102 control the duty cycles of the first and second transformers 52, 58 accurately.

[0197] As illustrated in FIG. 5, the phase angle reference output by the PLL control module 120 is also used by a control module 130 which is configured to open and close switches 26, 28, 30 to ensure that the second selector 112 selects the second highest instantaneous phase-to-phase voltage at any given time.

[0198] FIG. 8a illustrates the instantaneous voltage and current of the first input phase 18 of the three-phase AC supply over half of a phase cycle of the three-phase AC supply 2 (which in this case comprises a line to line voltage of 200V at 50 Hz) at 100% load. These plots assume a unity power factor as the phase current and phase voltage are in phase with each other. FIG. 8b illustrates the instantaneous voltages across the first and second bulk power rails 8, 10 and 38, 40 over the same half of a phase cycle. FIG. 8c shows the signals provided by the sine-wave look up table 94 to the pulse width modulator 92, the magnitudes of the signals being normalised such that a 1V signal represents a 100% duty cycle (it will be understood that, when the controller 42 is digital, the signals provided by the sine-wave look up table 94 are virtual). In order to implement the above expression for Duty1, the signal provided by the sine-wave look up table 94 to the pulse width modulator 92 to control the duty cycle of the first transformer 52 conforms to the equation for Duty1 provided above.

[0199] Duty1 is labelled as V(B1_Duty) in FIG. 8c (and is represented by a solid line). As shown in FIG. 8c, this corresponds (over each 60° phase cycle, for an ideal three-phase AC supply) to a concatenation of first and second portions of a sine wave, a first portion of a sine wave from 30° to 60° and a second portion from 60° to 30° .

[0200] Similarly, in order to implement the above expression for Duty2, the signal provided by the sine-wave look up table 94 to the pulse width modulator 92 to control the duty cycle of the second transformer 58 conforms to the equation provided for Duty2 above.

[0201] Duty2 is labelled as V(B2_Duty) in FIG. 8c (and is represented by a dashed line). As shown in FIG. 8c this corresponds (over each 60° phase cycle, for an ideal three-phase AC supply) to a concatenation of third and fourth scaled portions of a sine wave, a third portion from 30° to 0° and a fourth portion from 0° to 30°.

[0202] The pulse width modulator 92 calculates the required values of φ.sub.PWM1_1, φ.sub.PWM1_2, φ.sub.PWM2_1 and φ.sub.PWM2_2 using the relations set out above.

[0203] The signals provided by the sine-wave look up table 94 to control the duty cycle of the first transformer 52 are always positive and non-zero, indicating that the duty cycle of the first transformer 52 is always positive and non-zero (i.e. the first transformer continuously supplies electrical energy to the DC output). The signals provided by the sine-wave look up table 94 to control the duty cycle of the second transformer 58 are always greater than or equal to zero, indicating that the duty cycle of the second transformer is always greater than or equal to zero (i.e. for the most part the second transformer supplies electrical energy to the DC output, but at the points at which the duty cycle of the second transformer 58 equals zero, the second transformer 58 does not supply electrical energy to the DC output).

[0204] FIG. 8d shows the voltage and current at the DC output 3 for the illustrated half phase cycle of the three-phase AC supply. The voltage and current at the DC output both remain constant (or substantially constant) over this half cycle.

[0205] The power converter 1 typically comprises an electromagnetic interference filter 150, such as the one shown in FIG. 9, configured to reduce the line current harmonics fed back into the three phase AC supply from the power converter 1. The electromagnetic interference filter 150 comprises a first inductor 152 connected to the first phase 18, a second inductor 154 connected to the second phase 20 and a third inductor 156 connected to the third phase 22. The filter 150 further comprises a first capacitor 158 connected from a position between the first phase 18 and the first inductor 152 and a position between the second phase 20 and the second inductor 154, a second capacitor 160 connected from a position between the first phase 18 and the first inductor 152 and a position between the third phase 22 and the third inductor 156, and a third capacitor 162 connected from a position between the second phase 20 and the second inductor 154 and a position between the third phase 22 and the third inductor 156. The filter 150 further comprises a fourth capacitor 170 connected from a position between the first inductor 152 and the first and second selectors 4, 12 to a position between the second inductor 154 and the first and second selectors 4, 12, a fifth capacitor 172 connected from a position between the first inductor 152 and the first and second selectors 4, 12 and a position between the third inductor 156 and the first and second selectors 4, 12, and a sixth capacitor 174 connected from a position between the second inductor 154 and the first and second selectors 4, 12 and a position between the third inductor 156 and the first and second selectors 4, 12. These capacitors 158-162, 170-174 produce a phase shift and result in the steps 175 in the current waveform of FIG. 10a (see below). The capacitors are minimised in size to minimise total harmonic distortion.

[0206] For the purposes of the following discussion, the simpler electromagnetic interference filter 150 illustrated in FIG. 1 will be considered. In this case, the electromagnetic interference filter 150 consists of respective capacitors 176 each having a value C.sub.filter provided across each pair of phases of the three phase supply and connected together in a delta arrangement. The equivalent input filter capacitor (delta-to-star conversion) can be considered to be C.sub.eq=3C.sub.filter.

[0207] The waveforms shown in FIG. 8a above assumed that the phase current and phase voltage within each phase of the three-phase supply were in phase with each other (i.e. that the input power factor of the converter was unity). However, current flow within the capacitors 176 of the electromagnetic interference filter 150 provide the power converter 1 with a power factor lead. This is illustrated by the waveforms shown in FIG. 10a, which show the instantaneous voltage (dotted lines) and current (solid line) drawn from the first phase 18 when there is a leading power factor (the phase current leads the phase voltage) which has not been corrected for. FIGS. 10b and 10c are identical to FIGS. 8b and 8c, but the DC outputs shown in FIG. 10d are lower than those in FIG. 8d due to a 20% load (rather than the 100% load of FIG. 8a) in this example.

[0208] The power factor lead introduced by the electromagnetic interference filter 150 can be corrected (brought closer to unity) by adjusting the duty cycles of the first and second transformers 52, 58, thereby varying the relative contributions of the first and second transformers 52, 58 to the DC output 3. This is illustrated in FIG. 11a which shows the instantaneous voltage and current drawn from the first phase 18 in phase with each other.

[0209] In order to achieve power factor correction, a non-zero phase compensation term φ needs to be considered in the equations for Duty1 and Duty2. In order to determine φ, the capacitive current magnitude due to C.sub.eq must be taken into account. This can be determined from:

I.sub.Ceq_filter=ωC.sub.eqV.sub.pk

[0210] where V.sub.pk is the peak input voltage of one of the phases of the three phase AC supply.

[0211] In addition, the capacitive currents passing through capacitors 180, 182 provided between the first power rail portion and its return and between the second power rail portion and its return respectively must also be considered. These can be determined from:

I.sub.Bulkcap=ω√6Vrms(0.083C.sub.Bulk1+0.205C.sub.Bulk2)

[0212] where C.sub.Bulk1 is the capacitance of capacitor 180 and C.sub.Bulk2 is the capacitance of capacitor 182 and V.sub.rms is the line-neutral RMS input voltage of the three phase supply.

[0213] The minimum current in the first power rail is defined by:

[00003]$I_{\mathrm{Bulk}1\_\min }=K_1{\delta }_T\sin \left(30°\right)I_{\mathrm{outDC}}\frac{N_{T1s}}{N_{T1p}}$

[0214] where I.sub.outDC is the output DC current.

[0215] The maximum current in the second power rail is defined by:

[00004]$I_{\mathrm{Bulk}2\_\max }=K_2{\delta }_T\sin \left(30°\right)I_{\mathrm{outDC}}\frac{N_{T2s}}{N_{T2p}}$

[0216] The total current delivered to the first and second power rails is:

[00005]$I_{\mathrm{Bn}\_pk}=I_{\mathrm{Bulk}1\_\min }+I_{\mathrm{Bulk}2\_\max }{I}_{\mathrm{Bn}\_pk}=K_1{\delta }_T\sin \left(30°\right)I_{\mathrm{outDC}}\frac{N_{T1s}}{N_{T1p}}+K_2{\delta }_T\sin \left(30°\right)I_{\mathrm{outDC}}\frac{N_{T2s}}{N_{T2p}}{I}_{\mathrm{Bn}\_pk}=K_1{\delta }_T{I}_{\mathrm{outDC}}\frac{N_{T1s}}{N_{T1p}}$

[0217] The phase-shift compensation parameter is expressed as:

[00006]$\phi ={\tan }^{-1}\frac{\left(I_{\mathrm{Ceq}}+I_{\mathrm{Bulkcap}}\right)}{I_{\mathrm{Bn}\_pk}}$

[0218] In the present example, the following parameters are assumed: V.sub.rms=254V; AC peak line-neutral input voltage, V.sub.pk=359V; frequency of three phase supply, f.sub.AC=60 Hz; output power P.sub.outDC=3 kW; Output voltage, V.sub.outDC=250V; output current, I.sub.outDC=12 A; N.sub.T1p=16; N.sub.T1s=10; N.sub.T2p=13; N.sub.T2s=6; δ.sub.T=0.643; C.sub.filter=2400 nF; C.sub.Bulk1=680 nF; C.sub.Bulk2=1 nF; K.sub.1=1.155 (as above).

[0219] In this case:

[00007]$I_{\mathrm{Ceq}\_\mathrm{filter}}=2\sqcap \left(60\mathrm{Hz}\right)\times 7.2\mu F\times 359V=0.975A{I}_{\mathrm{Bulkcap}}=2\sqcap \left(60\mathrm{Hz}\right)\surd 6\times 254\times \left(\left(0.083\times 680nF\right)\right)=0.013A{I}_{\mathrm{Bn}\_pk}=1.155\times 0.643\times 12\times 10/16=5.57A\phi ={\tan }^{-1}\frac{\left(0.975+0.013\right)}{5.57}=0.176\mathrm{radians}\left(\mathrm{or}10°\right)$

[0220] Thus, in the present case, power factor correction is achieved by applying a 10° phase shift (a phase lag in the present embodiment) to the Duty1 and Duty2 signals requested from the sine-wave look up table 94 and providing the phase shifted signals to the pulse width modulator 92, as illustrated in FIG. 11c. The repeated sine wave portions from the look up table controlling the duty cycle of the first transformer have been phase shifted from a combination of a 60° to 30° portion of a sine wave and a 30° to 60° portion to a combination of a 70° to 40° portion and a 20° to 50° portion. The repeated sine wave portions from the look up table controlling the duty cycle of the second transformer 58 have been changed from a combination of a 0° to 30° portion of a sine wave and a 30° to 0° portion to a combination of a -10° to 20° portion of a sine wave and a 40° to 10° portion of a sine wave.

[0221] As shown in FIG. 11c, this introduces steps (discontinuities) into the signals provided by the sine-wave look up table 94 because, in respect of the signals controlling the duty cycle of the first transformer 52, the magnitude of a sine wave at 40° is not equal to the magnitude of a sine wave at 20° and the magnitude of a sine wave at 50° is not equal to the magnitude of a sine wave at 70°. Similarly, in respect of the signals controlling the duty cycle of the second transformer 58, the magnitude of a sine wave at 20° is not equal to the magnitude of a sine wave at 40° and the magnitude of a sine wave at −10° is not the same as the magnitude of a sine wave at 10°. The signals provided by the sine-wave look up table 94 to control the duty cycle of the first transformer 52 are still always positive and non-zero, indicating that the duty cycle of the first transformer 52 is always positive and non-zero (i.e. the first transformer continuously supplies electrical energy to the DC output). However, for a number of (short) time periods of a phase cycle of the three-phase supply, the signals requested from and provided by the sine-wave look up table 94 to the pulse width modulator 92 to control the duty cycle of the second transformer 58 are negative. This indicates that, for a portion of each phase cycle of the three-phase supply, the duty cycle of the second transformer 58 is negative. That is, for the said portions of each phase cycle of the three-phase supply, the second transformer 58 (and therefore the second bulk power rail 38, 40) consumes electrical energy rather than supplies it to the DC output. This consumed electrical energy is supplied by the first transformer 52, which also solely supplies the DC output during these time periods. Therefore, for these portions of each phase cycle of the three-phase supply, the first transformer 52 (and therefore the first power rail 8, 10) supplies more electrical energy than is required by the DC output 3. For these time periods, it can be said that the second transformer has a negative duty cycle.

[0222] The electrical energy consumed by the second transformer 58 during these portions of the phase cycle of the three-phase AC supply is sent back through the secondary winding 61 of the second transformer 58 to the primary winding 56 thereof and ultimately onto the capacitors of the electromagnetic interference filter 150 where it is stored until the duty cycle of the second transformer 58 becomes positive again, when the said electrical energy is discharged from the capacitors through the second selector 12, the second power rail 38, 40 the second inverter 60 and ultimately the second transformer 58. The electrical energy consumed by the second transformer 58 is effectively superimposed onto the capacitors of the electromagnetic interference filter to correct the power factor of the power converter towards unity. This is because the electrical energy consumed by the second transformer is 180° out of phase with the electrical energy provided by the three phase supply (and can therefore be used to correct the power factor lead provided by the electromagnetic interference filter to the electrical energy provided by the three phase supply). Thus, by adding a phase lag to the inverter current loads, the reactive currents in the electromagnetic interference filter which lead the AC voltage may be balanced out, thereby improving power factor. This is particularly important when the load of the converter reduces and the reactive load of the electromagnetic interference filter becomes increasingly significant.

[0223] FIGS. 11b and 11d are identical to FIGS. 10b and 10d.

[0224] It will be understood that it would not be possible to send electrical energy from the first power rail 8, 10 back to the electromagnetic interference filter 150 by way of the second inverter 60 and the second selector 12 shown in FIG. 1 because the diodes of the second selector 12 are unidirectional. Accordingly an alternative second selector design is employed which allows electrical energy to be sent back from the first power rail 8, 10 to the capacitors of the electromagnetic interference filter 150 by way of the second inverter 60 and the second selector. For example FIG. 12 shows an alternative power converter comprising a second selector 190 comprising six bi-directional switches 192-202, one between the each phase of the three phase supply and the second power rail portion 38 and one between each phase of the three phase supply and the second return power rail portion 40 of the second bulk power rail. Each of the bi-directional switches 192-202 is configurable by the controller 42 (with which each of the switches is in communication) in an open position in which it is configured to block both positive and negative electrical signals and a closed position in which it is configured to allow electrical signals to propagate both from the three phase AC supply to the second bulk power rail 38, 40 and from the first power rail 8, 10 to the capacitors of the electromagnetic interference filter 150 by way of the second inverter 60 and the second selector 190. For example, each of the switches 192-202 may comprise back to back FETs.

[0225] The rail 2 control module 130 of the controller 42 (which is provided in communication with the switches 192-202) is configured to open and close the switches 192-202 in phased relationship with the three-phase AC supply to provide the voltage across the second bulk power rail 38, 40 with the second highest instantaneous phase-to-phase voltage of the three-phase AC supply. Again, the controller 42 (e.g. the rail 2 control module 130) uses the phase angle reference provided by the phase reference generator 110 to determine when to open and close each of the switches 192-202 so as to achieve this result.

[0226] In some embodiments, the power converter 1 has first and second modes: an AC to DC mode and a DC to AC mode. In the AC to DC mode, the power converter is configured to convert a three-phase AC supply to a DC output. In the DC to AC mode the power converter is configured to convert a DC input to a three-phase AC output. That is, it may be that the power converter 1 is a bi-directional power converter. In this case, the first selector 4 shown in FIGS. 1, 12 is also replaced with a selector which permits electrical energy to be fed back to the three-phase AC supply, the diodes 17 of the first selector 4 being unsuitable for this purpose because they are unidirectional. FIG. 13 shows a further alternative power converter where both the first selector and the second selector comprise six bi-directional switches 192-202 configured as described above with reference to FIG. 12. In this case, the controller 42 further comprises a rail 1 control module which, when the power converter is configured in AC to DC mode, is configured to open and close the switches 192-202 of the first selector in phased relationship with the three-phase AC supply to provide the voltage across the first bulk power rail 8, 10 with the highest instantaneous phase-to-phase voltage of the three-phase AC supply. The rail 2 control module 130 is again provided and configured to open and close the switches 192-202 of the second selector in phased relationship with the three-phase AC supply to provide the voltage across the second power rail 38, 40 with the second highest instantaneous phase-to-phase voltage of the three-phase AC supply. The rectifier 79 shown in FIG. 1 which is configured to rectify the combined outputs from the secondary windings 55, 61 of the first and second transformers 52, 58 is replaced with a rectifier bridge 204 comprising a plurality of switches in communication with the controller 42, the rectifier bridge 204 being configurable to operate as a rectifier (providing the same or similar functionality to rectifier 79 of the embodiment of FIG. 1) when the power converter is operating in the AC to DC mode and as a power inverter when the power converter is operating in the DC to AC mode.

[0227] When operating in DC to AC mode, the power converter is operated in reverse (i.e. right to left rather than left to right in the view of the schematic of FIG. 13) and the DC input is provided where the DC output was provided in AC to DC mode. The DC signal is then converted by the inverter to produce a high frequency AC voltage signal (e.g. at least 1 kHz, at least 10 kHz or at least 100 kHz) which can be fed to the secondary windings 55, 61 of the first and second transformers. The high frequency AC voltage signal is stepped up to the primary windings 50, 56 before being transmitted to the first and second inverter bridges 54, 60 which are in this mode configured as rectifiers so as to provide the first and second power rails 8, 10 and 38, 40.

[0228] As the rectifier bridge 204 must be capable of propagating electrical energy from the transformers 52, 58 to the DC output in the AC to DC mode, and from the DC input to the transformers 52, 58 in the DC to AC mode, the switches of the rectifier bridge 204 (e.g. configured as an H-bridge) must be bi-directional switches configurable in their “on” states to conduct electrical current in both of two opposing directions. It will be understood that, unlike the first and second selectors, the switches of the rectifier bridge 204 do not typically need to block the propagation of electrical current in the said two opposing directions when in their off states because the DC input is typically positive or negative (rather than cycling between positive and negative in the way that the three-phase AC supply does). Accordingly, each of the switches of the rectifier 204 may be implemented by, for example, single FETs.

[0229] By being operable in AC to DC mode and in DC to AC mode, the converter can draw in electrical power from the three-phase AC supply (e.g. from the grid) in the AC to DC mode to charge a DC power storage device (e.g. a battery), and in the DC to AC mode to discharge electrical power from the DC power storage device back to the three-phase AC supply (e.g. to the grid). This makes the power converter particularly suitable for renewable energy applications, particularly where the renewable energy source is unreliable, remote from users and/or has to be stored at off-peak times for use at peak times (e.g. wind, tidal or solar power).

[0230] A first capacitor 180 is connected in parallel between the first selector and the first inverter bridge, and a second capacitor 182 is connected in parallel between the second selector and the second DC to AC inverter bridge 60. These capacitors 180, 182 provide a current path for high frequency currents at or above the frequency of the respective inverters 54, 60 to minimise electromagnetic compatibility problems and reduce the voltage stress on the bridge FETs and other components. These capacitors 180, 182 will introduce an inherent harmonic current, but this can be minimised by setting the capacitance of the first capacitor 180 equal to twice the capacitance of the second capacitor 182.

[0231] In the event of a fault with the three-phase supply, it may be that the voltages across the respective first and second bulk power rails 8, 10 and 38, 40 will drop significantly. If the fault lasts for long enough, this could lead to an undesirable decrease in the current/voltage of the DC output 3. As shown in FIG. 14, in order to mitigate the risk of this situation occurring, a hold-up capacitor 210 may be coupled to, and between, the first bulk power rail 8, 10 and the second bulk power rail 38, 40. More specifically, a first plate of the hold-up capacitor 210 is connected to the first power rail portion 8 via a first diode 212 (the anode of the first diode 212 being connected to the capacitor 210 and the cathode being connected to the first power rail portion 8) and to the second power rail portion 38 via a second diode 214 which is an antiparallel diode of a first (in this case n-type) MOSFET switch (the gate voltage of which is controlled by controller 42), the anode of the second diode 214 being connected to the second power rail portion 38 and the cathode of the second diode 214 being connected to the capacitor 210, and a second plate of the capacitor 210 opposite the first plate is connected to the first return power rail portion 10 via a third diode 216 (the cathode of the third diode 216 being connected to the capacitor and the anode of the third diode 216 being connected to the first return power rail portion 10) and to the second return power rail portion 40 of via a fourth diode 218 which is an antiparallel diode of a second (in this case n-type) MOSFET switch (the gate voltage of which is controlled by the controller 42), the cathode of the fourth diode being connected to the return 40 and the anode of the fourth diode being connected to the capacitor 210.

[0232] In normal operation, assuming that the capacitor 210 is initially discharged, that the first selector provides the first power rail 8, 10 with the highest instantaneous phase to phase voltage and the second selector provides the second power rail 38, 40 with the second highest instantaneous phase to phase voltage and that the initial conditions correspond to the phase voltages at 0° in FIG. 2a, the second power rail portion 38 will have a higher voltage (provided by phase A) than the first plate (left hand plate in FIG. 14) of the capacitor 210. Accordingly, the second diode 214 is forward biased and in an “on” state. The first power rail portion 8 (also provided by phase A) will also have a higher voltage than the first plate of the capacitor 210 and so the first diode 212 is reverse biased and in an “off” state. The second return power rail portion 40 will have a lower voltage (provided by phase C) than the second plate (right hand plate in FIG. 14) of the capacitor 210, so the fourth diode 218 is forward biased and in an “on” state. The first return power rail portion 10 will have a voltage (provided by phase B) less than that of the second plate of the capacitor, so the third diode 216 will be reverse biased and in an “off” state. Accordingly, the first plate charges up towards the voltage of the second power rail portion and the second plate charges up towards the voltage of the second return power rail portion 40.

[0233] At around 15°, the voltages of the first and second power rail portions 8, 38 (both provided by phase A at this point) decrease and, because there will be a lag before the first plate of the capacitor 210 discharges in response to the reduced voltage, the voltage of the first plate of the capacitor 210 becomes greater than the voltages of the first and second power rail portions 8, 38. Accordingly, the first diode 212 becomes forward biased and turns on, while the second diode 214 becomes reverse biased and turns off. The first plate of the capacitor 210 therefore becomes connected to the first power rail portion 8 and so the voltage of the first plate follows that of the first power rail portion (provided by phase A). Meanwhile, the voltage of the second return power rail portion 40 (provided by phase C) increases and, because there will be a lag before the second plate reaches the increased voltage, the voltage of the second plate of the capacitor 210 becomes less than the voltage of the second return power rail portion 40, thereby turning off the fourth diode 218. The voltage of the second plate of the capacitor 210 remains above that of the second return power rail portion (which has decreased) and so the third diode 216 remains off.

[0234] At a phase of 30°, the second power rail portion 38 switches to phase C and the second return power rail portion 40 switches to phase B, which causes the fourth diode 218 to become forward biased and turn on. The voltage of the second plate of the capacitor therefore follows that of the second return power rail portion 40 (which at 30° is the same as the voltage of the first return power rail portion 10), thereby increasing the voltage across the capacitor 210 towards that across the first power rail.

[0235] At a phase of 60°, the first power rail portion 8 switches to phase C and the second power rail portion 38 switches to phase A. Shortly thereafter, the voltage of the first plate of the capacitor starts to increase. As that increase lags the increase in the voltage of the first power rail portion, the first diode 212 turns off. In addition, the voltages of the first and second return power rail portions 10, 40 start to increase and, because the voltage of the second plate of the capacitor 210 lags that of the first and second return power rail portions 10, 40, the third diode 216 turns on and the fourth diode 218 turns off. Thus, the second plate of the capacitor 210 continues to follow the voltage of the first return power rail portion 8.

[0236] At a phase of 90°, the second power rail portion 38 switches to phase C and the second return power rail portion 40 switches to phase A. Shortly thereafter, the voltage of the second power rail portion 38 becomes greater than the voltage of the first plate of the capacitor 210, thereby causing the second diode 214 to turn on, thereby connecting the first plate of the capacitor 210 to the second power rail portion 38 (which at 90° is the same as that of the first power rail portion 8). Meanwhile the third diode 216 remains on (connecting the second plate of the capacitor 210 to the first return power rail portion 8) and the fourth diode 218 remains off. Accordingly, the voltage across the capacitor 210 follows the voltage across the first power rail 8, 10.

[0237] At a phase of 120°, the first return power rail portion 10 switches to phase A, while the second return power rail portion 40 switches to phase B. Shortly thereafter the voltage of the first return power rail portion 10 decreases, causing the third diode 216 to turn off. The fourth diode 218 remains off. The first plate of the capacitor 210 remains connected to the second power rail portion 38 (which remains the same as that of the first power rail portion 8).

[0238] At a phase of 150°, the second power rail portion 38 switches to phase B and the second return power rail portion 40 switches to phase A. This causes the second diode 214 to turn off and, because the voltage of the first power rail portion 8 is decreasing, the voltage of the first plate of the capacitor 210 becomes greater than that of the first power rail portion 8, causing the first diode 212 to turn on and connecting the first plate of the capacitor 210 to the first power rail portion 8. As the second return power rail portion 40 is decreasing, the fourth diode 218 turns on, connecting the second plate of the capacitor 210 to the second return power rail portion 40 (which at 150° is the same as the first return power rail portion 8).

[0239] At a phase of 180°, the first power rail portion 8 switches to phase B and the second power rail portion 38 switches to phase C. Shortly thereafter, the voltage of the first power rail portion 8 increases above that of the first plate of the capacitor, thereby turning off the first diode 212. The second power rail portion 38 also decreases, so the second diode 214 remains off. The fourth diode 218 remains on (thereby connecting the second plate of the capacitor 210 to the second return power rail portion 40 which at 180° has the same voltage as the first return power rail portion 10), but shortly thereafter the voltages of the first and second return power rail portions 10, 40 increase, causing the third diode 216 to turn on and the fourth diode 218 to turn off (connecting the second plate of the capacitor to the first return power rail portion). The conditions at this stage are analogous to those at 60°, and the cycle described above between 60° and 180° then repeats during normal operation.

[0240] The capacitor is sized so that, when the first and second diodes 212, 214 are off, the first plate of the capacitor 210 does not discharge quickly relative to the frequency of the three phase AC source. Similarly, the capacitor is sized so that, when the third and fourth diodes 216, 218 are off, the second plate of the capacitor does not discharge quickly relative to the frequency of the three phase AC source. The capacitor and the diode switching circuit are thus configured to maintain the voltage across the capacitor 210 at a value greater than or equal to the minimum voltage across the first power rail during normal operation of the three phase supply.

[0241] In the event of a fault with the three-phase supply which causes the voltage of the first plate of the capacitor 210 to be greater than the voltage of the first power rail portion 8, and the voltage of the second plate of the capacitor 210 to be less than the voltage of the first return power rail portion 10, the first and third diodes 212, 216 turn on and the capacitor 210 discharges through the first positive and return power rail portions 8, 10, acting as a source of energy to supply to the DC output 3 for a finite time period (i.e. until the capacitor has discharged). In addition, the gate voltages of the MOSFETs comprising diodes 214, 218 are controlled by the controller 42 to turn on in the event of a fault to allow the holdup capacitor 210 to discharge through the second positive and return power rail portions 38, 40, acting as a source of energy to supply to the DC output 3 for a finite time period (i.e. until the capacitor has discharged).The arrangement of the hold-up capacitor 210 ensures that it does not affect any other circuitry of the power converter.

[0242] Further modifications and variations may be made within the scope of the invention herein disclosed.

[0243] For example, although the present invention has been described in terms of a power converter in which the highest and second highest phase to phase voltages of the three-phase supply are selected to provide the first and second bulk power rails 8, 38, 17 the power converter may alternatively select the highest and lowest phase to phase voltages or the second highest and the lowest phase to phase voltages to provide the first and second bulk power rails 8, 38.

[0244] In another example, MOSFETS 214, 218 may be replaced by passive diodes in which case, in the fault detection mode, the holdup capacitor discharges to the DC output through the first power rail 8, 10 but not through the second power rail 38, 40.

[0245] The present invention has been described in terms of a variety of possible topologies. The present invention may equally be applied to other possible topologies.

[0246] Any diodes provided in the circuitry discussed above may be replaced with any alternative switch (e.g. a bidirectional switch), such as a FET, in communication with the controller 42.

[0247] The required turns ratios of the first and second transformers are determined by the required input voltage and output voltage ranges. Precise ratios are not required, only that the transformers are able to provide their output windings with appropriate levels of voltage and current through the AC cycle.

[0248] Although in the embodiments described above, the first selector selects the highest instantaneous phase to phase voltage and the second selector selects the second highest instantaneous phase to phase voltage for each 360° cycle of the AC supply, in an alternative embodiment the second power rail portion 38 may be permanently tied to the highest instantaneous phase voltage and the second power rail return portion 40 may be permanently tied to the second highest instantaneous phase voltage. This means that the voltage across the second power rail 38, 40 is sometimes the second highest instantaneous phase to phase voltage, and sometimes the lowest instantaneous phase to phase voltage during a single phase cycle of the AC supply. In this case, a further capacitor may be provided between the first power rail portion 8 and the second power rail portion 38 to help reduce the harmonic content of the supply current drawn.

[0249] In another alternative embodiment, the second power rail portion 38 may be permanently tied to the second highest instantaneous phase voltage and the second power rail return portion 40 may be permanently tied to the lowest instantaneous phase voltage. This again means that the voltage across the second power rail 38, 40 is sometimes the second highest instantaneous phase to phase voltage, and sometimes the lowest instantaneous phase to phase voltage during a single phase cycle of the AC supply. In this case, a further capacitor may be provided between the first power rail return portion 10 and the second power rail return portion 40 to help reduce the harmonic content of the supply current drawn.