Field Effect Transistor and Method for Manufacturing Same

Abstract

Provided is a field effect transistor (FET) including a gate insulating film with a laminated (two-layer) structure having more improved characteristics for practical use. The FET includes a perovskite-type structure single-crystalline composite oxide substrate 1 that forms a channel layer; and a gate insulating film with a laminated structure in which para-xylylene polymer films 4 and 5 and hafnium oxide 6 are laminated in this order on the single-crystalline composite oxide substrate 1.

Claims

1. A field effect transistor comprising: a single-crystalline composite oxide substrate with a perovskite-type structure, the single-crystalline composite oxide substrate forming a channel layer; and a gate insulating film with a laminated structure in which a para-xylylene polymer film and hafnium oxide are laminated in this order on the single-crystalline composite oxide substrate.

2. The field effect transistor according to claim 1, wherein the single-crystalline composite oxide substrate is a single-crystalline strontium titanate substrate whose surface is a (100) surface, a (110) surface, or a (111) surface.

3. The field effect transistor according to claim 1, wherein the para-xylylene polymer film includes a Parylene C film.

4. The field effect transistor according to claim 3, wherein the Parylene C film has a thickness of 6 to 10 nm, and the hafnium oxide has a thickness of 20 to 30 nm.

5. A method for manufacturing a field effect transistor comprising: preparing a single-crystalline strontium titanate substrate; forming a first polymer film of para-xylylene having a first thickness on the single-crystalline strontium titanate substrate; forming openings to be a source and a drain by patterning the first polymer film; forming the source and the drain by forming a conductive film in the openings; forming a second polymer film of para-xylylene having a second thickness on the single-crystalline strontium titanate substrate on which the source and the drain have been formed; forming a hafnium oxide film on the second polymer film; and forming a gate electrode on the second polymer film between the source and the drain.

6. The manufacturing method according to claim 5, wherein the forming openings to be the source and the drain includes: forming a photomask on the first polymer film, the photomask having openings with an undercut structure, and removing the first polymer film in the openings with the undercut structure.

7. The manufacturing method according to claim 6, wherein the forming the source and the drain by forming a conductive film in the openings includes: forming a conductive film on an exposed surface of the single-crystalline strontium titanate substrate inside each opening with the undercut structure, the conductive film having a width defined by a width of an upper end of said each opening with the undercut structure, and removing the photomask.

8. The manufacturing method according to claim 7, wherein the forming the second polymer film of para-xylylene having the second thickness includes forming the second polymer film on the exposed surface of the single-crystalline strontium titanate substrate inside said each opening with the undercut structure between the conductive film and the first polymer film.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0013] FIG. 1 is a plan view (a) and cross-sectional views (b) and (c) illustrating configuration of a FET according to one embodiment of the present invention, where (a) is a SEM image, (b) is a schematic diagram, and (c) is a TEM image.

[0014] FIG. 2 is a diagram illustrating steps for manufacturing the FET according to one embodiment of the present invention.

[0015] FIG. 3 is a cross-sectional view illustrating a part of the steps for manufacturing the FET according to one embodiment of the present invention.

[0016] FIG. 4 is a diagram illustrating I.sub.D-V.sub.G (drain current vs gate voltage) characteristics of the FET according to one embodiment of the present invention in a sub-threshold region before carrier accumulation.

[0017] FIG. 5 is a diagram illustrating .sub.-n.sub. (sheet conductivity vs sheet charge density of the channel) relation of the FET according to one embodiment of the present invention in a region where carriers accumulate.

[0018] FIG. 6 is the sheet carrier density n.sub. of the channel () calculated from the Hall coefficient of the FET according to one embodiment of the present invention with respect to the gate voltage VG. The sheet carrier density n.sub. calculated from Gauss's law (dashed and single-dotted line) is also plotted with respect to the gate voltage V.sub.G for comparison.

[0019] FIG. 7 illustrates electrostatic capacitance C.sub..sup.ins and C.sub..sup.STO in the FET according to one embodiment of the present invention.

[0020] FIG. 8 depicts an energy band diagram of the FET according to one embodiment of the present invention in a state where carriers have accumulated.

[0021] FIG. 9 shows relations between the gate voltage V.sub.G and the sheet carrier density n.sub. and 1/C.sub..sup.STO for explaining that the sheet carrier density n.sub. of the channel of the FET according to one embodiment of the present invention is large.

DESCRIPTION OF EMBODIMENTS

[0022] An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating configuration of a FET 10 according to one embodiment of the present invention. (a) is a SEM image of an upper surface of the FET 10, (b) is a schematic diagram of a cross section of the FET 10, and (c) is a TEM image of a cross section of the FET 10. The FET 10 includes: a substrate 1 made of single-crystalline strontium titanate (SrTiO.sub.3) which is one of perovskite-type structure single-crystalline composite oxides and forms a channel layer; a source electrode 2 and a drain electrode 3 on a surface of the substrate 1; a gate insulating layer with a two-layer structure configured by Parylene C (poly-monochloro-para-xylylene, registered trademark) (4, 5) which is one of para-xylylene polymer films, and hafnium oxide (HfO.sub.2) 6; and a gate electrode 7. The Parylene C may be a single continuous layer. The reason why the Parylene C is illustrated as the two-layer structure in (b) of FIG. 1 will be described later.

[0023] A single-crystalline SrTiO.sub.3 substrate having a surface tilted about 0.03 degrees from (100) (hereinafter, (100) surface for simplicity) is used for the single-crystalline SrTiO.sub.3 substrate 1, for example. A single-crystalline SrTiO.sub.3 substrate having a different surface such as (110) or (111) surface may also be used for it. SrTiO.sup.3 is not the Mott insulator but a transition metal oxide, and it is a band insulator (intrinsic semiconductor) which does not naturally have an electron carrier or a hole carrier. However, SrTiO.sub.3 is a transition metal oxide with which an exceptionally pure and large single crystal can be fabricated, and a single-crystalline substrate having a flat surface at atomic level are widely supplied (commercially). In addition, SrTiO.sub.3 is an oxide which is very prone to the formation of surface defects, and its problems regarding FET fabrication are very similar to those of the Mott insulators which is prone to the formation of surface defects. Hence, a single-crystalline SrTiO.sub.3 substrate is used in the present invention.

[0024] A metal material such as titanium (Ti) or aluminum (Al) having a thickness of 10 nm is used for the source electrode 2 and the drain electrode 3, for example. The Parylene C (4, 5) has a thickness of 6 nm as a whole, for example. In this case, each of the lower layer 4 and the upper layer 5 may have a thickness of 3 nm, for example. One of new findings/features according to the present invention is that the thickness of the Parylene C (4, 5) can be reduced to about 6 nm. The Parylene C is deposited on a (100) surface of the single-crystalline SrTiO.sub.3 substrate for protecting the surface of the single-crystalline SrTiO.sub.3 which is a material that oxygen deficiency easily occurs on its surface when an electric field is applied, and the Parylene C protection prevents the surface deterioration during a photolithography process for fabricating the FET, and further prevents electro-chemical reactions or oxygen deficiency when an electric field is applied to the (100) surface for driving the completed FET.

[0025] The hafnium oxide (HfO.sub.2) 6 may have a thickness of approximately 20 nm to 30 nm, for example. As shown in (c) of FIG. 1, the thin Parylene C with a thickness of about 6 nm exists between the single-crystalline SrTiO.sub.3 substrate 1 and the hafnium oxide (HfO.sub.2) 6, so that mixing of devices does not occur between the hafnium oxide (HfO.sub.2) and the SrTiO.sub.3 even if gate electric field is continuously applied. The gate electrode 7 on the hafnium oxide (HfO.sub.2) 6 may be a single layer of gold (Au) or a two-layer structure configured by titanium (Ti) and gold (Au), for example.

[0026] A method for manufacturing the FET 10 according to one embodiment of the present invention will be described with reference to FIGS. 2 and 3. FIG. 2 is a diagram illustrating steps for manufacturing the FET according to one embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a part of the steps for manufacturing the FET according to one embodiment of the present invention. Step S1 in FIG. 2 is a step for preparing the single-crystalline SrTiO.sub.3 substrate 1 on which the channel of the FET is to be formed. A single-crystalline SrTiO.sub.3 substrate having a step and terrace structure and a (100) surface with a miscut angle of 0.03 degrees or smaller is used for the single-crystalline SrTiO.sub.3 substrate 1, for example.

[0027] Step S2 is a step for forming the first polymer film of para-xylylene having the first thickness on the surface of the single-crystalline SrTiO.sub.3 substrate 1. Specifically, the Parylene C polymer film 4 with a thickness of 3 nm is formed as mentioned earlier, for example. For example, the forming is performed as follows. First, the single-crystalline SrTiO.sub.3 substrate 1 is placed in a vacuum chamber which is then set to a vacuum of 5 mTorr or lower. A dimer of Parylene is heated at 135 C. to be sublimated, and its gas is passed through a furnace at 690 C. to be monomerized, and then introduced into the chamber which is maintained at a vacuum of 5 mTorr or lower. Inside the chamber, the Parylene C is polymerized at the surface of the single-crystalline SrTiO.sub.3 substrate 1 so that the Parylene C polymer film 4 is formed. The thickness of the actually formed Parylene C is measured with a film thickness measurement apparatus F20-UV by Filmetrics Japan, Inc. and also observed by using a transmission electron microscope (TEM), for example.

[0028] Step S3 is a step for patterning the first polymer film to form openings to be the source and drain electrodes. Specifically, first, a photoresist (SIPR-9684-1.5 by Shin-Etsu Chemical Co., Ltd.) 12 is coated on the Parylene C polymer film 4. Then, the photoresist 12 on the Parylene C polymer film 4 is patterned for the source and drain electrodes by a photolithography method using an i-line stepper UTS-1700 by Ultratech, Inc. In this case, the photoresist 12 is patterned to have trapezoidal openings in cross section, in other words, openings with an undercut structure, as illustrated in (a) of FIG. 3. This is to avoid burrs sticking from an edge of each source/drain electrode (metal) to be formed later. Then, the Parylene C polymer film inside each opening is selectively removed by irradiating it with vacuum ultraviolet light within ozone plasma. One cross section after the removal of the Parylene C polymer film is illustrated in (b) of FIG. 3.

[0029] Step S4 is a step for forming the source and drain electrodes. Specifically, as illustrated in (c) of FIG. 3, vacuum vapor deposition of Ti to a thickness of 10 nm or Al to a thickness of 10 nm, for example, is performed from above the photomask 12 having the openings with the undercut structure. For Al, it is placed in an alumina crucible and vapor-deposited at 1 nm/s by resistive heating. For Ti, it is vapor-deposited at 0.1 nm/s by electron beam heating. The width of the electrode 2 (3) is determined based on the opening size of the opening at the upper end with the undercut structure. Although only one electrode is illustrated in (c) of FIG. 3, similar electrodes are formed for the source and drain electrodes. After the source and drain electrodes have been formed, the photoresist (photomask) 12 is removed by lift off. A cross section after the removal is illustrated in (d) of FIG. 3. There is a surface of the single-crystalline SrTiO.sub.3 substrate 1, which is exposed around the electrode 2 (3).

[0030] Step S5 is a step for forming a second polymer film of para-xylylene having a second thickness on the single-crystalline SrTiO.sub.3 substrate 1 on which the source and drain electrodes have been formed. Specifically, the Parylene C polymer film 5 with a thickness of 3 nm is formed by a similar method to step S2. In this case, as illustrated in (e) of FIG. 3, the Parylene C polymer film 5 is formed in conformal shape on the electrode 2 (3). The Parylene C polymer film is formed in step S5 in addition to step S2, because it is necessary to protect the exposed surface of the single-crystalline SrTiO.sub.3 substrate 1 illustrated in (d) of FIG. 3. As illustrated in (b) of FIG. 1, a total thickness of the Parylene C polymer film in a region between the source electrode and the drain electrode is 6 nm as a result of these two forming steps. The Parylene C polymer film may have a thickness of approximately 6 to 10 nm in total.

[0031] Step S6 is a step for forming a hafnium oxide film (HfO.sub.2) on the second polymer film 5. Specifically, as illustrated in (b) of FIG. 1, a thin film of HfO.sub.2 6 with a thickness of 20 nm is deposited using an atomic layer deposition apparatus (ALD) SUNALE R-100B by Picosun, for example. TDMAH (Hf[N(CH.sub.3).sub.2].sub.4) may be used as a precursor of Hf in the deposition. The 20-nm thin HfO.sub.2 film may be formed by heating the single-crystalline SrTiO.sub.3 substrate at 120 C. in the vacuum chamber and introducing TDMAH at 130 C. and deionized purified water (H.sub.2O) for 169 cycles. The film thickness of HfO.sub.2 may be measured in a simple manner with a profiler AlphaStep D-100 by KLA-Tencor Corporation and also checked through the measurement with TEM, for example.

[0032] Step S7 is a step for forming a gate electrode on the second polymer film in the region between the source electrode and the drain electrode. Specifically, the gate electrode 7 may be formed in the following manner: using a photolithography method similar to step S3, a photoresist pattern of the gate electrode is formed, a 5-nm Ti film and a 500-nm Au film are vapor-deposited (the vapor deposition rate is 0.1 nm/s for Ti and 5 nm/s for Au) by electron beam heating, and then the photoresist is lifted off. In addition, moisture is removed by heating at 120 C. for one hour in the atmosphere, for example, and thereafter characteristics such as electrical conductivity is evaluated. The FET illustrated in FIG. 1 is formed by steps S1 to S7 described above.

[0033] Next, the characteristics of the FET with the configuration illustrated in FIG. 1 which is actually fabricated by using the steps in FIGS. 2 and 3, will be described with reference to FIGS. 4 to 9. FIG. 4 is the I.sub.D-V.sub.G (drain current vs gate voltage) characteristics of the FET according to one embodiment of the present invention in a sub-threshold region before the carrier accumulation. As shown in FIG. 4, in the sub-threshold region before the carrier accumulation, a reciprocal (sub-threshold swing S) for a gradient obtained from a semi-log plot of the I.sub.D-V.sub.G curve is approximately 170 mV/decade (channel width L=20 m). The theoretically smallest value of S is 60 mV/decade at room temperature. Normally, S is larger than 60 mV/decade, because electrostatic capacitance C.sub..sup.STO of the channel material per unit area is not negligibly small as compared to electrostatic capacitance C.sub..sup.ins of the gate insulator per unit area.

[0034] In a simple FET with a silicon channel, S at room temperature is about 100 mV/decade. There is no report that S of a FET configured by using a composite oxide such as SrTiO.sub.3 for its channel reaches 250 mV/decade or smaller. Thus, considering that the channel is made of SrTiO.sub.3, it may be seen that S of the FET fabricated this time is surprisingly small. This means that there are almost no unnecessary carriers due to oxygen deficiency and the like in the SrTiO.sub.3 channel. Furthermore, as increasing the gate voltage applied to the SrTiO.sub.3 channel, the channel is metalized due to an increase in accumulated carriers. Calculated carrier mobility at this moment is approximately 11 cm.sup.2/Vs (10.9 cm.sup.2/Vs to be precise), as shown in FIG. 5.

[0035] Here, FIG. 5 shows the .sub.-n.sub. (sheet conductivity vs sheet carrier density) relation of the FET according to one embodiment of the present invention in the accumulation region. Sheet carrier charge density n.sub. in FIG. 5 is derived by measuring the Hall effect. There has been no report that the carrier mobility of a FET configured by using a composite oxide such as SrTiO.sub.3 for its channel, exceeds 10.9 cm.sup.2/Vs at room temperature. This indicates that the channel is close to the ideal state without a trap or scattering due to oxygen deficiency or structural misalignment.

[0036] FIG. 6 is obtained by plotting the sheet carrier density n.sub.o (o) of the channel calculated from the Hall coefficient of the FET according to one embodiment of the present invention with respect to the gate voltage V.sub.G. A relative diagram of sheet carrier density calculated from Gauss's law n.sub.=C.sub..sup.insV.sub.G/e (dashed and single-dotted line) is also plotted against the gate voltage V.sub.G as a comparative example. The observed sheet carrier density reaches to the order of 10.sup.14/cm.sup.2, which is approximately 10 or more times larger than the sheet carrier density calculated from Gauss's law (dashed and single-dotted line).

[0037] FIG. 7 is an illustrative representation of the electrostatic capacitance C.sub..sup.ins and C.sub..sup.STO in the FET according to one embodiment of the present invention. As illustrated in FIG. 7, since the electrostatic capacitance C.sub..sup.ins and C.sub..sup.STO are connected in series, C.sub..sup.ins of the Gauss's low n.sub.=C.sub..sup.insV.sub.G/e should be replaced with (1/C.sub..sup.ins+1/C.sub..sup.STO).sup.1 in actuality. However, since C.sub..sup.ins>(1/C.sub..sup.ins+1/C.sub..sup.STO).sup.1, this cannot explain the 10 or more times enhancement of the sheet carrier charge density n.sub.. It has been checked that C.sub..sup.ins remains unchanged during measurement. Hence, in order for the observed sheet carrier density n.sub.o to exceed that calculated from n.sub.=(1/C.sub..sup.ins+1/C.sub..sup.STO).sup.1V.sub.G/e, C.sub..sup.STO<0 is necessary.

[0038] FIG. 8 illustrates an energy band diagram of the FET according to one embodiment of the present invention in the accumulation state. As illustrated in FIG. 8, both sides of a relational equation of the gate voltage V.sub.G and voltage drop V.sub.ins inside the gate insulator and chemical potential /e

V.sub.G=V.sub.ins+/e (1)

are differentiated with n.sub. to thereby obtain

[00001]$\begin{array}{cc}\mathrm{Math}..Math.1& \\ \frac{1}{e}.Math.\frac{{\mathrm{dV}}_G}{{\mathrm{dn}}_{}}=\frac{1}{e}.Math.\frac{{\mathrm{dV}}_{\mathrm{ins}}}{{\mathrm{dn}}_{}}+\frac{1}{e^2}.Math.\frac{d.Math..Math.}{{\mathrm{dn}}_{}}.& \left(2\right)\end{array}$

[0039] Thus, the following is obtained.

[00002]$\begin{array}{cc}\mathrm{Math}..Math.2& \\ \frac{1}{C_{}}=\frac{1}{C_{}^{\mathrm{ins}}}+\frac{1}{C_{}^q}& \left(3\right)\end{array}$

[0040] Here, the following holds true.

[00003]$\begin{array}{cc}\mathrm{Math}..Math.3& \\ \frac{1}{C_{}^q}=\frac{1}{e^2}.Math.\frac{d.Math..Math.}{{\mathrm{dn}}_{}}& \left(4\right)\end{array}$

[0041] Then, in order for this to be negative, the following must be satisfied.

[00004]$\begin{array}{cc}\mathrm{Math}..Math.4& \\ \frac{d.Math..Math.}{{\mathrm{dn}}_{}}<0& \left(5\right)\end{array}$

[0042] Normally, as the carrier concentration increases, the chemical potential /e rises. However, in a case where the density of states changes with change in carrier concentration (a case where the Mott gap is closed or the Rashba effect is present), the chemical potential may decrease. In this case, a negative electrostatic capacitance appears. FIG. 9 is a diagram illustrating the relations between the gate voltage VG and the sheet carrier density n.sub. and 1/C.sub..sup.STO for explaining the large enhancement of the sheet carrier density no of the channel of the FET according to one embodiment of the present invention. As illustrated by the lower graph (solid line) in FIG. 9, if the electrostatic capacitance of SrTiO.sub.3 (1/C.sub..sup.STO, solid line) changes from positive values to negative values, the huge enhancement of the sheet carrier density n.sub. (white circles ()) plotted in FIG. 6 can be well explained, as illustrated by the upper panel of FIG. 9.

[0043] An embodiment of the present invention has been described with reference to the drawings. However, the present invention is not limited to this embodiment. Furthermore, the present invention can be carried out in modes with various modifications, corrections, and changes based on the knowledge of those skilled in the art without departing from the gist of the invention.

INDUSTRIAL APPLICABILITY

[0044] The FET of the present invention is usable as a constituent device of various integrated circuits (IC, LSI, etc.).

REFERENCE SIGNS LIST

[0045] 1 single-crystalline strontium titanate (SrTiO.sub.3) substrate

[0046] 2, 3 source or drain electrode (source/drain electrode)

[0047] 4, 5 para-xylylene polymer film (Parylene C)

[0048] 6 hafnium oxide (HfO.sub.2)

[0049] 7 gate electrode

[0050] 10 field effect transistor (FET)

[0051] 12 photoresist (photomask)