PIEZOELECTRIC MICROPHONE WITH DEFLECTION CONTROL AND METHOD OF MAKING THE SAME

Abstract

A method of forming a piezoelectric microphone with an interlock/stopper and a micro-bump and a resulting device are provided. Embodiments include forming a membrane over a Si substrate having a first and second sacrificial layer disposed on opposite surfaces thereof, the membrane being formed on the first sacrificial layer, forming a first HM over the membrane, forming first and second vias through the first HM, forming a first pad layer in the first and second vias and over an exposed top thin film, forming a trench to the first sacrificial layer between the first and second vias and a gap between the trench and second via, patterning a second HM over the membrane, in the first and second vias, the trench and the gap, and forming a second pad layer over the second HM and in exposed areas around the first and second vias to form pad structures.

Claims

1. A method comprising: forming a membrane over a silicon (Si) substrate having a first and second sacrificial layer disposed on opposite surfaces thereof, the membrane being formed on the first sacrificial layer; forming a first hardmask (HM) over the membrane; forming first and second vias through the first HM and partially through the membrane exposing a portion of a top thin film surrounding each via; forming a first pad layer in the first and second vias and over the exposed top thin film; forming a trench to the first sacrificial layer between the first and second vias and a gap between the trench and second via; patterning a second HM over the membrane, in the first and second vias, the trench and the gap and to expose areas of the first pad layer around the first and second vias; and forming a second pad layer over the second HM and in the exposed areas around the first and second vias to form pad structures.

2. The method according to claim 1, wherein the membrane is formed by: forming a seed layer over the first sacrificial layer; patterning a bottom metal thin film over the seed layer; patterning a middle metal thin film over a first device layer; forming the top metal thin film over a second device layer; and forming a passivation layer over the top metal thin film.

3. The method according to claim 2, wherein the second HM is patterned by planarizing the HM to a thickness of 100 nm to 1000 nm and then etching the HM to form the second gap and to expose the areas of the first pad layer around the first and second vias.

4. The method according to claim 1, comprising: forming the first pad layer to a thickness of 0.1 ?m to 0.2 ?m and the second pad layer is formed to a thickness of 200 nm to 2000 nm.

5. The method according to claim 1, comprising: patterning the second HM forming a gap adjacent to the area exposed around the second via such that a first pad structure is formed over the first via, a second pad structure is formed over the second via and a third pad structure is formed adjacent to the second via.

6. The method according to claim 5, further comprising: patterning the second HM forming a second gap between the first via and the trench extending down to the top thin film such that the second pad layer is also formed in the second gap to form an interlock/stopper structure that extends from the gap and over the trench and a portion of the membrane.

7. The method according to claim 6, further comprising: forming a HM over the second pad layer to a thickness of 1 ?m to 5 ?m; removing the second sacrificial layer from the Si substrate; and forming a second trench through a middle of the Si substrate and through part of the first sacrificial layer below the first trench.

8. The method according to claim 7, further comprising: removing all the HM by a process of vapor hydrofluoric acid (VHF) etching.

9. The method according to claim 6, wherein the forming of the second pad layer includes patterning the second pad layer and then etching the second pad layer down to the second HM.

10. The method according to claim 2, wherein: the seed layer is formed of aluminum nitride (AlN), the metal thin films are formed of molybdenum (Mo), titanium (Ti), platinum (Pt), oraluminum (Al), the seed layer having a thickness of 20 nanometers (nm) to 200 nm, the metal thin films having a thickness of 20 nm to 200 nm, first and second device layers having a thickness of 100 nm to 1000 nm, and the passivation layer having a thickness of 20 nm to 200 nm.

11. A method comprising: forming a membrane for a piezoelectric microphone on a sacrificial layer covering a silicon (Si) substrate; forming a first hardmask (HM) over the membrane; forming first and second vias through the first HM and partially through the membrane, a gap and an area around the first and second vias, the gap and areas around the first and second vias extending through the first HM to the membrane; patterning a first pad layer in the first and second vias and over the areas formed around the vias and to form a bump structure in the gap; forming a trench through the membrane to the first sacrificial layer between the first via and the bump structure; patterning a second HM across the membrane in the first and second vias, the trench and over the bump structure such that portions of the first pad layer around the first and second vias are exposed; and forming a second pad layer over the exposed portions of the first pad layer to form pad structures.

12. The method according to claim 11, comprising: forming the first pad layer to a thickness of 0.1 ?m to 0.2 ?m, forming the bump structure to a thickness of 0.1 ?m to 0.2 ?m, and forming the second pad layer to a thickness of 200 nm to 2000 nm.

13. The method according to claim 12, wherein the step of forming the trench through the membrane between the first via and the first gap further includes forming a second gap between the first gap and the second via extending through a top metal thin film of the membrane.

14. The method according to claim 11, comprising: patterning the second HM to form a second gap between the first via and the trench, and forming the second pad layer in the second gap to form an interlock/stopper structure that extends from the second gap and over the bump structure.

15. The method according to claim 11, wherein the second HM is patterned by planarization to 0.1 micrometers (?m) to 0.5 ?m in height and then etched to expose the portions of the first pad layer around the first and second vias.

16. A device comprising: a structure including a silicon (Si) layer and a sacrificial oxide layer on one side of the Si layer and a membrane having a seed layer, metal thin films, device layers, a passivation layer and a trench through the middle thereof; first and second seal ring and cap structures extending into the membrane and separated by a predetermined distance; a trench extending through the membrane between the first and second seal structures; a bond pad adjacent to and in contact with the second seal ring and cap structure; and an interlock/stopper extending from the membrane between the trench and the first seal ring and cap structure, over the trench and over a portion of the membrane.

17. The device according to claim 16, wherein the portion of the interlock/stopper extending over the membrane is separated from the membrane by a gap of 0.1 ?m to 0.5 ?m.

18. The device according to claim 17, further comprising: a bump structure extending from the membrane and disposed under the interlock/stopper structure between the trench and the second seal ring and cap structure.

19. The device according to claim 18, wherein: the first seal ring and cap structures extend through the passivation layer, a third metal thin film and a first section of a second metal thin film to contact a first section of a first metal thin film, the seal ring and cap structure having an oxide disposed therein, and the second seal ring and cap structure extends through the passivation layer and the third metal thin film to extend to a third section of the second metal thin film.

20. The device according to claim 16, wherein: the first and second seal ring and cap structures are formed to a thickness of 200 nm to 2000 nm and are formed of aluminum copper (AlCu), and the bump structure is formed of AlCu and has a thickness of 0.1 ?m to 0.2 ?m.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

[0020] FIG. 1 schematically illustrates a cross-sectional view of a conventional piezoelectric microphone;

[0021] FIGS. 2 through 21 schematically illustrate cross-sectional views of fabrication process steps for a piezoelectric microphone device in accordance with an exemplary embodiment;

[0022] FIGS. 22 and 23 schematically illustrate cross-sectional views of fabrication process steps for a piezoelectric microphone device in accordance with another exemplary embodiment;

[0023] FIG. 24 illustrates a top view of a membrane and vias of a piezoelectric microphone according to an exemplary embodiment of the present disclosure;

[0024] FIG. 25A illustrates an enlarged top view of a portion of FIG. 24 illustrating the vias;

[0025] FIG. 25B illustrates another view of FIG. 25A with seal rings disposed around the vias; and

[0026] FIG. 25C illustrates another view of FIG. 25B with metal caps disposed over the seal rings to form a seal ring/metal cap structure.

DETAILED DESCRIPTION

[0027] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term about.

[0028] The present disclosure addresses and solves the current problem of limited control of a piezoelectric microphone attendant upon released device deflection mismatch in a gap between a bridge and a membrane thereof. The present disclosure also addresses and solves the current problem of preventing stiction from occurring with a bridge and membrane thereof. In accordance with embodiments of the present disclosure, a piezoelectric microphone is formed with an interlock/stopper structure on top of a membrane. Also in accordance with an embodiment of the present disclosure, a piezoelectric microphone can be formed with a micro-bump structure underneath an interlock/stopper. Also in accordance with an embodiment of the present disclosure, a piezoelectric microphone can be formed using fewer hardmasks to target a gap thickness between a bridge and a membrane thereof.

[0029] Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

[0030] FIGS. 2 through 21 schematically illustrate cross-sectional views of a process flow for forming a piezoelectric microphone device with an interlock/stopper structure above a membrane, in accordance with an exemplary embodiment. FIGS. 22 and 23 schematically illustrate cross-sectional views of a process flow for forming a piezoelectric microphone with an interlock/stopper structure above a membrane and a micro bump structure on the membrane under the interlock/stopper, in accordance with another exemplary embodiment of the present disclosure.

[0031] As illustrated in FIG. 2, a silicon (Si) layer 201 is provided with a sacrificial layer 203a formed on a front side 201a and a sacrificial layer 203b formed on a back side 201b thereof. The sacrificial layers 203a and 203b may be formed of an oxide formed to a thickness of 0.5 micrometers (?m) to 5 ?m. Further, the sacrificial layers 203a and 203b may be formed, for example, by oxidation or by a plasma enhanced chemical vapor deposition (PECVD) process.

[0032] Adverting to FIG. 3, a seed layer 305 can be formed on the oxide layer 203a on the front side 201a of the silicon (Si) layer 201. The seed layer 305 can be formed of, for example, aluminum nitride (AlN). The seed layer 305 is formed to a thickness of 20 nanometers (nm) to 200 nm. The seed layer 305 may be formed, for example, by a sputtering deposition process. A first metal thin film 307 can be formed on the seed layer 305 to a thickness of 20 nm to 200 nm. The first metal thin film 307 may be formed of, for example, Mo, Ti, Pt, or Al, and may be applied by a sputtering or a physical vapor deposition (PVD) process.

[0033] As illustrated in FIG. 4, the first metal thin film 307 can be patterned to form a first metal thin film section 307a and a second metal thin film section 307b. The first metal thin film section 307a and second thin film section 307b will act as a bottom electrode.

[0034] As illustrated in FIG. 5, a first device layer 505 can be formed over the first metal thin film section 307a and the second metal thin film section 307b. The first device layer 505 is formed to a thickness of 100 nm to 1000 nm. The first device layer 505 may be formed, for example, by a sputtering or physical vapor deposition process. A second metal thin film 507 is deposited on the first device layer 505.

[0035] As illustrated in FIG. 6, the second metal thin film 507 can be patterned to form a first metal thin film section 507a, a second metal thin film section 507b and a third metal thin film section 507c. The second metal thin film 507 can be patterned, for example, by an etching process. The remaining pattern of the second metal thin film 507, including metal thin film sections 507a, 507b and 507c, will act as a middle electrode.

[0036] As illustrated in FIG. 7, a second device layer 705 can be formed over the metal thin film sections 507a, 507b and 507c. The second device layer 705 is formed to a thickness of 100 nm to 1000 nm. The second device layer 705 may be formed, for example, by a sputtering or physical vapor deposition process. A third metal thin film 707 can be formed on the second device layer 705 to a thickness of 20 nm to 200 nm, followed by a passivation layer 709 formed on the third metal thin film 707. The passivation layer 709 can be formed of, for example, AlN. The second device layer 705, the third metal thin film 707 and the passivation layer 709 can be formed, for example, by atomic layer deposition or a sputtering process. The seed layer, metal thin films, device layers, and passivation layer form membrane 711.

[0037] Adverting to FIG. 8, a hardmask 803 can be formed on the passivation layer 709 to a thickness of 10 nm to 500 nm. The hardmask 803 can be formed of, for example, plasma tetra ethyl oxysilane (PTEOS). Next, a first via 809 can be formed. The first via 809 can be formed by etching through the hardmask 803, through the passivation layer 709, through the third metal thin film 707 and partially through the second device layer 705.

[0038] As illustrated in FIG. 9, a second via 911 can be formed. The second via 911 may be formed by etching through the hardmask 803, the passivation layer 709, the third metal thin film 707, the second device layer 705, metal thin film section 507a and partially through the first device layer 505. As a result of forming the first and second vias 809 and 911, the third metal thin film 707 is divided into a first section 707a, a second section 707b and a third section 707c.

[0039] Adverting to FIG. 10, using a mask (not shown for illustrative convenience), portions of the hardmask 803 around the first and second vias 809 and 911 are etched down to the passivation layer 709. A wet etch is then performed to extend the first via 809 down to metal thin film section 507c and to extend the second via 911 down to metal thin film section 307a. This process exposes portions of metal thin film sections 707a and 707b surrounding the via 911 and portions of metal thin film sections 707b and 707c surrounding the first via 809. As a result, the hardmask 803 can be separated into sections 803a and 803b while the passivation layer 709 can be separated into sections 709a and 709b.

[0040] During this etching process the first device layer 505, second device layer 705, and passivation layer 709 can be etched with another etching process different from the etching process used to remove the hardmask 803. For example, wet etching the first device layer 505, second device layer 705 and 705 can be performed by using a tetramethyl ammonium hydroxide (TMAH) based developer. As a result, sections of the passivation layer 709 including sections 709a and 709b remain on metal thin film sections 707b and 707c, respectively, and sections 803a and 803b of the hardmask 803 remain on sections 709a and 709b of the passivation layer 709, respectively. Sections 803a and 709a are of the same length and sections 803b and 709b are also of the same length, as illustrated in FIG. 10. However, sections 803a and 709a and sections 803b and 709b can vary in length.

[0041] As illustrated in FIG. 11, a pad layer 1113 can be formed in the vias 809 and 911 and over the surface of the membrane 711 including section 803a and section 803b. The pad layer 1113 can be formed of, for example, AlCu. The pad layer 1113 is formed to a thickness of 0.1 micro-meter (?m) to 0.2 ?m. The pad layer 1113 can be formed by a deposition process.

[0042] Next, while outer edges of hardmask section 803a are masked and section 803b is masked the rest of the hardmask section 803a remains exposed. Using the mask, the pad 1113 is removed only from the exposed portion of hardmask section 803a. The pad 1113 can be removed, for example, by an etching process.

[0043] Adverting to FIG. 12, the hardmask 803 is patterned to expose a first portion of hardmask section 803a and a second portion of hardmask section 803a. Then the exposed first and second portions of the hardmask section 803a are removed. As a result, portions of the passivation layer 709a and portions of metal thin film section 707b directly under the removed first and second portions of the hardmask section 803a are also removed, leaving a gap 1201 and a gap 1203 exposing the second device layer 705. This removal process can be performed, for example, by an etching process. As a result of this removal process, the passivation layer 709a is separated into section 709a1, section 709a2 and section 709a3. In addition, section 803a of the hardmask is separated into section 803a1, section 803a2 and section 803a3, and thin film section 707b is further separated into section 707b1, section 707b2 and section 707b3.

[0044] Adverting to FIG. 13, section 803a1, section 803a2 and section 803a3 are patterned to expose the gap 1201. Then a trench 1305 can be formed within the gap 1201 down to the oxide layer 203. More specifically, the trench 1305 can extend through the second device layer 705, between metal thin film sections 507b and 507c, through the first device 505, between the metal thin film sections 307a and 307b and through the seed layer 305.

[0045] Adverting to FIG. 14, a second hardmask 1403 can be formed in the vias 809 and 911 and the trench 1305 and over the entire surface of the membrane 711 to a thickness of 1 ?m to 5 ?m. This second hardmask 1403 can be formed, for example, by a deposition process.

[0046] Adverting to FIG. 15, the second hardmask 1403 is reduced to a thickness of 100 nm to 1000 nm. When the hardmask 1403 is formed of PTEOS, it can be reduced by an oxide planarization process. The oxide planarization process can be performed, for example, by chemical-mechanical planarization (CMP) or an etch back process.

[0047] Adverting to FIG. 16, the second hardmask 1403 is patterned to expose a plurality of areas therein. The exposed areas of the second hardmask 1403 are then removed to form gaps 1601, 1603, 1605 and 1607. Gaps 1601 and 1605 surround the first and second vias, respectively. The exposed areas can be removed by an etching process. Gaps 1601 and 1605 extend down to the pad 1113, gap 1603 extends down to thin film section 707b1, and gap 1607 extend down to the pad layer 1113. The exposed areas of the second hardmask 1403 can be removed to form the gaps the 1601, 1603, 1605 and 1607 by an etching process.

[0048] Adverting to FIG. 17, a pad layer 1713 can be formed over the second hardmask 1403 and in the gaps 1601, 1603, 1605 and 1607 to cover entire membrane 711 (portions of pad layer 1713 are not shown to illustrate the etching process described below). The pad layer 1713 can be formed using a metal pattern (not shown for illustrative convenience). The pad layer 1713 is formed to a thickness of 200 nm to 2000 nm. Then another mask (not shown for illustrative convenience) is used to remove part of the pad layer 1713 down to the second hardmask 1403. As a result of this selective removal using the mask, four pad layer structures 1715, 1717, 1719 and 1721 remain extending above the second hardmask 1403. The mask used here can be a metal pattern mask that is applied to provide for etching grooves 1717a and 1721a in the second and fourth structures 1717 and 1721.

[0049] As illustrated in FIG. 18, a hardmask 1803 is formed over the entire front surface of the structure illustrated in FIG. 17. The hardmask 1803 is formed to a thickness of 1 ?m to 5 ?m and can be formed of an oxide such as PTEOS. The hardmask 1803 can be formed, for example, by sputter deposition process.

[0050] Adverting to FIG. 19, while the front side of the structure (the hardmask 1803) is taped (not shown for illustrative convenience), the oxide layer 203 on the back side of the Si 201b (see FIG. 2) is removed and the remaining silicon 201, from the back side 201b, is thinned to a thickness of 300 um to 400 ?m. The oxide layer 203 and part of the Si 201 can be removed by a CMP process. After part of the Si is removed from the back side 201b, another mask can be formed over the back of the Si 101b to expose a portion thereof.

[0051] Adverting to FIG. 20, the exposed portion of the Si 201b is etched to the oxide layer 203 on the front side of the Si 201a or partially gouging into the oxide layer 203.

[0052] Adverting to FIG. 21, the hardmask 1403 is removed to result in a piezoelectric microphone with an interlock/stopper structure 1717 as well as a first seal ring 1715a and cap 1715b structure 1715 and a second seal ring 1719a and cap 1719b structure 1719 and a bond pad 1721. The hardmask 1403 can be removed by using, for example, a vapor hydrofluoric (VHF) acid step, which can remove silicon and oxide from around metal parts. The seal ring and cap structures 1715 and 1719 formed as described above, with the hardmask formed therein, protects the vias and the thin film layers connected thereto from vapor hydrofluoric acid etching when removing the hardmask, and also protects the vias from the environment around them during operation.

[0053] Adverting to FIG. 22, according to another embodiment of the present disclosure, during the application of the mask applied over hardmask 803 (described above with reference to FIG. 10), an alternative mask with an additional exposed portion of section 803a can be applied. Then during the process of removing the exposed portion of section 803a surrounding the first via 809 and the second via 911, and removing the portion of section 709a disposed under the exposed portions of section 803a, and removing the exposed portion of section 803a surrounding the second via 911 and the portion of section 709a thereunder, as described above and illustrated in FIG. 10, and prior to depositing the pad layer 1113 as illustrated in FIG. 11, a bump gap 2205 can be formed in the additional exposed portion of the hardmask section 803a and the portion of second 709a thereunder.

[0054] More specifically, during the etching process of vias 809 and 911 as described above with reference to FIG. 10, an additional exposed portion of section 803a can be removed with a portion of section 709a disposed thereunder to expose a portion of section 707b, leaving the bump gap 2505. Then a mask can be applied to form a bump pattern in the bump gap 2505. Next, during the deposition of the pad layer 1113, as described above with reference to FIG. 11, the bump gap 2205 with the mask bump pattern disposed thereover is also filled with the pad layer 1113 to a thickness of 0.1 to 0.2 ?m, thus forming micro-bumps 2207 in the bump gap 2205.

[0055] Adverting to FIG. 23, in accordance with the embodiment described with reference to FIG. 22, the resulting piezoelectric microphone of FIG. 21 will also include a micro-bump structure 2207 disposed underneath the interlock/stopper structure 1717 to prevent potential stiction of the interlock/stopper structure 1717 and membrane 711 during operation of the device.

[0056] FIG. 24 illustrates a top view of an example of a membrane 711 and vias (i.e., 911) of a piezoelectric microphone according an embodiment of the present disclosure.

[0057] FIG. 25A illustrates an enlarged top view of a portion of FIG. 24 within the dotted line box A showing the vias (i.e., via 911) before a seal ring and metal cap structure are provided thereon.

[0058] FIG. 25B illustrates another view of FIG. 25A with seal rings (i.e., 1715a) disposed around the vias (i.e., 911).

[0059] FIG. 25C illustrates another view of FIG. 25B with metal caps (i.e., 1715b) disposed over the seal rings (i.e., 1715a) to form the seal ring and metal cap structure (i.e., 1715).

[0060] The embodiments of the present disclosure can achieve several technical effects, including providing a piezoelectric microphone with a released device deflection mismatch that can be controlled to be less than a gap thickness between a membrane and an interlock/stopper, preventing potential stiction of the microphone during operation, and defining a gap between an interlock/stopper and a membrane while using less hardmasks to target the gap thickness. The present disclosure enjoys industrial applicability in any of acoustic leakage probes and in aeroacoustic tests, as well as many other uses not confined to air.

[0061] In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.