Method for Producing an Optoelectronic Semiconductor Component and Optoelectronic Semiconductor Component

Abstract

In an embodiment a method includes arranging a plurality of semiconductor chips on a carrier, arranging an auxiliary carrier on sides of the semiconductor chips facing away from the carrier, removing the carrier, separating the auxiliary carrier between the semiconductor chips to form auxiliary carrier-chip units, each of the auxiliary carrier-chip units has at least one semiconductor chip and an auxiliary carrier part adjoining the semiconductor chip, arranging each of the auxiliary carrier-chip units on a connecting carrier and removing the auxiliary carrier parts from each auxiliary carrier-chip unit.

Claims

1.-19. (canceled)

20. A method for producing an optoelectronic semiconductor component, the method comprising: arranging a plurality of semiconductor chips on a carrier; arranging an auxiliary carrier on sides of the semiconductor chips facing away from the carrier; removing the carrier; separating the auxiliary carrier between the semiconductor chips to form auxiliary carrier-chip units, each of the auxiliary carrier-chip units has at least one semiconductor chip and an auxiliary carrier part adjoining the semiconductor chip; arranging each of the auxiliary carrier-chip units on a connecting carrier; and removing the auxiliary carrier parts from each auxiliary carrier-chip unit.

21. The method as claimed in claim 20, further comprising fitting the semiconductor chips with electrical connector structures before arranging the plurality of semiconductor chips on the carrier.

22. The method as claimed in claim 20, wherein arranging the plurality of semiconductor chips on the carrier comprises arranging the plurality of semiconductor chips on the carrier by a first contact layer.

23. The method as claimed in claim 20, further comprising connecting the auxiliary carrier to the semiconductor chips by melting a thermoplastic connecting layer.

24. The method as claimed in claim 20, wherein arranging the auxiliary carrier comprise arranging the auxiliary carrier under a vacuum atmosphere.

25. The method as claimed in claim 20, wherein separating the auxiliary carrier comprises sawing the auxiliary carrier, or sawing or scoring and breaking the auxiliary carrier.

26. The method as claimed as claim 20, wherein the auxiliary carrier-chip units are arranged on the connecting carrier by a second contact layer.

27. The method as claimed in claim 26, wherein a surface tension of the second contact layer is greater than a surface tension of a material of a connecting layer.

28. The method as claimed in claim 26, wherein an arrangement of the auxiliary carrier-chip units on the connecting carrier takes place at temperatures between 200° C. and 300° C., inclusive.

29. The method as claimed in claim 20, wherein removing the auxiliary carrier parts comprises a laser lift-off, etching, lifting or shearing.

30. The method as claimed in claim 20, further comprising removing residues of a connecting layer by a solvent or by plasma cleaning.

31. An optoelectronic semiconductor component comprising: a connector carrier; and a carrier-less semiconductor chip comprising: a first connector structure; a second connector structure; and a semiconductor body comprising a first semiconductor region of a first conductor type, a second semiconductor region of a second conductor type, and an active region arranged between the first semiconductor region and the second semiconductor region, the active region being configured to emit and/or detect electromagnetic radiation, wherein the first connector structure is electrically conductively connected to the first semiconductor region, wherein the second connector structure is electrically conductively connected to the second semiconductor region, wherein the semiconductor chip is connected to the connector carrier by a contact layer, and wherein at least one of the connector structures is in contact with the connector carrier over an entire cross-sectional area of the semiconductor body, which is parallel to its main extension direction.

32. The optoelectronic semiconductor component as claimed in claim 31, further comprising an optical element arranged on the semiconductor chip on a side facing away from the connector carrier, the optical element being transparent to the electromagnetic radiation.

33. The optoelectronic semiconductor component as claimed in claim 32, wherein the optical element comprises a wavelength conversion material.

34. The optoelectronic semiconductor component as claimed claim 31, wherein a thickness of the semiconductor body is less than 10 μm.

35. The optoelectronic semiconductor component as claimed in claim 31, wherein at least one of the connector structures has a thickness of at least 1 μm.

36. The optoelectronic semiconductor component as claimed in claim 31, wherein at least one of the connector structures laterally overhangs the semiconductor body.

37. The optoelectronic semiconductor component as claimed in claim 31, wherein at least one of the connector structures extends over the entire cross-sectional area of the semiconductor body, which is parallel to its main extension direction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Further advantages and advantageous embodiments and refinements of the optoelectronic semiconductor component arise from the following exemplary embodiments in conjunction with those shown in the figures.

[0064] In the drawings:

[0065] FIGS. 1A to 1K show schematic sectional views of an optoelectronic semiconductor component described here according to a first exemplary embodiment at different stages of a method for its production;

[0066] FIG. 2A shows a schematic sectional view of an auxiliary carrier-chip unit described here according to a first exemplary embodiment;

[0067] FIG. 2B shows a schematic sectional view of an auxiliary carrier-chip unit described here according to a second exemplary embodiment;

[0068] FIG. 2C shows a schematic sectional view of an auxiliary carrier-chip unit described here according to a third exemplary embodiment;

[0069] FIGS. 3A to 3D show schematic sectional views of an optoelectronic semiconductor component described here according to a second exemplary embodiment at different stages of a method for its production;

[0070] FIG. 4 shows a schematic sectional view of an optoelectronic semiconductor component described here according to a third exemplary embodiment;

[0071] FIG. 5 shows a schematic sectional view of an optoelectronic semiconductor component described here according to a fourth exemplary embodiment;

[0072] FIG. 6 shows a schematic sectional view of an optoelectronic semiconductor component described here according to a fifth exemplary embodiment; and

[0073] FIG. 7 shows a schematic sectional view of an auxiliary carrier-chip unit described here according to a first exemplary embodiment.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0074] Identical, similar, or equivalently functioning elements are labelled with the same reference signs in the figures. The figures and the relative proportions of the elements represented in the figures are not to be considered to be true to scale. Instead, individual elements may be shown exaggerated in size for ease of visualization and/or better understanding.

[0075] In the step shown in FIG. 1A, a carrier 50 with a plurality of semiconductor chips 10 is provided. The carrier 50 is formed of silicon.

[0076] The semiconductor chips 10 are arranged on a common side of the carrier 50. The semiconductor chips 10 are fixed to the carrier 50 by means of a first contact layer 71. An auxiliary carrier 60 and a connecting layer 40 arranged on the auxiliary carrier 60 are also provided. The connecting layer 40 comprises a thermoplastic material, for example a polymer. The auxiliary carrier 60 is formed of glass or sapphire, for example. The auxiliary carrier 60 is preferably transparent to electromagnetic radiation in the visible wavelength range.

[0077] In the step shown in FIG. 1B, the carrier 50 with a plurality of semiconductor chips 10 is arranged on the auxiliary carrier 60 and the connecting layer 40. In a further processing step, the connecting layer 40 is heated to a temperature above its glass transition temperature. This softens the connecting layer 40 and makes it more easily deformable.

[0078] In the step shown in FIG. 1C, the heated connecting layer 40 has penetrated into spaces between the semiconductor chips 10. In particular, the semiconductor chips 10 are completely enclosed by the material of the connecting layer 40.

[0079] This step of the method is preferably carried out under a vacuum atmosphere. This advantageously avoids the formation of air bubbles and the emergence of cavities in the connecting layer 40. Consequently, a particularly good coating of the semiconductor chips 10 with the material of the connecting layer 40 is ensured.

[0080] In the step shown in FIG. 1D, the carrier 50 is completely removed from the semiconductor chips 10. For example, the removal of the carrier 50 is carried out by mechanically abrasion, in particular by means of polishing. Residues of the carrier 50 are removed, in particular by means of an etching solution. The first contact layer 71, which was provided for attaching the semiconductor chips 10 to the carrier 50, is also removed. Consequently, a second contact layer 72 is exposed on a side of the semiconductor chips 10 facing away from the auxiliary carrier 60. Alternatively, the second contact layer 72 instead of the first contact layer 71 is applied to the semiconductor chips 10.

[0081] In the step shown in FIG. 1E, recesses 41 are created in the connecting layer 40. The recesses 41 are arranged between pairs of adjacent semiconductor chips 10 and extend from a side of the connecting layer 40 facing away from the auxiliary carrier 60 through the entire connecting layer 40 as far as the auxiliary carrier 60. For example, the recesses 41 are created by means of a sawing process. For example, the recesses 41 represent breaking notches for a subsequent separation step, provided that they extend at least partially into the auxiliary carrier 60.

[0082] At the stage shown in FIG. 1F, the auxiliary carrier 60 is separated into a plurality of auxiliary carrier-chip units 2. Each auxiliary carrier-chip unit 2 comprises a semiconductor chip 10 and an auxiliary carrier part 61. The separation of the auxiliary carrier 60 into the auxiliary carrier parts 61 is carried out by breaking it at the break points defined by the recesses 41 or by sawing.

[0083] In the step shown in FIG. 1G, the auxiliary carrier-chip unit 2 is arranged on a connector carrier 30 by means of the second contact layer 72. The second contact layer 72 comprises in particular a eutectic alloy of gold and tin. The semiconductor chip 10 also comprises a first connector structure 201 and a second connector structure 202. The first connector structure 201 is arranged between the second contact layer 72 and the semiconductor layers and is not shown in this figure. The second connector structure 202 is arranged at the side and embedded in the connecting layer 40.

[0084] The connector carrier 30 is formed of aluminum nitride. In addition, the connector carrier 30 comprises contact structures 31 for electrical contacting. The contact structures 31 are formed of copper. To facilitate positioning of the auxiliary carrier-chip unit 2 on the connector carrier 30, a flux 90 is applied to the connector carrier 30. The flux 90 comprises glycol, for example.

[0085] In the step shown in FIG. 1H, the auxiliary carrier-chip unit 2 is aligned on the connector carrier 30 before the auxiliary carrier-chip units (2) are arranged on the connector carrier (30). The flux 90 allows the auxiliary carrier-chip unit 2 to float on the connector carrier 30. In other words, the auxiliary carrier-chip unit 2 is free to move on the connector carrier 30 as long as the flux 90 remains present between the auxiliary carrier-chip unit 2 and the connector carrier 30. In a further processing step, the flux 90 is evaporated off at a temperature below the melting temperature of the second contact layer 72.

[0086] At the stage shown in FIG. 1I, the flux 90 has completely evaporated and by increasing the temperature to over 280° C., the material of the second contact layer 72 has melted. The connector carrier 30 is now connected to the auxiliary carrier-chip unit 2 to form an optoelectronic semiconductor component 1. The surface tension of the material of the second contact layer 72 is greater than the surface tension of the material of the connecting layer 40. The net result is that a force which is directed toward the connector carrier 30 acts on the second connector structure 202. This advantageously prevents the second connector structure 202 from bending in the direction of the connecting layer 40.

[0087] In the step shown in FIG. 1J, the auxiliary carrier part 61 is completely removed from the optoelectronic semiconductor component 1. For example, the auxiliary carrier part 61 is mechanically removed by shearing the auxiliary carrier part 61 from the connecting layer 40. The connecting layer 40 initially remains on the semiconductor chip 10.

[0088] At the stage shown in FIG. 1K, the connecting layer 40 has been completely removed from the semiconductor chip 10. For example, the connecting layer 40 is completely dissolved by means of a solvent. The surface of the semiconductor chip 10 facing the connector carrier 30 is completely freed of residues of the connecting layer 40 by means of a cleaning process, for example a plasma etching process. This advantageously enables a particularly simple rearrangement of optical elements on the semiconductor chip 10.

[0089] In the exemplary embodiment of an auxiliary carrier-chip unit 2 described here, shown in FIG. 2A in a schematic sectional view, the connecting layer 40 around the semiconductor chip 10 has recesses 41. The recesses 41 are generated by a sawing process or by laser ablation, for example. The recesses reach at least into the auxiliary carrier 60 and extend partially into the auxiliary carrier 60. The auxiliary carrier 60 is thus provided with a mechanical weak point, which is used, for example, in a breaking process for separating the auxiliary carrier 60 into the auxiliary carrier parts 61.

[0090] In the exemplary embodiment of an auxiliary carrier-chip unit 2 described here, shown in FIG. 2B in a schematic sectional view, the auxiliary carrier-chip unit 2 shown does not have any recesses 41. For example, this auxiliary carrier-chip unit 2 was severed by means of a single processing step in a sawing process. The saw completely severed the auxiliary carrier 60 and the connecting layer 40 in one step.

[0091] In the exemplary embodiment of an auxiliary carrier-chip unit 2 described here, shown in FIG. 2C in a schematic sectional view, a first sawing process is carried out from the side of the auxiliary carrier-chip unit 2 facing the auxiliary carrier 60 and a second sawing process is carried out from the side of the auxiliary carrier chip unit 2 opposite the auxiliary carrier 60 to separate the auxiliary carrier 60 into auxiliary carrier parts 61. A cutting width of the sawing processes is advantageously variable. Thus, in the first sawing process a wider cut is tolerated than in the second sawing process.

[0092] In the step shown in FIG. 3A, the auxiliary carrier part 61 is removed by mechanical lifting. The direction in which a force is exerted on the auxiliary carrier part 61 is indicated with an arrow. The connecting layer 40 is initially heated to a temperature above its glass transition temperature in order to reduce the adhesion between the auxiliary carrier part 61 and the connecting layer 40. The removal of the auxiliary carrier part 61 is therefore particularly fast and cost-effective. A disadvantage is that, depending on the temperature, the semiconductor chip 10 is exposed to a high mechanical load.

[0093] In the step shown in FIG. 3B, the auxiliary carrier part 61 is removed by mechanical shearing. In the shearing process, the auxiliary carrier part 61 is removed by applying a force to a side surface of the auxiliary carrier part 61. The direction in which a force is exerted on the auxiliary carrier part 61 is indicated with an arrow. Before applying the force, the connecting layer 40 is preferably heated to a temperature above its glass transition temperature in order to reduce the adhesion between the auxiliary carrier part 61 and the connecting layer 40. The majority of the connecting layer 40 remains on the semiconductor chip 10.

[0094] In the step shown in FIG. 3C, the auxiliary carrier part 61 is removed by means of laser lift-off. In the laser lift-off process, the adhesion between the connecting layer 40 and the auxiliary carrier part 61 is reduced or eliminated by means of a laser radiation. For example, at least a part of the connecting layer 40 is melted or vaporized by means of the laser radiation. The laser beam penetrates through the radiolucent auxiliary carrier part 61 as far as the connecting layer 40. In other words, the auxiliary carrier part 61 is preferably designed to be radiolucent for the laser radiation.

[0095] In the step shown in FIG. 3D, the auxiliary carrier part 61 is removed by means of a solvent. The connecting layer 40 is completely dissolved by means of a chemical solvent. The solvent penetrates from the side surfaces of the connecting layer 40 to the center of the semiconductor chip 10. Depending on the lateral extension of the semiconductor chip 10, a greater amount of time is thus required to remove the connecting layer 40. The removal of the connecting layer 40 and the auxiliary carrier part 61 is thus particularly harmless to the semiconductor chip 10. A further processing step to remove the connecting layer 40 can therefore be significantly shortened or is advantageously eliminated entirely.

[0096] In the exemplary embodiment shown in FIG. 4 in a sectional view, the optoelectronic semiconductor component 1 comprises a semiconductor chip 10 arranged on a connector carrier 30, and a protective diode 101 arranged to the side of it. The protective diode 101 is also arranged on the connector carrier 30 and fulfills the function of an ESD protective diode. The protective diode 101 thus protects the semiconductor chip 10 from damage due to electrostatic discharge.

[0097] In the exemplary embodiment shown in FIG. 5 in a sectional view, an optical element 80 is arranged on the semiconductor chip 1. The exemplary embodiment shown here essentially corresponds to the third exemplary embodiment of an optoelectronic semiconductor component 1, shown in FIG. 4. The optical element 80 is arranged on a side of the semiconductor chip 10 facing away from the connector carrier 30. The optical element 80 is radiolucent and contains, for example, a wavelength conversion material.

[0098] In addition, the semiconductor chip 10 and the optical element 80 are surrounded by a molded body 301. The molded body 301 is flush with the side of the optical element 80 facing away from the connector carrier 30. For example, the molded body 301 is formed from a polymer that has a white filling material. For example, the molded body 301 is formed from a silicone into which particles of titanium dioxide have been introduced. Electromagnetic radiation emitted from the side of the semiconductor chip 10 or the optical protective element 80 is at least partially reflected back by the molded body 301. The molded body 301 also provides protection for the semiconductor chip 10 against mechanical influences and/or chemical influences from the surrounding atmosphere.

[0099] In the exemplary embodiment of an optoelectronic semiconductor component 1 shown in a sectional view in FIG. 6, a second connector structure 202 is arranged on a side of a semiconductor chip 10 facing away from a connector carrier 30. In this more mechanically stable design of the second connector structure 202, the surface tension of the material of the second contact layer 72 is largely irrelevant compared to the surface tension of the material of the connecting layer 40.

[0100] In the exemplary embodiment of an auxiliary carrier-chip unit 2 described here, shown in a sectional view in FIG. 7, the auxiliary carrier-chip unit 2 comprises an auxiliary carrier part 61 and a semiconductor chip 10. The semiconductor chip 10 is divided into a plurality of semiconductor layers which are combined in a semiconductor body 100. The semiconductor body 100 consists of a first semiconductor region 1001, a second semiconductor region 1002, and an active region 1003 arranged between the first semiconductor region 1001 and the second semiconductor region 1002. The active region 1003 comprises a pn-junction and is designed for the emission and/or detection of electromagnetic radiation. In particular, there is no growth substrate and/or no carrier body arranged between the semiconductor body 100 and the connector structures 201, 202.

[0101] The semiconductor body 100 is mechanically connected to the auxiliary carrier part 61 by means of a connecting layer 40. On the side of the semiconductor body 100 facing away from the auxiliary carrier part 61, a first connector structure 201, a second connector structure 202 and a dielectric layer 203 are located. The dielectric layer 203 is formed from an electrically insulating material and insulates the first connector structure 201 from the second connector structure 202. For example, the dielectric layer 203 is formed of silicon dioxide. The first connector structure 201 and the second connector structure 202 each have a thickness 200X. The thickness 200X of the connector structures 201, 202 is preferably more than 1 μm. This means that the mechanical stability of the connector structures 201, 202 is advantageously increased. The semiconductor body 100, together with the connector structures 201, 202 and the dielectric layer 203, forms a semiconductor chip 10.

[0102] The semiconductor body 100 also has a decoupling surface 100A on the side facing away from the connector structures 201, 202. The decoupling surface 100A is roughened and is designed for decoupling at least a major part of the electromagnetic radiation generated in the active region 1003. The semiconductor body 100 has a thickness 100X. The thickness 100X of the semiconductor body 100 corresponds to its extension perpendicular to its main extension direction. Preferably, the thickness 100X of the semiconductor body 100 is less than 10 μm. A particularly small distance from the active region 1003 to the connector structures 201, 202, which act as heat sinks, can thus be advantageously realized. Furthermore, it is particularly advantageous to design the dielectric layer 203 particularly thin in order to enable a good heat dissipation from the second connector structure 202 and thus achieve a particularly good cooling of the semiconductor body 10.

[0103] A second contact layer 72 is arranged on the side of the semiconductor region 100 facing away from the auxiliary carrier part 61. The second contact layer 72 is formed with a eutectic alloy of gold and tin and is used in particular to attach the auxiliary carrier-chip unit 2 to a connector carrier 30. The second contact layer 72 is already included in the semiconductor chip 10 in other figures and embodiments, but in the interests of better presentation is not shown in every figure.

[0104] The invention is not limited by the description based on the exemplary embodiments. Rather, the invention comprises each new feature, as well as any combination of features, which includes in particular every combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.