III-N based substrate for power electronic devices and method for manufacturing same

Abstract

The present disclosure relates to a III-N based substrate for power electronic devices, comprising a base substrate, a III-N laminate above the base substrate and a buffer layer structure between the base substrate and the III-N laminate. The buffer layer structure comprises at least a first superlattice laminate and a second superlattice laminate above the first superlattice laminate. The first superlattice laminate comprises a repetition of a first superlattice unit which consists of a plurality of first AlGaN layers. The second superlattice laminate comprises a repetition of a second superlattice unit which consists of a plurality of second AlGaN layers. An average aluminum content of the first superlattice laminate is a predetermined difference greater than an average aluminum content of the second superlattice laminate, to improve the vertical breakdown voltage. The present disclosure also relates to a method for manufacturing a III-N based substrate for power electronic devices.

Claims

1. A III-N based substrate for power electronic devices comprising: a base substrate; a III-N laminate above the base substrate; and a buffer layer structure between the base substrate and the III-N laminate, wherein the buffer layer structure comprises at least a first superlattice laminate and a second superlattice laminate above the first superlattice laminate, wherein the first superlattice laminate comprises a repetition of a first superlattice unit which comprises a plurality of first AlGaN layers, each of which is made of Al.sub.xGa.sub.1-xN with 0x1 and x being different among the first AlGaN layers, wherein the second superlattice laminate comprises a repetition of a second superlattice unit which comprises a plurality of second AlGaN layers, each of which is made of Al.sub.yGa.sub.1-yN with 0y1 and y being different among the second AlGaN layers, wherein an average aluminum content of the first superlattice laminate is greater than an average aluminum content of the second superlattice laminate by a predetermined difference, and wherein the buffer layer structure has a breakdown field strength of more than 150 V/m in forward or reverse vertical bias at room temperature (25 C.).

2. The III-N based substrate according to claim 1, wherein the base substrate comprises SiC.

3. The III-N based substrate according to claim 1, wherein the predetermined difference controls substrate warpage at room temperature (25 C.) to be below 50 m for a substrate of 200 mm in diameter.

4. The III-N based substrate according to claim 1, wherein an at least partial strain relaxation is present in the buffer layer structure, between at least one adjacent pair of layers of the first superlattice laminate or the second superlattice laminate.

5. The III-N based substrate according to claim 1, wherein the average aluminum content of the first superlattice laminate is at least 30%.

6. The III-N based substrate according to claim 1, wherein the average aluminum content of the second superlattice laminate is below 25%.

7. The III-N based substrate according to claim 1, wherein the predetermined difference is at least 5%.

8. The III-N based substrate according to claim 1, wherein the buffer layer structure comprises at least one additional superlattice laminate on top of the second superlattice laminate, wherein each additional superlattice laminate comprises a repetition of a respective third superlattice unit which comprises a plurality of respective third AlGaN layers, each of which is made of Al.sub.iGa.sub.1-iN with 0i1 and i being different among the respective third AlGaN layers of the respective third superlattice unit, wherein the average aluminum content of the first superlattice laminate is at least 5% greater than the average aluminum content of the second superlattice laminate, and wherein the average aluminum content of the second superlattice laminate is at least 5% greater than an average aluminum content of the at least one additional superlattice laminate.

9. The III-N based substrate according to claim 8, wherein the average aluminum content of the at least one additional superlattice laminate is at least 5%.

10. The III-N based substrate according to claim 8, wherein the first superlattice unit, the second superlattice unit, or an additional superlattice unit comprises at least three AlGaN layers.

11. The III-N based substrate according to claim 10, wherein the first superlattice unit, the second superlattice unit, or a third superlattice unit comprises a layer of Al.sub.jGa.sub.1-jN, with 0j0.5.

12. The III-N based substrate according to claim 8, wherein the first superlattice unit, the second superlattice unit or an additional superlattice unit comprises a layer of AlN.

13. The III-N based substrate according to claim 8, wherein one or more layers selected from the first superlattice laminate, the second superlattice laminate, or one of the at least one additional superlattice laminates comprises impurity atoms.

14. The III-N based substrate according to claim 13, wherein the impurity atoms are one or more species selected from the group consisting of C atoms, Fe atoms, Mn atoms, Mg atoms, V atoms, Cr atoms, Be atoms, and B atoms.

15. The III-N based substrate according to claim 14, wherein the impurity atoms are C atoms or Fe atoms.

16. A method for manufacturing a III-N based substrate for power electronic devices, comprising the steps of: providing a base substrate; growing a buffer layer structure on the base substrate; and growing a III-N laminate on the buffer layer structure, wherein the buffer layer structure comprises at least a first superlattice laminate and a second superlattice laminate above the first superlattice laminate, wherein the first superlattice laminate comprises a repetition of a first superlattice unit which comprises a plurality of first AlGaN layers, each of which is made of Al.sub.xGa.sub.1-xN with 0x1 and x being different among the first AlGaN layers, wherein the second superlattice laminate comprises a repetition of a second superlattice unit which consists of a plurality of second AlGaN layers, each of which is made of Al.sub.yGa.sub.1-yN with 0y1 and y being different among the second AlGaN layers wherein upon growing the buffer layer structure, process conditions are controlled such that an average aluminum content of the first superlattice laminate is greater than an average aluminum content of the second superlattice laminate by a predetermined difference, and wherein the buffer layer structure has a breakdown field strength of more than 150 V/m in forward or reverse vertical bias at room temperature (25 C.).

17. The method according to claim 16, wherein the first superlattice unit and the second superlattice unit have the same layer structure except for a variation in a respective thickness of at least one of the AlGaN layers to influence the average aluminum content of the superlattice units and hence the superlattice laminates.

18. The method according to claim 16, wherein for at least one superlattice laminate, growth of superlattice units is at least continued until a slope of an in situ wafer curvature drops below 0.015 km.sup.1/s.

19. The method according to claim 16, wherein the buffer layer structure is grown such that an at least partial strain relaxation occurs between at least one adjacent pair of layers of the first superlattice laminate or the second superlattice laminate.

20. The method according to claim 16, wherein the base substrate comprises SiC.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) The above, as well as additional, features will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.

(2) The disclosure will be further elucidated by means of the following description and the appended drawings.

(3) FIG. 1 shows a schematic example of GaN-based power HEMT (or Diode) stack with a stepped-SL buffer, according to an example embodiment.

(4) FIG. 2 shows an example of the formula for calculating equivalent aluminum content, according to an example embodiment.

(5) FIG. 3 shows a first example according to the present disclosure, with two SL laminates, wherein the difference in equivalent Al % is achieved by varying the Al content in the top layer of the SL units, according to an example embodiment.

(6) FIG. 4 shows, for the structure of FIG. 3, the vertical buffer breakdown (Vbd) measurement results at 25 C. and 150 C., according to an example embodiment.

(7) FIG. 5 shows a second example according to the present disclosure, with two SL laminates, wherein the difference in equivalent Al % is achieved by varying the thickness of the top layer of the SL units, according to an example embodiment.

(8) FIG. 6 shows, for the structure of FIG. 5, the vertical buffer breakdown (Vbd) measurement results at 25 C. and 150 C., according to an example embodiment.

(9) FIG. 7 shows a reference stack with a single SL laminate, according to an example embodiment.

(10) FIG. 8 shows, for the structure of FIG. 7, the vertical buffer breakdown (Vbd) measurement results at 25 C. and 150 C., according to an example embodiment.

(11) FIG. 9 shows a summary of the Vbd measurements of the two examples of FIG. 3 and FIG. 5 and the reference under both bias polarities and at 25 C. and 150 C., respectively, according to example embodiments.

(12) FIG. 10 shows the variation of the in situ wafer curvature over time during construction of an embodiment of a stepped-SL buffer, according to example embodiments.

(13) All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.

DETAILED DESCRIPTION

(14) Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout.

(15) The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to actual reductions to practice of the disclosure.

(16) Furthermore, the terms first, second, third, and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. The terms are interchangeable under appropriate circumstances and the embodiments of the disclosure can operate in other sequences than described or illustrated herein.

(17) Moreover, the terms top, bottom, above, over, under, and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. The terms so used are interchangeable under appropriate circumstances and the embodiments of the disclosure described herein can operate in other orientations than described or illustrated herein. For instance, the terms above and below may refer to directions along and opposite to, respectively, a normal direction to (a main plane of extension or a main surface of) the base substrate (or any of the layers formed thereon).

(18) Furthermore, the various embodiments are to be construed as exemplary manners in which the disclosure may be implemented rather than as limiting the scope of the disclosure.

(19) The term comprising, used in the claims, should not be interpreted as being restricted to the elements or steps listed thereafter; it does not exclude other elements or steps. It needs to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression a device comprising A and B should not be limited to devices consisting only of components A and B, rather with respect to the present disclosure, the only enumerated components of the device are A and B, and further the claim should be interpreted as including equivalents of those components.

(20) In this disclosure, a stepped-superlattice (SL) buffer scheme is presented, embodiments of which can be not only more efficient in enhancing the leakage blocking capability in terms of buffer thickness but also more efficient in introducing in situ convex wafer bow compared with a traditional SL buffer.

(21) The stepped-SL buffer scheme may comprise multiple blocks or laminates of SL structures. An example of GaN-based power HEMT (or Diode) stack with such a stepped-SL buffer is shown schematically in FIG. 1. As shown, each SL laminate consists of a repetition of an SL unit, which in turn consists of a plurality of AlGaN layers, in example embodiments, three to five AlGaN layers. The base substrate may be a foreign substrate to III-N materials, for example a Si, sapphire, or SiC substrate. Optional nucleation and/or transition layers may be provided in between the base substrate and the SL laminates. On top of the upper SL laminate, i.e., below the GaN channel layer, an optional further (Al)GaN layer may be provided, which may be intentionally or un-intentionally C-doped.

(22) In SL1 laminate, the equivalent (average) Al % of SL1 laminate is Al.sub.eq-1%. In SLn laminate, the equivalent (average) Al % of SLn laminate is Al.sub.eqn%. The equivalent Al % is calculated using the formula for which an example is shown in FIG. 2 for a SL unit consisting of a layer of AlN with thickness of D.sub.AlN and a layer of Al.sub.xGa.sub.1-xN with thickness of D.sub.AlGaN. Throughout the present disclosure, the index x, y, z or the like refers to atomic percentage.

(23) In embodiments according to this disclosure, It is required that Al.sub.eq-n%<Al.sub.eq-(n1)%<Al.sub.eq-(n-2)%<Al.sub.eq-(n-3)%< . . . <Al.sub.eq-1% (hence the terminology stepped-superlattice buffer), such that the SL laminates with a higher Al.sub.eq% can be more effective in enhancing the leakage blocking capability while a higher in situ convex wafer bow can be introduced between each SL laminate. The SL laminates may have a C concentration1E18 cm.sup.3 to further increase the electric resistance.

(24) In the following, experimental results are presented which prove the effectiveness of the stepped SL buffer, by way of comparative examples. All examples are grown on 200 mm Si substrates.

(25) FIG. 3 shows a first example according to the present disclosure. The stack schematic shows two SL laminates in this buffer structure where the total stack thickness is 4 m (200 nm AlN nucleation layer+1 m SL1+1.65 m SL2+1 m CGaN+300 nm GaN, which is the total stack that contributes to the total vertical Vbd). The SL1 laminate has an equivalent Al % of 40.6% and SL2 laminate has 23.6%. Both the SL1 and SL2 laminates consist of repetitions of SL units consisting of an AlN layer (5 nm) with an Al.sub.xGa.sub.1-xN, respectively Al.sub.yGa.sub.1-yN layer on top (28 nm). The difference in equivalent Al % is achieved by varying the Al content in the top layer: in this example x is 0.3 while y is 0.1. SL1 consists of 30 repetitions; SL2 consists of 50 repetitions. The figure on the right is the in situ wafer curvature recorded during the growth of this stack, where the sharp spikes and short range high frequency oscillations of the curves are the artefacts of the measurement system. The positive curvature represents a convex wafer shape and negative curvature represents a concave wafer shape. According to the Stoney equation, the slope of the in situ wafer curvature is proportional to the in-plane stress at the growth front. A positive slope indicates a compressive in-plane stress and a negative slope indicates a tensile in-plane stress. The in situ wafer curvature indicates that throughout the SL growth, a compressive stress can be maintained which can effectively compensate the tensile stress during the cooling and minimize the epitaxial wafer warp. Especially, a clear increase of the slope of the in situ curvature can be seen when SL2 laminate starts to grow. This is due to the lattice mismatch introduced compressive stress when growing the SL2 laminate on the SL1 laminate because the equivalent Al % in the SL2 laminate is less than in the SL1 laminate (for an Al.sub.xGa.sub.1-xN layer, the smaller x is, the lager lattice constant is) while the compressive strain of SL1 laminate is already sufficiently relaxed before growing SL2 laminate. The regions indicated by the dashed boxes represent in situ curvature during growth of SL1 and SL2 laminates, respectively.

(26) The final epitaxial wafer warp (at room temperature, i.e. 25 C.) is +40 m. The positive sign of the warp follows the same as for in situ curvature (i.e., convex wafer shape). For device processing in a 200 mm Si CMOS line, typical SPEC for wafer warp is 50 m and a positive warp is more favorable for the stability of epitaxial wafer integrity. So the wafer warp achieved in this first example is within acceptable limits.

(27) FIG. 4 shows the vertical buffer breakdown (Vbd) measurement results at 25 C. and 150 C. The measurement method is illustrated on the left where, square (100 m100 m) metal dots were processed on the samples by Ti/Au metallization and lift-off. The buffer breakdown voltage is defined as the voltage where the leakage current reaches 1 A/mm.sup.2. The measurements prove a high breakdown voltage even though the total buffer structure thickness is only 4.14 m.

(28) FIG. 5 shows a second example according to the present disclosure. The stack schematic shows two SL laminates in this buffer structure where the total thickness is 4 m. The SL1 laminate has an equivalent Al % of 40.0% and SL2 laminate has 23.6%. Both the SL1 and SL2 laminates consist of repetitions of SL units consisting of an AlN layer (5 nm) with an Al.sub.xGa.sub.1-xN, respectively Al.sub.yGa.sub.1-yN layer on top (10 nm, respectively 28 nm). In this example x=y=0.1 and the difference in equivalent Al % is achieved by varying the thickness of the top layer. SL1 consists of 66 repetitions; SL2 consists of 50 repetitions. The figure on the right is the in situ wafer curvature recorded during the growth of this stack, where the sharp spikes and short range high frequency oscillations of the curves are the artefacts of the measurement system. The positive curvature represents a convex wafer shape and negative curvature represents a concave wafer shape. According to the Stoney equation, the slope of the in situ wafer curvature is proportional to the in-plane stress at the growth front. A positive slope indicates a compressive in-plane stress and a negative slope indicates a tensile in-plane stress. The in situ wafer curvature indicates that throughout the SL growth, a compressive stress can be maintained which can effectively compensate the tensile stress during the cooling in order to minimize the epitaxial wafer warp. Especially, a clear increase of the slope of the in situ curvature can be seen when SL2 laminate starts to grow. This is due to the lattice mismatch introduced compressive stress when growing SL2 on SL1 laminate because the equivalent Al % in SL2 laminate is less than SL1 laminate (while the compressive strain of SL1 laminate is already sufficiently relaxed before growing SL2 laminate), even though the Al % in the AlGaN layer in both SL1 and SL2 laminates is the same. The regions indicated by the dashed boxes represent in situ curvature during growth of SL1 and SL2 laminates, respectively.

(29) The final epitaxial wafer warp (after cooling) is about 20 m. The positive sign of the warp follows the same as for in situ curvature (i.e. convex wafer shape). For device processing in a 200 mm Si production line, typical SPEC for wafer warp is 50 m and a positive warp is more favorable for the stability of epitaxial wafer integrity. So the final warp is within acceptable limits.

(30) FIG. 6 shows the vertical buffer breakdown (Vbd) measurement results at 25 C. and 150 C. The measurements prove a high breakdown voltage even though the total buffer structure thickness is only 4.14 m.

(31) As a reference, a stack with a single SL laminate is shown in FIGS. 7 and 8. The SL laminate consists of 100 repetitions of the same SL unit as the SL2 laminate in examples 1 and 2, namely an AlN layer (5 nm) with an AlGaN layer on top (28 nm) with 10% Al. The total stack thickness is 5.4 m. Because it has only one SL laminate, there is no additional compressive stress introduced during SL growth, and the wafer warp at room temperature (25 C.) is 40 m which is also less favorable. Although the Vbd of this stack is similar to that of the examples 1 and 2, its thickness is much higher. As a result, the breakdown field strength of the reference stack is in comparison much lower.

(32) FIG. 9 shows a summary of the Vbd measurements of the two examples and the reference under both bias polarities and at 25 C. and 150 C., respectively. The figure clearly shows that the breakdown field strength is much higher for the two examples than the reference under all conditions, especially at 150 C.

(33) FIG. 10 is provided as an explanation for the thickness of at least one superlattice laminate, which may be enough to allow sufficient strain relaxation of the superlattice laminate. The sharp spikes and short range high frequency oscillations of the curves are the artefacts of the measurement system. The thickness corresponds to the thickness where the slope of the wafer in situ curvature appreciably decreases (the addition of SL units is continued at least until the slope of the in situ wafer curvature drops below 0.015 km.sup.1/s). This thickness depends on the average aluminum content of as well as the layer structure of the superlattice laminate. The figure gives an example: the arrow indicates where the slope of the in situ wafer curvature is considered as appreciably decreasing, so where a suitable thickness for the strain relaxation has been obtained.

(34) It should be noted that FIG. 10 merely represents one example and that the growth of the buffer layer structure may be performed such that an at least partial in-plane strain relaxation occurs between one adjacent pair of layers within a lower, middle, or top portion of the first or the second superlattice laminate. The pair may include a lower layer and an upper layer formed on the lower layer wherein the upper layer, during the growth of the buffer layer structure, becomes or is formed to be at least partially strain relaxed with respect to the lower layer. The strain relaxation may be achieved for instance by growing the upper layer to a thickness exceeding a critical layer thickness. Alternatively, the upper layer may be grown as a pseudomorphic layer (i.e. thinner than the critical thickness) and subsequently, following growth of further layers on top, become partially strain relaxed. Strain relaxation may occur at one or more positions within the first superlattice laminate and/or within the second superlattice laminate. All other layers of the superlattice laminate(s) may form pseudomorphic layers. For instance, in the example of FIG. 5 it may be seen that that strain relaxation occurs already in a lower portion of the SL1.

(35) Following completion and cooling of the III-N substrate, an at least partial strain relaxation may be present in the buffer layer structure, between (at least) the lower and adjacent upper layer. The lattice mismatch induced in-plane strain f for an adjacent lower and upper layer may be defined as f=(c.sub.Lc.sub.U)/c.sub.U, where c.sub.L is the in-plane lattice constant of the lower layer and c.sub.U is the relaxed in-plane lattice constant of the upper layer. For a pseudomorphic upper layer, the in-plane lattice constant of the upper layer matches the in-plane lattice constant of the lower layer.

(36) In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.

(37) While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.