Method and device for damping voltage harmonics in a multilevel power converter

Abstract

A method for controlling a modular multilevel converter to reduce the lower order harmonics generated by the converter is provided. The method may also reduce the overall switching loss of the converter by switching the switches close to fundamental switching frequencies while still reducing the lower order harmonics that are generated.

Claims

1. A method for reducing lower order harmonics of a multi-level power converter comprising at least one phase leg comprising a plurality of chain-link connected cells each comprising a capacitor, the method comprising, for each phase leg of the converter: obtaining, from a current control, a present reference voltage for use during a present half switching duration, a half switching duration being a time period corresponding to one switching opportunity of the cells; dividing the half switching duration into a plurality of time intervals; and at the beginning of each time interval: predicting the reference voltage waveform for the remainder of the half switching duration based on the present reference voltage; predicting the leg output voltage waveform for the remainder of the present half switching duration for the case that switching for one cell is performed in the leg during the time interval; predicting a flux error, being a time integral of a difference between the leg output voltage and the reference voltage, at the end of the present half switching duration for the case, based on the present reference voltage, the predicted reference voltage waveform and the predicted leg output voltage waveform, wherein the predicted flux error is a cumulative flux error of the present half switching duration and a preceding half switching duration; and determining not to perform switching for any cell in a present time interval of the plurality of time intervals when the predicted flux error passes zero during the first half switching duration.

2. The method of claim 1, wherein switching for only one cell is performed during the present half switching duration.

3. The method of claim 2, wherein a pulse number of the converter is less than 5.5.

4. The method of claim 2, wherein the method is performed by a control unit of the converter.

5. A computer program product embodied on a non-transitory computer readable medium and comprising computer-executable components for causing a control unit for a phase leg of a power converter to perform the method of claim 2 when the computer-executable components are run on processor circuitry comprised in the control unit.

6. The method of claim 1, wherein switching for a second cell, in addition to a first cell for which switching has been performed at a previous time interval, is performed during the present half switching duration when the flux error predicted at a present time interval is outside of a predetermined range.

7. The method of claim 6, wherein a pulse number of the converter is less than 5.5.

8. The method of claim 6, wherein the method is performed by a control unit of the converter.

9. A computer program product embodied on a non-transitory computer readable medium and comprising computer-executable components for causing a control unit for a phase leg of a power converter to perform the method of claim 6 when the computer-executable components are run on processor circuitry comprised in the control unit.

10. The method of claim 1, wherein a pulse number of the converter is less than 5.5.

11. The method of claim 10, wherein the method is performed by a control unit of the converter.

12. A computer program product embodied on a non-transitory computer readable medium and comprising computer-executable components for causing a control unit for a phase leg of a power converter to perform the method of claim 10 when the computer-executable components are run on processor circuitry comprised in the control unit.

13. The method of claim 1, wherein the method is performed by a control unit of the converter.

14. A computer program product embodied on a non-transitory computer readable medium and comprising computer-executable components for causing the control unit for a phase leg of a power converter to perform the method of claim 13 when the computer-executable components are run on processor circuitry comprised in the control unit.

15. A computer program product embodied on a non-transitory computer readable medium and comprising computer-executable components for causing a control unit for a phase leg of a power converter to perform the method of claim 1 when the computer-executable components are run on processor circuitry comprised in the control unit.

16. The method of claim 1, wherein a pulse number of the converter is less than 2.5.

17. A control unit for a phase leg of a multi-level power converter, the control unit comprising: processor circuitry; and a storage unit storing instructions executable by said processor circuitry whereby said control unit is operative to: obtain, from a current control, a present reference voltage for use during a present half switching duration, a half switching duration being a time period corresponding to one switching opportunity of the cells; divide the half switching duration into a plurality of time intervals; and at the beginning of each time interval: predict the reference voltage waveform for the remainder of the half switching duration based on the present reference voltage; predict the leg output voltage waveform for the remainder of the present half switching duration for the case that switching for one cell is performed in the leg during the time interval; predict a flux error, being a time integral of a difference between the leg output voltage and the reference voltage, at the end of the present half switching duration for the case, based on the present reference voltage, the predicted reference voltage waveform and the predicted leg output voltage waveform, wherein the predicted flux error is a cumulative flux error of the present half switching duration and a preceding half switching duration; and determine not to perform switching for any cell in a present time interval of the plurality of time intervals when the predicted flux error passes zero during the first half switching duration.

18. A power converter comprising a plurality of phase legs, each of the plurality of phase legs comprising the control unit of claim 17.

19. The power converter of claim 18, wherein the converter is a three-phase converter connected in a delta configuration or a three-phase converter connected in a Y configuration.

20. A computer program embodied on a non-transitory computer readable medium for reducing lower order harmonics of a multi-level power converter, the computer program comprising computer program code which is able to, when run on processor circuitry of a control unit for a phase leg of the power converter, cause the control unit to: obtain, from a current control, a present reference voltage for use during a present half switching duration, a half switching duration being a time period corresponding to one switching opportunity of the cells; divide the half switching duration into a plurality of time intervals; and at the beginning of each time interval: predict the reference voltage waveform for the remainder of the half switching duration based on the present reference voltage; predict the leg output voltage waveform for the remainder of the present half switching duration for the case that switching for one cell is performed in the leg during the time interval; predict a flux error, being a time integral of a difference between the leg output voltage and the reference voltage, at the end of the present half switching duration for the case, based on the present reference voltage, the predicted reference voltage waveform and the predicted leg output voltage waveform, wherein the predicted flux error is a cumulative flux error of the present half switching duration and a preceding half switching duration; and determine not to perform switching for any cell in a present time interval of the plurality of time intervals when the predicted flux error passes zero during the first half switching duration.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments will be described, by way of example, with reference to the accompanying drawings, in which:

(2) FIG. 1 is a schematic circuit diagram of an embodiment of an AC-AC converter in delta configuration, in accordance with the present invention.

(3) FIG. 2a is a diagram illustrating voltage waveforms and corresponding flux error in accordance with an embodiment of the present invention.

(4) FIG. 2b is a diagram illustrating voltage waveforms and corresponding flux error in accordance with another embodiment of the present invention.

(5) FIG. 2c is a diagram illustrating voltage waveforms and corresponding flux error in accordance with another embodiment of the present invention.

(6) FIG. 2d is a diagram illustrating voltage waveforms and corresponding flux error in accordance with another embodiment of the present invention.

(7) FIG. 2e is a diagram illustrating voltage waveforms and corresponding flux error in accordance with another embodiment of the present invention.

(8) FIG. 3 is a schematic flow chart of an embodiment of the method of the present invention.

(9) FIG. 4a is a schematic flow chart of a part of an example embodiment of a method algorithm in accordance with the present invention.

(10) FIG. 4b is a schematic flow chart of another part of an example embodiment of a method algorithm in accordance with the present invention.

(11) FIG. 4c is a schematic flow chart of another part of an example embodiment of a method algorithm in accordance with the present invention.

DETAILED DESCRIPTION

(12) Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown. However, other embodiments in many different forms are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout the description.

(13) A delta connected chain-link based STATCOM, as shown in FIG. 1 as an example of a power converter in accordance with the present invention, is a voltage source converter (VSC) which can behave like an inductor or capacitor, storing the reactive power in its cell capacitors. This causes lower order harmonics on the AC side of the converter. Also, in addition to this when a lesser pulse number per cell (less than 3.5) is used, then the triangle comparison based modulation scheme may generate lower order harmonics irrespective of the number of cells used (e.g., could be more than 20 cells). As an alternative to a STATCOM, the multilevel converter of the present invention may be a static VAR compensator (SVC). The same discussion is valid also for Y-connected converters.

(14) Herein, the time integral of voltage is defined as flux. The time integral of a difference between actual voltage generated by the converter and the reference voltage is defined as the flux error.

(15) FIG. 1 schematically illustrates an embodiment of a chain-link converter 1 of the present invention. In the embodiment of FIG. 1, the chain-link converter 1 is in a delta configuration and in a full-bridge configuration. The converter 1 is configured to control and be connected to a three-phase AC system having the phases A, B and C. The converter 1 comprises three phase legs 2, each connected between two of the phases A, B and C. Each of the phase legs 2 comprises a plurality of series-connected converter cells 3. Each cell 3 comprises a capacitor 4. A current control 11 is comprised in the converter 1 in order to control the operation of each of the phase legs 2 of the converter 1, e.g. by setting reference voltages for the phase legs 2. In accordance with embodiments of the present invention, the converter 1 also comprises a control unit 10 for each phase, here called 10a, 10b and 10c depending on the phase leg 2 it is configured to control. The control units 10 thus perform control on a lower (per phase) level in the converter than the current control 11. Each control unit 10 comprises a processor and a data storage unit, as well as other circuitry which may be appropriate. In accordance with the present invention, the control unit 10 implements a plurality of control functions on its phase leg 2 of the converter 1 for improving the operation of the converter 1 in accordance with the present invention. One or more of the control units 10 may be co-located with each other and/or with the current control 11, and may thus share components e.g. processor circuitry and/or data storage with each other.

(16) The method of the present invention may be a PWM method which performs switching in such a way that the flux error reaches to zero at each half switching duration. A switching duration (sometimes called switching sample) is the time period in which two switchings (which can either be a cell Insert and cell Bypass, or two cell Insert or two cell Bypass operations) are traditionally performed, whereby a half switching duration is a time period which traditionally corresponds to one switching (either a cell insert or bypass operation) opportunity. It can be shown that such PWM of the present invention generates very low lower order harmonics (up to 10.sup.th harmonics is less than 0.1%) at an average pulse number of between 2 and 2.5.

(17) The reference and actual voltage (u.sub.ref and u.sub.leg) waveforms along with the flux error (F.sub.error (Wb)) are shown in the FIGS. 2a-2e. The flux error is computed according to Equation 2.
F.sub.error=(u.sub.refu.sub.leg)dtEquation 2

(18) In addition, the flux is defined as a time integral of voltage as F(t)=V(t)dt, such that the flux error can be defined as Equation 2 above. When the flux is expressed for a specific frequency (w) i.e., V(t)=V.sub.m sin(wt), F(t)=V.sub.m sin(wt) dt=v.sub.m/w cos(wt)+F.sub.0, where F.sub.0 is the initial condition of flux and unit of F in the above equation is Volts/Hz. As a result, the flux error (F.sub.error (Wb)) can be expressed in terms of frequency as well.

(19) At an instant t.sub.A, the phase leg voltage is less than the reference voltage and flux error is F.sub.A. The intention is to make this flux error zero, or close to zero, at the end of switching sample (i.e. instant t.sub.B). Note that the time scale between t.sub.A and t.sub.B has been magnified in the figures as compared to the time scale from 0 to t.sub.A. Now, the trajectory of the flux error for a few different cases will be analysed with reference to the FIGS. 2a-2e. The polarity of the current flowing through the phase leg 2 is considered to be charging the cells 3. The FIGS. 2a-2e relates to when the reference voltage is increasing, when the decision to be taken is whether or not insert an additional cell 3. Similarly, if the reference voltage is decreasing, the decision to be taken is whether or not bypass an additional cell 3. However, we may also have to bypass a cell even when the reference voltage is increasing. This situation may occur when the switching frequency is not very low or if the number of cells in the converter phase leg is low. To give an example, say if there is only one cell, then even for the first 90 of voltage reference (where the reference is increasing only) still we may have to insert once and bypass once the cell in every T.sub.sw to make the flux error zero. But when the number of cells are high, e.g. 50, this is usually not needed but still there may in some instances be a need for bypass even when the voltage reference is increasing. For instance, in FIG. 2d at t.sub.B the leg voltage is higher than the reference voltage and the reference is increasing. So in the next half switching time (which is not shown in the figure), we may actually have to decide whether to bypass since the leg voltage is already higher. Similarly, when the reference voltage is decreasing, it may in some cases be desirable to insert a cell rather than only bypass cells. Both the act of inserting a cell and the act of bypassing a cell may be called a switching.

(20) FIG. 2a describes the situation up until the start t.sub.A of the present half switching duration. As can be seen in the top part of the figure, the leg voltage u.sub.leg roughly follows the reference voltage u.sub.ref in incremental steps corresponding to the insertions of additional cells 3 (switchings) to increase the leg voltage. Similarly, the leg voltage may be reduced in decremental steps by bypassing inserted cells 3 (also by switching). The corresponding flux error is shown in the bottom part of the figure. As can be seen, the flux error is not zero at t.sub.A. The proposed PWM scheme may not be activated until t.sub.A (a carrier based PWM may be used) and that may be why the flux error was not zero at t.sub.A.

(21) FIG. 2b illustrates the case when no cell is inserted at t.sub.A. The flux error is calculated (predicted) at the end of the half switching duration (t.sub.B) based on the information of the current flowing through the leg 2, the capacitance of the cells 3 and the number of cells inserted. In this case, the area between the actual leg voltage and the reference voltage (marked with hatched lines), which will drive the flux error to a higher positive value (F.sub.B), as shown in the bottom part of the figure.

(22) FIG. 2c illustrates the case when one cell is inserted at t.sub.A. In this case, the area between the reference voltage and actual leg voltage (u.sub.refu.sub.leg) will reduce the flux error and drives it to a negative value (F.sub.B1) at t.sub.B. The flux error curve passes zero (at t.sub.C) before t.sub.B. Hence, the control unit 10 decides not to perform any switching in this time sample t.sub.A and proceeds to perform similar calculations in the next time sample.

(23) FIG. 2d illustrates the case when one cell is inserted in the time sample t.sub.1t.sub.2. The half switching duration T.sub.sw/2 is divided into time samples having a predetermined size. Typically, a half switching duration may be divided into 100-500 time samples, but in this hypothetical example (for simplification) there are only three time samples in the present half switching duration, namely t.sub.At.sub.1, t.sub.1t.sub.2 and t.sub.2t.sub.B. When the cell 3 is inserted at the instant t.sub.1, the flux error reaches to F.sub.B2 (which is less, in absolute value, than F.sub.B1) at t.sub.B. This indicates that the flux error moves towards zero at the end of the present half switching duration. Hence, the control unit 10 decides not to perform any switching in this time sample t.sub.1t.sub.2 and waits for the next time sample t.sub.2t.sub.B to make the decision for inserting the cell 3.

(24) FIG. 2e illustrates the case when one cell is inserted in the time sample t.sub.2t.sub.B. As can be seen in the bottom part of the figure, the flux error is slightly above zero and its value becomes positive at the end of the half switching duration, at t.sub.B if the cell 3 is inserted at the instant t.sub.2. This prediction shows that the cell has to be inserted at the instant t.sub.2, since waiting till the next time sample will just increase the flux error more towards the positive side. Hence, the control unit 10 generates the command to insert a cell at the time instant t.sub.2.

(25) A similar logic as regarding the FIGS. 2a-2e has been developed to generate bypass commands for the cells. The flux error at the end of the half switching duration reduces with the increase in the number of time samples in a half switching duration. This suggests that if the algorithm is executed at higher sampling rates, the harmonic spectrum generated by the converter 1 will have small, negligible or no lower order harmonics.

(26) Basically, with this PWM method, it may be possible to make the flux error to approach zero at the end of each half switching duration T.sub.sw/2 by switching (insert/bypass a cell 3) at the most appropriate instant. Also, it may be possible to allow additional switching(s) if convenient. The concept of this PWM method may be summarized as follows. Calculate, in accordance with the above discussion relating to the FIGS. 2a-2e, the cell switching (insert/bypass) instance (if any) for every half switching duration so that the flux error is brought back to zero (or as close to zero as possible in view of the number of time samples used). Add the flux error at the end of the previous half switching duration so that any error created by the previous half switching durations can be corrected in the present half switching duration.

(27) The following information may be needed for every half switching duration T.sub.sw/2 to determine the instant of switching: Leg voltage output (u.sub.leg), which is calculated based on switching states and measured voltages over the cells 3 in the phase leg 2, for previous time samples and predicted for future time samples in the half switching duration. Number of cells 3 presently inserted, N.sub.I (can be represented by pINS or nINS in accordance with FIG. 4a), or bypassed. Capacitance per cell, C. Next cell 3 that will be inserted or bypassed (depends on the type of cell selection method used). Current flowing through the converter leg 2.

(28) The half switching duration T.sub.sw/2 is calculated according to Equation 1 and the number of samples (N.sub.samI) within the half switching duration is computed as follows.

(29) $\begin{array}{cc}{N}_{\mathrm{samI}}=\frac{T_{\mathrm{sw}}}{2T_s}=\frac{1}{f_s*\mathrm{PN}*\mathrm{NL}*2*T_s}& \mathrm{Equation}3\end{array}$

(30) where,

(31) T.sub.s is the size of the time samples (which is also the rate at which the algorithm is executed by the control unit 10).

(32) The half switching duration T.sub.sw/2 is divided into N.sub.samI time samples, each corresponding to a sampling instance (see also FIGS. 2a-2e, time samples to FIGS. 2a-2e, t.sub.At.sub.1 or t.sub.1t.sub.2 or t.sub.2 to t.sub.B).

(33) FIG. 3 is a schematic flow chart of an embodiment of the method of the present invention. The method is for reducing lower order harmonics of a multi-level power converter 1 comprising at least one phase leg 2 comprising a plurality of chain-link connected cells 3, each cell comprising a capacitor 4. The method comprises, for each phase leg 2 of the converter obtaining S1, e.g. from a current control 11, a present reference voltage u.sub.ref for use during a present half switching duration T.sub.sw/2, and dividing S2 the half switching duration T.sub.sw/2 into a plurality of time samples t.sub.At.sub.1, t.sub.1t.sub.2 and t.sub.2t.sub.B. The method also comprises, at the beginning t.sub.A, t.sub.1 and t.sub.2 of each time sample t.sub.At.sub.1, t.sub.1t.sub.2 and t.sub.2t.sub.B, predicting S3 the reference voltage u.sub.ref waveform for the remainder of the half switching duration T.sub.sw/2 based on the obtained present reference voltage u.sub.ref. Thus, the reference voltage over the whole half switching duration may be estimated (both from known, past reference voltages, and from estimated, future reference voltages). The method also comprises, at the beginning t.sub.A, t.sub.1 and t.sub.2 of each time sample t.sub.At.sub.1, t.sub.1t.sub.2 and t.sub.2t.sub.B, predicting S4 the leg output voltage u.sub.leg waveform for the remainder of the present half switching duration T.sub.sw/2 both for the case S4a that no cell 3 is inserted or bypassed in the leg 2 during the time sample, and for the case S4b that one cell 3 is inserted or bypassed in the leg 2 during the time sample. Thus the real leg output voltage over the whole half switching duration may be estimated (both from known, past leg voltages, and from estimated, future leg voltages). The method also comprises, at the beginning t.sub.A, t.sub.1 and t.sub.B of each time sample t.sub.At.sub.1, t.sub.1t.sub.2 and t.sub.2t.sub.B, predicting S5 the flux error F.sub.error at the end t.sub.B of the present half switching duration T.sub.sw/2 for each of the cases, based on the obtained present reference voltage u.sub.ref, the predicted reference voltage waveform and the predicted leg output voltage u.sub.leg waveforms. The flux error resulting from the difference between the predicted reference voltage over the present half switching duration and the predicted real leg voltage over the present half switching duration may be calculated. As discussed herein, this flux error should preferably be as close to zero as possible at the end t.sub.B of the present half switching duration. The method also comprises, at the beginning t.sub.A, t.sub.1 and t.sub.2 of each time sample t.sub.At.sub.1, t.sub.1t.sub.2 and t.sub.2t.sub.B, determining S6 whether to insert or bypass the cell 3, during the time sample t.sub.At.sub.1, t.sub.1t.sub.2 or t.sub.2t.sub.B, based on the predicted flux errors F.sub.error (one predicted flux error for if switching is not performed in the time sample (case S4a) and one predicted flux error for if switching is performed in the time sample (case S4b)). By means of the present method, the switching may be performed in the time sample which results in the flux error at the end of the half switching duration (T.sub.sw/2) which is closest to zero. Typically, only one switching operation (insert or bypass) is performed per half switching duration, but, as discussed herein, a second and possibly even a third or further switching operation may in some embodiments be performed (in different time samples) if it results in a smaller flux error at the end of the half switching duration.

(34) For instance, each T.sub.sw/2 (e.g. of 100 to 500 microseconds) may e.g. be divided into hundred time samples (e.g. each of ten microsecond or less) and the flux error is predicted S5 in each sample and it is determined S6 whether to insert or bypass or do nothing in the present time sample (for each and every sample of the 100 samples this predictive calculation S5 is performed).

(35) When we are in the first sample and we have got the u.sub.ref from the current control 11, we now have to predict S3 the u.sub.ref waveform for the rest 99 samples e.g. based on liner/higher order interpolation technique. Note that the u.sub.ref for the next 99 sample may be the same as present sample. But it may be good to predict the curve rather than keeping it constant. And when we are in the second sample, we try to predict the rest 98 samples for u.sub.ref. Note that now we have two sample information to predict the rest 98 so the predicted S3 curve may be different from the previous prediction, but typically by a small amount. We may use a prediction window of the half switching duration (100 samples) from past/present u.sub.ref and use this information to predict S3 the u.sub.ref of the present/next half switching duration.

(36) We may also calculate the actual flux error of the previous switching duration, F.sub.err(k).
F.sub.err=[U.sub.ref(k1)U.sub.leg(k1)]*T.sub.s+F.sub.err(k1)Equation 4

(37) where

(38) $\begin{array}{cc}{U}_{\mathrm{leg}}\left(k-1\right)=\underset{i=1}{\overset{N}{.Math.}}\frac{S_i\left(k-1\right)*U_{dc,i}\left(k-1\right)}{N}& \mathrm{Equation}5\end{array}$

(39) U.sub.ref (k1) is the previous sample obtained voltage reference,

(40) U.sub.leg(k1) is the previous sample estimated converter phase leg voltage,

(41) T.sub.s is the sampling time of the control unit 10 (to the time duration between t.sub.A and t.sub.1 or t.sub.1 and t.sub.2, etc.),

(42) S.sub.i(k1) is the previous sample switching state of the cells in the converter phase leg,

(43) N is the number of cells 3 in the converter phase leg 2,

(44) U.sub.dc,i(k1) refers to the previous sample sensed cell capacitor voltages in the phase leg.

(45) Then we may calculate the required Volt-Second (i.e. flux) in view of the u.sub.ref for the present half switching duration, which may be calculated as follows

(46) $\begin{array}{cc}{\mathrm{VS}}_{U_{\mathrm{ref}}}=F_{\mathrm{err}}\left(k\right)+\underset{i=k}{\overset{k+N_{\mathrm{sam}}}{.Math.}}{U}_{\mathrm{ref}}\left(i\right)*T_s,& \mathrm{Equation}6\end{array}$

(47) Where:

(48) The values of reference voltage, U.sub.ref(k+1) to U.sub.ref(k+N.sub.sam) is predicted based on present U.sub.ref(k) and previous U.sub.ref(k1) time sample values.

(49) N.sub.sam=N.sub.samI-1 when we are in the first sample for the half switching duration. Now say the time has passed by one microsecond and we are in the second sample of the 100 samples. Then, N.sub.sam in Equation 4 will change to N.sub.samI-2 and when we are in the 3.sup.rd sample of the 100 samples, N.sub.sam=N.sub.samI-3 and so on.

(50) We may calculate the actual Volt-Second (flux) generated due to the output voltage u.sub.leg for the half switching duration if no cell 3 is inserted/bypassed and if one cell is inserted/bypassed, which may be calculated as follows
VS.sub.U.sub.leg=.sub.i=k.sup.k+N.sup.samU.sub.leg(i)*T.sub.s,Equation 7

(51) Where:

(52) The present sample value of leg voltage, U.sub.leg(k) is calculated as

(53) $\begin{array}{cc}{U}_{\mathrm{leg}}\left(k\right)=U_{\mathrm{leg}}\left(k-1\right)+\frac{N_I}{C}{I}_{\mathrm{leg}}\left(k-1\right)*T_s& \mathrm{Equation}8\end{array}$

(54) U.sub.leg(k1) is calculated in accordance with equation 5, and

(55) I.sub.leg(k1) is the sensed current flowing through the phase leg for the previous time sample.

(56) The values of U.sub.leg(k+1) to U.sub.leg(k+N.sub.sam) are calculated using equation 8 and predicted values of current I.sub.leg(k) to I.sub.leg(k+N.sub.sam-1) based on previous I.sub.leg(k1) time sample values.

(57) If e.g. we are in the 63.sup.rd sample of the hundred in real time and our calculations based on predicted S5 flux error shows that we should insert (or bypass) a cell in the present sample to achieve zero flux error at the end of the half switching time period. The command to insert (or bypass) a cell 3 is generated and a cell is inserted (or bypassed) in the real system. The cell 3 to be inserted may be chosen based on any known sorting algorithm.

(58) Then we need to calculate the required Volt-Second due to U.sub.ref for this half switching sample, which can be calculated as follows,

(59) Note that we decided to switch in the 63.sup.rd sample based on the reference voltage at the 63.sup.rd sample and the prediction S3 for the remaining time of T.sub.sw/2 current and cell voltages at the time of the 63.sup.rd sample. This may change when time progresses, which means that the flux error may not go exactly to zero as predicted at the 63.sup.rd sample. When we then are in e.g. the 85.sup.th sample and we see that with the present voltage output u.sub.leg and reference voltage u.sub.ref and making similar calculations S4 and S5 the flux error is no longer predicted to reach zero but still within a predetermined range around zero, then we determined S6 not to perform a switching. However, when we are in e.g. the 90.sup.th sample and performing similar calculations S4 and S5 shows that the predicted flux error at the last sample of present T.sub.sw/2 is not zero and outside the predetermined range, then we determine S6 to allow one more switching within the present T.sub.sw/2 duration. Again, the same process may follow in which we check if we have to do the additional switching now, in the 90.sup.th sample or in a coming sample. Note that the concept of allowing more than one switching to make the predicted flux error to zero, within the present T.sub.sw/2, when the predicted S5 flux error at the end of the present T.sub.sw/2 (for the case S4a that no switching is performed) is outside a predetermined range is optional but may be very convenient is some embodiments of the present invention. Extra switching may generate even less lower order harmonic spectrum, even at very low (fundamental or close to fundamental) switching frequencies. In addition to the flux error predicted S5, we may also add the real flux error at the end of the previous half switching duration T.sub.sw/2, to cancel any error from the previous durations.

(60) Note that, though we choose the switching instant (in which sample to switch) to make the flux error to be zero, it may not always become zero in reality since circumstances (e.g. the reference voltage u.sub.ref, which the current control 11 may update e.g. every 100 microseconds) may change. Also, we may allow a flux error which is less than the predetermined range and only if it exceeds the range, we perform additional switching to make it zero within the same half switching duration. So, this flux error which is within the range in the present half switching duration may be corrected in the next half switching duration.

(61) The control unit 10 may be caused to perform the method by means of running a computer program, as presented above. This computer program may be stored in the storage unit of the control unit 10, or be stored on an external medium, to form a computer program product. The computer program product comprises a computer readable (non-volatile) medium comprising a computer program in the form of computer-executable components. The computer program/computer-executable components may be configured to cause a control unit 10, e.g. as discussed herein, to perform an embodiment of the method of the present disclosure. The computer program/computer-executable components may be run on the processor circuitry of the control unit 10 for causing it to perform the method. The computer program product may e.g. be comprised in a storage unit or memory comprised in the control unit 10 and associated with the processor circuitry. Alternatively, the computer program product may be, or be part of, a separate, e.g. mobile, storage means, such as a computer readable disc, e.g. CD or DVD or hard disc/drive, or a solid state storage medium, e.g. a RAM or Flash memory.

Example

(62) In FIGS. 4a, 4b and 4c, an example algorithm for performing some embodiments of the present invention.

(63) V.sub.dc,nom is the nominal cell DC voltage

(64) NL is the number of cells 3 in one arm 2 of the converter 1

(65) PN is the pulse number per cell 3

(66) F.sub.s is the fundamental frequency of the converter 1

(67) The Duty may be 0.3

(68) Ex_Sw is the number of additional switching(s) allowed in the half switching duration

(69) pIns is the number of cells that are inserted with positive polarity at any given time instant

(70) nIns is the number of cells that are inserted with negative polarity at any given time instant

(71) SetP, SetN, RstP and RstN are the switching commands to insert a cell with positive polarity, insert a cell with negative polarity, bypass a cell inserted with positive polarity and bypass a cell inserted with negative polarity respectively.

(72) SS and AA are variables that are used to control the number of switchings performed in a half switching duration.

(73) Based on the information of the flux VS.sub.leg generated by the leg 2 and the reference flux VS.sub.ref based on the reference voltage u.sub.ref, some conditional logic is used to generate the insert/bypass command. An example of this logic is shown in the FIG. 4.

(74) Now that we generated the insert/bypass command (as a result of the determining S6), a cell sorting algorithm is used to identify which cell 3 is to be inserted/bypassed. Any cell sorting algorithm may be used.

(75) So, we want to switch once, i.e. give one insert or bypass command in every half switching T.sub.sw/2. But during low switching frequency operation (i.e., fundamental frequency switching), if we only switch once every T.sub.sw/2, then the flux error may reach high values at the end of the half switching duration rather than going to zero, especially at the high slope regions of the voltage reference. To prevent this from happening, we also allow additional switching(s) to occur within a T.sub.sw/2.

(76) When to allow more than one switching for every T.sub.sw/2:

(77) If the predicted flux error at the end of the present T.sub.sw/2 (or the N.sub.samI.sup.th sample) is predicted S5 to be more than a predetermined threshold value, then additional switching within the present T.sub.sw/2 is allowed. The maximum number of additional switchings that are allowed within a T.sub.sw/2 may be predefined. Usually it is sufficient to allow 1 or 2 additional switchings to get very good harmonic spectrum especially in the lower order harmonics.

(78) $\begin{array}{cc}{F}_{\mathrm{err},\mathrm{Predict}}=.Math.\begin{array}{cc}{\mathrm{VS}}_{U_{\mathrm{ref}}}& {\mathrm{VS}}_{U_{\mathrm{leg},o}}.Math.\end{array}& \mathrm{Equation}9\end{array}$

(79) Where VSu.sub.leg,o corresponds to flux error when no switching is performed.
F.sub.err,lim=Duty*V.sub.dc,norm*N.sub.samI*T.sub.sEquation 10

(80) Where:

(81) Duty is a user defined gain varied between 0-1, and

(82) V.sub.dc,nom is the nominal cell capacitor voltage.

(83) The present disclosure has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims.