Multi-branch outphasing system and method

Abstract

A multi-level, multi-branch outphasing amplifier (20-1) includes a first branch group circuit (22-1) including a first branch circuit (11) receiving a first RF input signal (S.sub.1(t)) and first control information (S.sub.11.sub._Ctrl=V.sub.DD) and a second branch circuit (12) receiving the first input signal and second control information (S.sub.12.sub._Ctrl). Each of the first (11) and second (12) branch circuits includes a power amplifier. The second control information enables the second branch circuit to be switched on or off while the first branch circuit (12) remains on. A second branch group circuit (22-2) includes a third branch circuit (21) receiving a second RF input signal (S.sub.2(t)) and third control information (S.sub.21.sub._Ctrl=V.sub.DD) and a fourth branch circuit (22) receiving the second input signal (S.sub.2(t)) and fourth control information (S.sub.22.sub._Ctrl). Each of the third and fourth branch circuits includes a power amplifier. The fourth control information enables the fourth branch circuit to be switched on or off while the third branch circuit remains on. A combiner (24) combines output signals of the power amplifiers to produce an output signal (S.sub.OUT(t)).

Claims

1. A multi-level, multi-branch outphasing amplifier comprising: a first branch group circuit including: a first branch circuit including a first activation circuit and a first power amplifier, the first activation circuit coupled to receive an RF first input signal and a first control signal, the first activation circuit configured to selectively enable and disable the RF first input signal from being transmitted to the first power amplifier responsive to the first control signal; and a second branch circuit including a second activation circuit an a second power amplifier, the second activation circuit coupled to receive the RF first input signal and a second control signal, the second activation circuit configured to selectively enable and disable the RF first input signal from being transmitted to the second power amplifier responsive to the second control signal; a second branch group circuit including: a third branch circuit including a third activation circuit and a third power amplifier, the third activation circuit coupled to receive an RF second input signal and a third control signal, the third activation circuit configured to selectively enable and disable the RF second input signal from being transmitted to the third power amplifier responsive to the third control signal; a fourth branch circuit including a fourth activation circuit and a fourth power amplifier, the fourth activation circuit coupled to receive the RF second input signal and a fourth control signal, the fourth activation circuit configured to selectively enable and disable the RF second input signal from being transmitted to the fourth power amplifier responsive to the fourth control signal; and combiner circuitry for combining output signals of the first, second, third and fourth power amplifiers and producing an output signal across a load; wherein a single constant-value voltage supply supplies power to the first branch group circuit and to the second branch group circuit, and wherein a number of enabled RF input signals in the first branch group circuit and a number of enabled RF input signals in the second branch group circuit is selected to be the same or different depending on a power demand of the load or on a backoff load current.

2. The multi-level, multi-branch outphasing amplifier of claim 1 wherein the first, second, third, and fourth power amplifiers are switching power amplifiers.

3. The multi-level, multi-branch outphasing amplifier of claim 2 wherein the first, second, third, and fourth power amplifiers are class-E power amplifiers.

4. The multi-level, multi-branch outphasing amplifier of claim 2 wherein each of the first, second, third, and fourth amplifiers includes a respective switching transistor having a gate capacitance.

5. The multi-level, multi-branch outphasing amplifier of claim 4 wherein each branch circuit includes a respective driver circuit for charging the gate capacitance of a switching transistor.

6. The multi-level, multi-branch outphasing amplifier of claim 1 further including a third branch group circuit including a fifth branch circuit coupled to receive an RF third input signal, which is a complement of the RF first input signal, and the first control information and a sixth branch circuit coupled to receive the RF third input signal and the second control information; a fourth branch group circuit including a seventh branch circuit coupled to receive an RF fourth input signal which is a complement of the RF second input signal, and the third control information and an eighth branch circuit coupled to receive the RF fourth input signal and the fourth control information, each of the fifth, sixth, seventh, and eighth branch circuits also including a respective power amplifier; and outputs of the corresponding power amplifiers of the fifth, sixth, seventh, and eighth branch circuits coupled to the combining circuitry.

7. The multi-level, multi-branch outphasing amplifier of claim 1 wherein each activation circuit includes a respective logical ANDing circuit.

8. The multi-level, multi-branch outphasing amplifier of claim 1 wherein each of the first, second, third, and fourth control signals is indicative of an amount of power being delivered to the load by the multi-level, multi-branch outphasing amplifier compared to a peak amount of power which the multi-level, multi-branch outphasing amplifier is capable of delivering to the load.

9. The multi-level, multi-branch outphasing amplifier of claim 1 including efficiency enhancement circuitry including a reactive efficiency element coupled between the output of the power amplifiers in the multi-level, multi-branch outphasing amplifier branch circuits of the first branch group circuit and the output of the power amplifier of the corresponding branch circuit of the second branch group circuit to form a resonant network with reactive elements associated with those power amplifiers so as to reduce out-of-phase current when the amount of power delivered to the load is relatively low.

10. The multi-level, multi-branch outphasing amplifier of claim 1 including power enhancement circuitry coupled to the output of one of the power amplifiers so as resonate at a predetermined frequency which is a harmonic frequency of a fundamental frequency of the RF first input signal and thereby reduce a peak transistor drain voltage for all phase angles between the first and second input signals so that a power supply voltage of the multi-level, multi-branch outphasing amplifier can be increased without causing a predetermined transistor drain voltage limitation to be exceeded.

11. The multi-level, multi-branch outphasing amplifier of claim 1, wherein the first and second activation circuits are configured to selectively enable and disable the RF first input signal, and the third and fourth activation circuits are configured to selectively enable and disable the RF second input signal, in dependence on a power demand of the load.

12. A multi-level, multi-branch outphasing amplifier, comprising: a first plurality of branch circuits coupled to receive a first input signal to be amplified, each branch circuit of the first plurality of branch circuits including a respective power amplifier; a second plurality of branch circuits coupled to receive a second input signal to be amplified, each branch circuit of the second plurality of branch including a respective power amplifier, the second input signal being phase-shifted with respect to the first input signal; a third plurality of branch circuits coupled to receive a third input signal to be amplified, each branch circuit of the third plurality of branch circuits including a respective power amplifier, the third input signal being 180 degrees out of phase with respect to the first input signal; a fourth plurality of branch circuits coupled to receive a fourth input signal to be amplified, each branch circuit of the fourth plurality of branch circuits including a respective power amplifier, the fourth input signal being 180 degrees out of phase with respect to the second input signal; a combiner circuit coupled to outputs of the power amplifiers of the first, second, third, and fourth pluralities of branch circuits and to generate an output signal for a load, wherein a number of branch circuits in which the respective activation circuits enable the corresponding first, second, third, or fourth input signal is selected to be the same in, or different among, different ones of the first, second, third and fourth pluralities of branch circuits depending on a power demand of the load or on a backoff load current.

13. The multi-level, multi-branch outphasing amplifier of claim 12, wherein each of the branch circuits of the first, second, third, and fourth pluralities of branch circuits includes a respective activation circuit to selectively enable or disable the corresponding first, second, third, or fourth input signal, depending on a power demand of the load, from reaching the corresponding power amplifier.

14. The multi-level, multi-branch outphasing amplifier of claim 12, further comprising a signal generator to generate the first, second, third, and fourth input signals, wherein: the first input signal comprises, for each of the branch circuits of the first plurality of branch circuits, a respective input signal that is separately enabled and disabled by the signal generator; the second input signal comprises, for each of the branch circuits of the second plurality of branch circuits, a respective input signal that is separately enabled and disabled by the signal generator; the third input signal comprises, for each of the branch circuits of the third plurality of branch circuits, a respective input signal that is separately enabled and disabled by the signal generator; and the fourth input signal comprises, for each of the branch circuits of the fourth plurality of branch circuits, a respective input signal that is separately enabled and disabled by the signal generator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram illustrating the technique for generating the phase modulated driving signals for outphasing power amplifiers.

(2) FIG. 2 is a diagram of a conventional asymmetric multi-level outphasing power amplifier.

(3) FIG. 3 is a generalized block diagram of a single-ended multi-level, multi-branch outphasing power amplifier operable from a single supply voltage.

(4) FIG. 4A is a generalized block diagram of a differential multi-level, multi-branch outphasing power amplifier operable from a single supply voltage.

(5) FIGS. 4B and 4C are diagrams illustrating generation of control signals used in the system of FIGS. 3 and 4A.

(6) FIG. 5 is a diagram useful in explaining generation of the phase modulated driving signals for the multi-level, multi-branch outphasing power amplifier of FIGS. 3 and 4A.

(7) FIGS. 6A and 6B are diagrams illustrating an alternative system for generating the RF input signals for the individual power amplifiers in FIG. 4A without requiring use of separate digital control signals.

(8) FIGS. 7A and 7B constitute a schematic diagram of the multilevel, multi-branch outphasing power amplifier of FIG. 4A.

(9) FIG. 8 is a graph illustrating power efficiency versus output power for several variations of the multilevel, multi-branch outphasing power amplifier shown in FIGS. 7A and 7B.

(10) FIG. 9 is a graph illustrating effective efficiency versus output power for the multilevel, multi-branch outphasing power amplifier of FIGS. 7A and 7B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(11) An asymmetric multi-level, multi-branch outphasing power amplifier includes multiple circuits, each of which includes a power amplifier (such as a class-E power amplifier) and combiner circuitry coupled to the output of that power amplifier. A first RF drive signal is coupled to inputs of all the power amplifiers of a first group of branch circuits, and a second RF drive signal is coupled to inputs of all of the power amplifiers of a second group of branch circuits. In one embodiment, each branch circuit of the first group includes an enable circuit or activation circuit that couples or enables the first drive signal to the inputs of the various power amplifiers in the first group of branch circuits in response to a first group of corresponding selection control signals. Similarly, each branch circuit of the second group includes an enable circuit or activation circuit that couples the second drive signal to the inputs of the various power amplifiers in the second group of branch circuits in response to a second group of corresponding selection control signals. In another embodiment, the activation circuits are omitted and instead the control information is in effect contained or embedded in the RF drive signal being applied to each branch circuit in the sense that the RF drive signal is zero if that branch circuit needs to be turned off.

(12) Outputs of the first group of branch circuits all are coupled to inputs of the combiner or combining circuitry. Outputs of the second group of branch circuits are all coupled to inputs of the combiner. An output of the combiner is coupled to a load circuit. The individual branch circuits are in effect turned on and turned off according to power back-off conditions determined by the amount of current required by the load circuit (in contrast to switching between power supply voltages as in the prior art). The branch circuits that are turned ON provide the current presently demanded by the load.

(13) FIG. 3 shows a single-ended multi-level, multi-branch outphasing power amplifier 20-1 which includes a first group 22-1 of branch circuits 11, 12, 13, . . . 1n, and also includes a second group 22-2 of branch circuits 21, 22, 23, . . . 2n. The multi-level, multi-branch outphasing power amplifier 20-1 can operate in symmetric or asymmetric mode. The terms symmetric and asymmetric mean that the number of branches turned ON in the first group and the number of branches turned ON in the second group can be the same (for symmetric operation) or different (for asymmetric operation). Each branch circuit includes an enable/activation circuit, a driver circuit (which may include an even number of series-coupled inverters), and a power amplifier having an output coupled to an input of a combiner. For example, branch 11 includes an enable/activation circuit A11 having a first input coupled by conductor 14A to receive RF drive signal S.sub.1(t) and an enable input coupled to receive a control signal S.sub.11 Ctrl. Input signals S.sub.1(t) and S.sub.2(t) are phase modulated RF signals (similar to the input signals in the above mentioned Godoy reference). The output of enable/activation circuit A11 is connected to the input of driver circuit D11, the output of which is connected to the input of power amplifier P11. The output of power amplifier P11 is coupled to an input of combiner circuitry 24. Combiner 24 has an output coupled to one terminal of a load circuit 25 including a load resistor R having another terminal coupled to ground.

(14) Similarly, branch circuit 12 includes an enable/activation circuit A12 having an input coupled by conductor 14A to receive drive signal S.sub.1(t) and an enable input coupled to receive a control signal S.sub.12.sub._Ctrl. The output of activation circuit A12 is connected to the input of driver circuit D12, the output of which is connected to the input of power amplifier P12. The output of power amplifier P12 is also coupled to an input of combiner circuit 24. The other branch circuits in first group 22-1 are configured similarly. The output S.sub.OUT(t) of combiner 24 is applied to load circuit R.

(15) In second group 22-2, branch circuit 21 includes an activation circuit A21 having a signal input coupled by conductor 14B to receive drive signal S.sub.2(t) and an enable input coupled to receive a control signal S.sub.21.sub._Ctrl. The output of activation circuit A21 is connected to the input of driver circuit D21, the output of which is connected to the input of power amplifier P21. The output of power amplifier P21 is coupled to an input of combiner 24. Branch circuits 22, 23, . . . , 2n are essentially the same as branch circuit 21.

(16) During operation of asymmetric multi-level multi-branch outphasing circuitry 20-1 in FIG. 3, the multiple branch circuits are individually selected or enabled to allow them, in response to the control signals S.sub.11.sub._Ctrl, S.sub.12.sub._Ctrl, S.sub.13.sub._Ctrl, . . . , S.sub.21.sub._Ctrl, S.sub.22.sub._Ctrl, S.sub.23.sub._Ctrl, . . . , etc., to be turned ON and OFF so that they can selectively respond to or not respond to a corresponding one of RF drive signals S.sub.1(t) and S.sub.2(t). Only a single power supply, such as V.sub.DD, is used to provide the operating power to all of the multiple branch circuits of asymmetric multi-level, multi-branch outphasing power amplifier 20-1. (This is in direct contrast to the previously mentioned prior art AMO (asymmetric multi-level outphasing) systems, which all require switching among various power supply voltages to provide operating power to the power amplifiers, respectively, in accordance with the power back-off conditions.) When the maximum allowable current is demanded by the load, all of the branch circuits in the S.sub.1(t) side or section and the S.sub.2(t) side or section are turned ON, and as the load voltage or load current is reduced, individual branch circuits are gradually turned OFF. When the load current required by the load becomes very low, only one branch circuit from each of the S.sub.1(t) section and the S.sub.2(t) section remains turned ON.

(17) FIG. 4A shows a differential multi-level, multi-branch outphasing power amplifier 20-2 which, as in FIG. 3, includes a first group 22-1 of branch circuits 11, 12, 13, . . . 1n, and also includes a second group 22-2 of branch circuits 21, 22, 23, . . . 2n. First group 22-1 and second group 22-2 in FIG. 4A are identical to first group 22-1 and second group 22-2 in FIG. 3.

(18) Differential multi-level, multi-branch outphasing power amplifier 20-2 further includes a third group 22-3 of branch circuits 11, 12, 13, . . . 1n and a fourth group 22-4 of branch circuits 21, 22, 23, . . . 2n. Third group 22-3 and fourth group 22-4 in FIG. 4A are structurally identical to first group 22-1 and second group 22-2, respectively. The power amplifier outputs of third group 22-3 and fourth group 22-4 are coupled to inputs of combiner 24. Combiner 24 has an output S.sub.OUT(t) coupled to load resistor R.

(19) The designations of the drive signals and components in third group 22-3 and fourth group 22-4 are the same as for first group 22-1 and second group 22-2, respectively, except that the designation for each drive signal and each component in third group 22-3 and fourth group 22-4 is followed by the prime character (). For example, in third group 22-3, branch 11 includes an activation circuit A11 having a signal input coupled by conductor 14A to receive drive signal S.sub.1(t) and an enable input coupled to receive the control signal S.sub.11.sub._Ctrl. The output of activation circuit A11 is connected to the input of driver circuit D11, the output of which is connected to the input of power amplifier P11. The output of power amplifier P11 is coupled to an input of combiner 24 and so forth, and similarly for fourth group 22-4 and RF drive signal S.sub.2(t). The drive signals SAO and S.sub.2(t) are phase shifted 180 with respect to (i.e., are the complements of) the drive signals S.sub.1(t) and S.sub.2(t), respectively. (Combiner block 24 consists of various passive circuit elements, for example as shown in subsequently described FIGS. 7A and 7B, and are coupled to the various power amplifiers and are selected to match their output impedance to the impedance of the load circuit so as to achieve maximum power transfer and also are selected to effectively combine the output signals of the various branch groups 22-1, 22-2, 22-3, and 22-4 and couple them to the load.)

(20) Conceptually, the basic operation of the multi-level, multi-branch outphasing power amplifiers of FIGS. 3 and 4A is generally similar to the operation of known multi-level outphasing power amplifiers, but instead of switching between various power supply voltages, various numbers of branch circuits are selectively turned on and off, depending on the back-off load current and the load power requirement of the multi-branch outphasing amplifiers, wherein the objective is to improve efficiency by minimizing phase difference () between the driving waveforms and by turning off branch circuits whenever possible according to power back-off requirements.

(21) Thus, FIGS. 3 and 4A show single-ended and differential implementations, respectively, of the multi-level, multi-branch outphasing power amplifier technique described herein. Generation of the RF drive signals S.sub.1(t) and S.sub.2(t) and S.sub.1(t) and S.sub.2(t) is explained with reference to subsequently described FIGS. 4B, 4C, and 5. The control signals S.sub.11.sub._Ctrl, S.sub.12.sub._Ctrl, S.sub.13.sub._Ctrl, . . . , S.sub.21.sub._Ctrl, S.sub.22.sub._Ctrl, S.sub.23.sub._Ctrl, . . . , etc., in FIG. 4A are used with enable/activation circuits to either apply S.sub.1(t) and S.sub.2(t) and S.sub.1(t) and S.sub.2(t) signals to the respective branch circuits to enable (i.e., turn them on) or to disable (i.e., turn them off).

(22) Alternatively, however, instead of using the above control signals, RF signals can be generated for every branch, as subsequently explained with reference to FIGS. 6A and 6B. In that case more input signals will be required, but the activation circuits would not be required.

(23) The power amplifiers (PAs) can be implemented by means of various kinds of switched-mode power amplifiers (such as class-D, class-E, class-F, etc.) and the combiner circuits may be implemented by means of various kinds of outphasing combiners (such as isolated or non-isolated combiners, passive combiners, transmission lines, Chireix combiners, . . . etc.

(24) FIG. 4B shows the typical normalized output voltage of multi-level, multi-branch outphasing amplifier 20-2 of FIGS. 3 and 4A across the load R. The normalized waveform is divided into segments or regions A, B, . . . , K, according to the load voltage levels, wherein different load voltage levels are indicated by the horizontal dotted lines.

(25) The multi-branch outphasing signal generation circuit 47 in FIG. 4C generates the control signals S.sub.11.sub._Ctrl, S.sub.12.sub._Ctrl, S.sub.13.sub._Ctrl, . . . , S.sub.21.sub._Ctrl, S.sub.22.sub._Ctrl, S.sub.23.sub._Ctrl, . . . , etc., so as to suitably adapt the operation of multi-level, multi-branch outphasing amplifiers 20-1 and 20-2 of FIGS. 3 and 4A to the present amount of output current or power being demanded by the load R according to the input data and modulation technique used.

(26) The control signals S.sub.11.sub._Ctrl, S.sub.12.sub._Ctrl, S.sub.13.sub._Ctrl, . . . , S.sub.21.sub._Ctrl, S.sub.22.sub._Ctrl, S.sub.23.sub._Ctrl, . . . , etc. are generated based on instantaneous amplitude levels of S(t). FIG. 4B shows an example of multi-branch outphasing PA which has two branches for the S.sub.1(t) section and two branches for the S.sub.2(t) section therefore generates the four control signals S.sub.11.sub._Ctrl, S.sub.12.sub._Ctrl, S.sub.21.sub._Ctrl and S.sub.22.sub._Ctrl such that one branch circuit from the S.sub.1(t) section and one branch circuit from the S.sub.2(t) section remain always turned ON (S.sub.11.sub._Ctrl and S.sub.21.sub._Ctrl are always equal to 1), similarly to the example shown and subsequently described in FIGS. 7A and 7B. The regions A, B, . . . , K in FIG. 4B are determined by instantaneous amplitude level of S(t) as shown by the horizontal dotted lines (the control signals change when the instantaneous amplitude level of S(t) crosses the horizontal dotted lines), and the corresponding control signal levels are shown in Table 1.

(27) TABLE-US-00001 TABLE 1 A: S.sub.12_Ctrl = 1, S.sub.22_Ctrl = 1 B: S.sub.12_Ctrl = 1, S.sub.22_Ctrl = 0 C: S.sub.12_Ctrl = 0, S.sub.22_Ctrl = 0 D: S.sub.12_Ctrl = 1, S.sub.22_Ctrl = 0 E: S.sub.12_Ctrl = 0, S.sub.22_Ctrl = 0 F: S.sub.12_Ctrl = 1, S.sub.22_Ctrl = 0 G: S.sub.12_Ctrl = 1, S.sub.22_Ctrl = 1 H: S.sub.12_Ctrl = 1, S.sub.22_Ctrl = 0 I: S.sub.12_Ctrl = 0, S.sub.22_Ctrl = 0 J: S.sub.12_Ctrl = 1, S.sub.22_Ctrl = 0 K: S.sub.12_Ctrl = 0, S.sub.22_Ctrl = 0 (S.sub.11_Ctrl = 1 S.sub.21_Ctrl = 1 always)

(28) FIG. 5 indicates generally how the input drive signals S.sub.1(t) and S.sub.2(t) for the multi-level multi-branch outphasing power amplifiers shown in FIGS. 3 and 4 are produced from an amplitude and phase modulated signal S(t). (The RF signals S(t), S.sub.1(t), and S.sub.2(t) are represented in FIG. 5 by the illustrated vectors.) In this case, the number n of branch circuits of the asymmetric, multi-level, multi-branch outphasing amplifiers of FIGS. 3 and 4 determines the number n of different amplitude levels (and hence the number of concentric circles in FIG. 5) of the drive signal vectors S.sub.1(t) and S.sub.2(t). In the example of FIG. 5, the RF drive signal generation is indicated for two branch circuits, i.e., for the case wherein n=2. The two radii A.sub.1 and A.sub.2 of the half-circles 17D and 17E, respectively, in FIG. 5 indicate the length of the RF drive signal vectors S.sub.1(t) and S.sub.2(t). A.sub.1 corresponds to the case wherein only one branch circuit is enabled or turned on and A.sub.2 corresponds to the case when both branch circuits are enabled or turned on. The following three cases illustrate the generation of drive signals S.sub.1(t) and S.sub.2(t): (1) When 0a(t)2A.sub.1, the signal generation is similar to conventional outphasing signal generation with A=A.sub.1. In this case S.sub.11.sub._Ctrl=1, S.sub.12.sub._Ctrl=0, S.sub.21.sub._Ctrl=1, and S.sub.22.sub._Ctrl=0 to turn on only one branch from the S.sub.1(t) and S.sub.2(t) sides of the diagrams of FIGS. 3 and 4. (2) When A.sub.1+A.sub.2<a(t)2A.sub.2, the signal generation scheme is same as the conventional outphasing signal generation with A=A.sub.2. In this case S.sub.11.sub._Ctrl=1, S.sub.12.sub._Ctrl=1, S.sub.21.sub._Ctrl=1, and S.sub.22.sub._Ctrl=1 to turn on both of the branch circuits from S.sub.1(t) and S.sub.2(t) sides of the diagrams of FIGS. 3 and 4. (3) For 2A.sub.1a(t)A.sub.1+A.sub.2, the signals can be generated as follows:
S.sub.1(t)=A.sub.1e.sup.j[(t)+.sup.1.sup.(t)]
S.sub.2(t)=A.sub.2e.sup.j[(t).sup.2.sup.(t)]

(29) ${}_1\left(t\right)={\cos }^{-1}\left[\frac{A_1^2+{.Math.a\left(t\right).Math.}^2-A_2^2}{2.Math.a\left(t\right).Math.A_1}\right]$${}_2\left(t\right)={\cos }^{-1}\left[\frac{A_2^2+{.Math.a\left(t\right).Math.}^2-A_1^2}{2.Math.a\left(t\right).Math.A_2}\right].$

(30) In this case S.sub.11.sub._Ctrl=1, S.sub.12.sub._Ctrl=0, S.sub.21.sub._Ctrl=1, and S.sub.22.sub._Ctrl=1 to turn on only one branch of the S.sub.1(t) side and both of the branch circuits of S.sub.2(t) sides. (Note that in the description of the previous examples for these conditions it was shown only that one branch of the S.sub.2(t) side and both of the branch circuits of S.sub.1(t) sides were turned ON.)

(31) The described multi-branch outphasing power amplifier can be used in the following different modes:

(32) (i) assymetric multi-level, multi-branch outphasing: the S.sub.1(t) and S.sub.2(t) vectors can be of the same length or different length; the magnitude level and the phase of the S.sub.1(t) and S.sub.2(t) vectors change depending on the envelope power level;

(33) (ii) symmetric multi-level, multi-branch outphasing: the S.sub.1(t) and S.sub.2(t) vectors are always of same length but magnitude level and phase of the S.sub.1(t) and S.sub.2(t) vectors change depending on the envelope power level; and

(34) (iii) single level multi-branch outphasing: the S.sub.1(t) and S.sub.2(t) vectors are always of same length and magnitude of the S.sub.1(t) and S.sub.2(t) vectors always remain same, but phase of the S.sub.1(t) and S.sub.2(t) vectors change depending on the envelope power level. An advantage of having multiple branch circuits in single level operation mode is it allows increasing the amount of peak output power delivered to the load by combining output power (and current) of multiple branches.

(35) The control signals S.sub.11.sub._Ctrl, S.sub.12.sub._Ctrl, S.sub.13.sub._Ctrl, . . . , S.sub.21.sub._Ctrl, S.sub.22.sub._Ctrl, S.sub.23.sub._Ctrl, . . . , etc., change at the modulation envelope frequency of the RF signal S(t). The overall multi-level, multi-branch outphasing power amplifier operation is generally similar to the conventional AMO operation except that instead of using multiple power supply voltage sources to adjust the amount of power delivered to the load in accordance with the current required by the load, multiple branch circuits are utilized to generate different magnitudes of the signals S.sub.1(t) and S.sub.2(t), i.e., to create different vector lengths of S.sub.1(t) and S.sub.2(t) in FIG. 5. When the load requires only a very small current to be supplied to it, a large phase angle is needed between S.sub.1(t) and S.sub.2(t) and most of the PA branch circuits are turned off and only one or a few low-current-supplying branch circuits are turned on so that the total delivered load current is appropriately small. In contrast, in a conventional AMO architecture, the required very low power output level is achieved by switching to a particular low voltage power supply.

(36) Instead of using activation/enable circuits controlled by the above-mentioned control signals S.sub.11.sub._Ctrl, S.sub.12.sub._Ctrl, S.sub.13.sub._Ctrl, . . . , S.sub.21.sub._Ctrl, S.sub.22.sub._Ctrl, S.sub.23.sub._Ctrl, . . . , etc., to control the individual power amplifiers, the control information may be contained or embedded in the RF signals applied to the inputs of the various power amplifiers P11, P12, etc., as shown by the 8 waveforms in FIG. 6A. FIG. 6A illustrates the above-mentioned RF signals for the various power amplifier drive signals S.sub.11(t), S.sub.12(t), . . . and S.sub.21(t), S.sub.22(t), . . . . For example, in FIG. 6A, it will be assumed that branch circuits 11, 11, 21, and 21 are always ON, and the remaining branch circuits can be turned either ON or OFF in accordance with the previously mentioned various power back-off-levels. In this example, the RF input signals S.sub.11(t), S.sub.11(t), S.sub.21(t), and S.sub.21(t) are applied to the inputs of individual power amplifiers P11, P11, P21, and P21, respectively, and will be continuous, i.e., always switching, and always delivering power to the load R as shown in FIG. 6A. The remaining RF input signals S.sub.12(t), S.sub.12(t), S.sub.22(t), and S.sub.22(t) applied to the inputs of individual power amplifiers P12, P12, P22, and P22, respectively, can be non-switching for some of the time and can be switching for the rest of the time in accordance with the previously mentioned various power back-off-off levels.

(37) Referring to FIG. 6B, the signal S(t), which represents the load current level or other signal representative of the output power level delivered to load R, is provided as an input to multi-branch outphasing signal generation circuit 50. Multi-branch outphasing signal generation circuit 50 in FIG. 6B accordingly generates the various RF power amplifier drive signals S.sub.11(t), S.sub.11(t), . . . and S.sub.21(t), S.sub.22(t), . . . that are provided as inputs to the corresponding power amplifiers P11, P12, etc., such that each output signal of multi-branch outphasing signal generation circuit 50 is either a switching signal or is instead equal to 0 in accordance with the present back-off requirement. For example, when all of the individual branch circuits are in effect turned ON and are delivering power to the load R, every branch circuit will be receiving the RF switching signal. For lower load current or load power levels, one or more of the branch circuits will be receiving a 0 value of its RF input signal. As is evident from the waveforms shown in FIG. 6A, the non-zero portions of the signals S.sub.12(t), S.sub.12(t), S.sub.22(t), and S.sub.22(t) are identical to corresponding portions of drive signals S.sub.1(t) and S.sub.2(t), and all portions of the waveforms of S.sub.11(t), S.sub.11(t), S.sub.21(t), and S.sub.21(t) are always identical to corresponding portions of drive signals S.sub.1(t) and S.sub.2(t). It is evident that this RF signal generation technique requires more signals (i.e., 8 signals vs. 4 signals) to be generated than is the case in which drive signals S.sub.1(t) and S.sub.2(t) and control signals S.sub.12.sub._Ctrl and S.sub.22.sub._Ctrl are required (S.sub.11.sub._Ctrl and S.sub.21.sub._Ctrl are always equal to 1). (That is, 8 signals vs. 4 signals in previous case, i.e., S.sub.1(t), S.sub.2(t), S.sub.12.sub._Ctrl and S.sub.22.sub._Ctrl).

(38) FIGS. 7A and 7B illustrate a practical implementation of a differential, asymmetric, multi-level, multi-branch outphasing power amplifier generally based on the multi-branch outphasing power amplifier block diagram shown in FIG. 4A. In FIGS. 7A and 7B, the first group of branch circuits 22-1 includes an upper branch circuit 12 and a lower branch circuit 11. The upper branch circuits and lower branch circuits are sized differently. The sizing of the branch circuits is determined by the signal statistics and the power levels at which efficiency peaks are located. The lower branch circuit 11 includes an AND gate 37-1, which corresponds to enable/activation circuit A11 in FIG. 4A. A first input of AND gate 37-1 receives control signal S.sub.11.sub._Ctrl equal to V.sub.DD and a second input of AND gate 37-1 receives the drive signal S.sub.1(t). The output of AND gate 37-1 is connected to the input of a driver circuit 38-1 which corresponds to driver circuit D11 in FIG. 4A. The class-E power amplifier 40-1 in FIGS. 7A and 7B corresponds to power amplifier P11 in FIG. 4A. Class-E power amplifier 40-1 includes an N-channel MOS switching transistor M.sub.A, a N-channel cascode transistor N.sub.A, an inductor L.sub.C1, and a capacitor C.sub.P1. (The capacitors C.sub.P1 and C.sub.P2 can be the output capacitance of power amplifier or a parallel combination of output capacitor of the power amplifier and an external capacitor.) The gate of switching transistor M.sub.A is connected to the output of driver circuit 38-1. The source of switching transistor M.sub.A is connected to ground, and its drain is connected to the source of cascode transistor N.sub.A. The gate of cascode transistor N.sub.A is connected to a cascode bias voltage Bias, and its drain is connected to one terminal of inductor L.sub.C1, to one terminal of an inductor L.sub.A, and to one terminal of capacitor C.sub.P1. The other terminal of inductor L.sub.C1 is connected to power supply voltage V.sub.DD.

(39) The upper branch circuit 12 of the first group 22-1 includes an AND gate 37-2, which corresponds to enable/activation circuit A12 in FIG. 4A. A first input of AND gate 37-2 receives control signal S.sub.12.sub._Ctrl and a second input of AND gate 37-2 receives the drive signal S.sub.1(t). The output of AND gate 37-2 is connected to the input of a driver circuit 38-2 which corresponds to driver D12 in FIG. 4A. A class-E power amplifier 40-2 in FIGS. 7A and 7B corresponds to power amplifier P12 in FIG. 4A. Class-E power amplifier 40-2 includes an N-channel MOS switching transistor M.sub.B, a N-channel cascode transistor N.sub.B, an inductor L.sub.C2, and a capacitor C.sub.P2. The gate of switching transistor M.sub.B is connected to the output of driver circuit 38-2. The source of switching transistor M.sub.B is connected to ground and its drain is connected to the source of cascode transistor N.sub.B. The gate of cascode transistor N.sub.B is connected to cascode bias voltage Bias, and its drain is connected to one terminal of an inductor L.sub.C2, to one terminal of an inductor L.sub.B, and to one terminal of capacitor C.sub.P2. The other terminal of inductor L.sub.C2, is connected to V.sub.DD.

(40) In FIGS. 7A and 7B, the second group of branch circuits 22-2 includes an upper branch circuit 21 and a lower branch circuit 22. The lower branch circuit includes an AND gate 37-4, which corresponds to activation circuit A22 in FIG. 4A. A first input of AND gate 37-4 receives control signal S.sub.22.sub._Ctrl and a second input of AND gate 37-4 receives the drive signal S.sub.2(t). The output of AND gate 37-4 is connected to the input of a driver circuit 38-4 which corresponds to driver D22 in FIG. 4A. A class-E power amplifier 40-4 in FIGS. 7A and 7B corresponds to power amplifier P22 in FIG. 4A. Class-E power amplifier 40-4 includes an N-channel MOS switching transistor M.sub.B, an N-channel cascode transistor N.sub.B, an inductor L.sub.C2, and a capacitor C.sub.P2. The gate of switching transistor M.sub.B is connected to the output of driver circuit 38-4. The source of switching transistor M.sub.B is connected to ground and its drain is connected to the source of cascode transistor N.sub.B. The gate of cascode transistor N.sub.B is connected to cascode bias voltage Bias, and its drain is connected to one terminal of inductor L.sub.C2, to one terminal of an inductor L.sub.B, and to one terminal of capacitor C.sub.P2. The other terminal of inductor L.sub.C2, is connected to V.sub.DD.

(41) The upper branch circuit 21 of the second group 22-2 includes an AND gate 37-3, which corresponds to activation circuit A21 in FIG. 4A. A first input of AND gate 37-3 receives control signal S.sub.21.sub._Ctrl equal to V.sub.DD and a second input of AND gate 37-3 also receives the drive signal S.sub.2(t). The output of AND gate 37-3 is connected to the input of a driver circuit 38-3 which corresponds to driver D21 in FIG. 4A. A class-E power amplifier 40-3 in FIGS. 7A and 7B corresponds to power amplifier P21 in FIG. 4A. Class-E power amplifier 40-3 includes an N-channel MOS switching transistor M.sub.A, an N-channel cascode transistor N.sub.A, an inductor L.sub.C1, and a capacitor C.sub.P1. The gate of switching transistor M.sub.A is connected to the output of driver circuit 38-3. The source of switching transistor M.sub.A is connected to ground and its drain is connected to the source of cascode transistor N.sub.A. (The driver circuits D11, D12, . . . etc. typically are required because the switching transistors M.sub.A and M.sub.B of the power amplifiers are very large transistors with a very large gate capacitance.) The gate of cascode transistor N.sub.A is connected to cascode bias voltage Bias, and its drain is connected to one terminal of an inductor L.sub.C1, to one terminal of an inductor L.sub.A, and to one terminal of capacitor C.sub.P1. The other terminal of inductor L.sub.C1 is connected to V.sub.DD.

(42) The implementation of branch groups 22-3 and 22-4 in FIGS. 7A and 7B is essentially the same as the implementation of branch groups 22-1 and 22-2, respectively, except that the drive signals S.sub.1(t) and S.sub.2(t) for branch groups 22-1 and 22-2 are replaced by drive signals S.sub.1(t) and S.sub.2(t) for branch groups 22-3 and 22-4, respectively. The symbols designating the various circuit elements in groups 22-3 and 22-4 are the same as in groups 22-1 and 22-2, respectively, except that each symbol is includes a prime (), except at the control signals on the left side are the same as on the right side.

(43) Specifically, in FIGS. 7A and 7B, the third group of branch circuits 22-3 includes an upper branch circuit 12 and a lower branch circuit 11. The lower branch circuit 11 includes an AND gate 37-1, which corresponds to enable/activation circuit A11 in FIG. 4A. A first input of AND gate 37-1 receives control signal S.sub.11.sub._Ctrl equal to V.sub.DD and a second input of AND gate 37-1 receives the drive signal S.sub.1(t). The output of AND gate 37-1 is connected to the input of a driver circuit 38-1 which corresponds to driver circuit D11 in FIG. 4A. A class-E power amplifier 40-1 in FIGS. 7A and 7B corresponds to power amplifier P11 in FIG. 4A. Class-E power amplifier 40-1 includes an N-channel MOS switching transistor M.sub.A, an N-channel cascode transistor N.sub.A, an inductor L.sub.C1, and a capacitor C.sub.P1. The gate of switching transistor M.sub.A is connected to the output of driver circuit 38-1. The source of switching transistor M.sub.A is connected to ground, and its drain is connected to the source of cascode transistor N.sub.A. The gate of cascode transistor N.sub.A is connected to a cascode bias voltage Bias, and its drain is connected to one terminal of inductor L.sub.C1, to one terminal of an inductor L.sub.A, and to one terminal of capacitor C.sub.P1. The other terminal of inductor L.sub.C1, is connected to power supply voltage V.sub.DD.

(44) The upper branch circuit 12 of the third group 22-3 includes an AND gate 37-2, which corresponds to enable/activation circuit A12 in FIG. 4A. A first input of AND gate 37-2 receives S.sub.12.sub._Ctrl and a second input of AND gate 37-2 receives the drive signal S.sub.1(t). The output of AND gate 37-2 is connected to the input of a driver circuit 38-2 which corresponds to driver D12 in FIG. 4A. A class-E power amplifier 40-2 in FIGS. 7A and 7B corresponds to power amplifier P12 in FIG. 4A. Class-E power amplifier 40-2 includes an N-channel MOS switching transistor M.sub.B, an N-channel cascode transistor N.sub.B, an inductor L.sub.C2, and a capacitor C.sub.P2. The gate of switching transistor M.sub.B is connected to the output of driver circuit 38-2. The source of switching transistor M.sub.B is connected to ground and its drain is connected to the source of cascode transistor N.sub.B. The gate of cascode transistor N.sub.B is connected to cascode bias voltage Bias, and its drain is connected to one terminal of an inductor L.sub.C2, to one terminal of an inductor L.sub.B, and to one terminal of capacitor C.sub.P2. The other terminal of inductor L.sub.C2 is connected to V.sub.DD.

(45) In FIGS. 7A and 7B, the fourth group of branch circuits 22-4 includes an upper branch circuit 21 and a lower branch circuit 22. The lower branch circuit 22 includes an AND gate 37-4, which corresponds to activation circuit A22 in FIG. 4A. A first input of AND gate 37-4 receives S.sub.22.sub._Ctrl and a second input of AND gate 37-4 receives the drive signal S.sub.2(t). The output of AND gate 37-4 is connected to the input of a driver circuit 38-4 which corresponds to driver D22 in FIG. 4A. A class-E power amplifier 40-4 in FIGS. 7A and 7B corresponds to power amplifier P22 in FIG. 4A. Class-E power amplifier 40-4 includes an N-channel MOS switching transistor M.sub.B, an N-channel cascode transistor N.sub.B, an inductor L.sub.C2, and a capacitor C.sub.P2. The gate of switching transistor M.sub.B is connected to the output of driver circuit 38-4. The source of switching transistor M.sub.B is connected to ground and its drain is connected to the source of cascode transistor N.sub.B. The gate of cascode transistor N.sub.B is connected to cascode bias voltage Bias, and its drain is connected to one terminal of inductor L.sub.C2, to one terminal of an inductor L.sub.B, and to one terminal of capacitor C.sub.P2. The other terminal of inductor L.sub.C2 is connected to V.sub.DD.

(46) The upper branch circuit 21 of the fourth group 22-4 includes an AND gate 37-3, which corresponds to activation circuit A21 in FIG. 4A. A first input of AND gate 37-3 receives control signal S.sub.21.sub._Ctrl equal to V.sub.DD and a second input of AND gate 37-3 also receives the drive signal S.sub.2(t). The output of AND gate 37-3 is connected to the input of a driver circuit 38-3 which corresponds to driver D21 in FIG. 4A. A class-E power amplifier 40-3 in FIGS. 7A and 7B corresponds to power amplifier P21 in FIG. 4A. Class-E power amplifier 40-3 includes an N-channel MOS switching transistor M.sub.A, an N-channel cascode transistor N.sub.A, an inductor L.sub.C1, and a capacitor C.sub.P1. The gate of switching transistor M.sub.A is connected to the output of driver circuit 38-3. The source of switching transistor M.sub.A is connected to ground and its drain is connected to the source of cascode transistor N.sub.A. (The driver circuits D11, D12, . . . etc. typically are required because the switching transistors M.sub.A and M.sub.B of the power amplifiers are very large transistors with a very large gate capacitance.) The gate of cascode transistor N.sub.A is connected to cascode bias voltage Bias, and its drain is connected to one terminal of an inductor L.sub.C1, to one terminal of an inductor L.sub.A, and to one terminal of capacitor C.sub.P1. The other terminal of inductor L.sub.C1 is connected to V.sub.DD.

(47) In FIGS. 7A and 7B, an inductor L.sub.B is connected between conductor 31-1 and conductor 30-1, and similarly, another inductor L.sub.B is connected between conductor 31-3 and conductor 30-2. An inductor L.sub.PEC and capacitor C.sub.PEC are connected in series between conductors 31-1 and 31-3. An inductor L.sub.A is connected between conductor 32-1 and conductor 30-1 and another inductor L.sub.A is connected between conductor 32-3 and conductor 30-2. Another inductor L.sub.PEC and capacitor C.sub.PEC are connected in series between conductors 32-1 and 32-3. Also, another inductor L.sub.A is connected between conductor 32-2 and conductor 30-1 and another inductor L.sub.A is connected between conductor 32-4 and conductor 30-2. Another inductor L.sub.PEC and capacitor C.sub.PEC are connected in series between conductors 32-2 and 32-4. Another inductor L.sub.B is connected between conductor 31-2 and conductor 30-1, and another inductor L.sub.B is connected between conductor 31-4 and conductor 30-2. Another inductor L.sub.PEC and capacitor C.sub.PEC are connected in series between conductors 31-2 and 31-4.

(48) Also, an inductor L.sub.EEC is connected between conductors 32-1 and 32-2, and another inductor L.sub.EEC is connected between conductors 32-3 and 32-4. A capacitor C.sub.A is connected between conductor 30-1 and conductor 34. An output capacitor C.sub.O is connected between conductors 34 and 35, and another capacitor C.sub.A is connected between conductors 35 and 30-2. The primary winding of a transformer T is connected across output capacitor C.sub.O between conductors 34 and 35. A secondary winding of transformer T is connected across a load resistor R, and one terminal of the secondary winding is connected to ground. The output voltage S.sub.OUT(t) is developed across the load resistor R.

(49) It should be understood that individual branch circuits can be sized asymmetrically in order to maximize the power efficiency of the outphasing power amplifier, depending on the characteristics of the amplitude and phase modulated RF signal S(t) such that efficiency peaks are obtained at particular back-off power levels and overall average efficiency is maximized.

(50) In the operation of the asymmetric multi-level, multi-branch outphasing power amplifier of FIGS. 7A and 7B, one S.sub.1(t) (and also one S.sub.1(t)) branch circuit and one S.sub.2(t) (and also one S.sub.2(t)) branch circuit are always turned on, and the other branch circuits are turned on or off in response to the various control signals S.sub.12.sub._Ctrl and S.sub.22.sub._Ctrl.

(51) Each series-connected combination of an inductor L.sub.PEC and a capacitor C.sub.PEC forms a Power Enhancement Circuit (PEC) which can be tuned to the third harmonic of the fundamental RF frequency (although other harmonics could be used), and the result of doing that is to shape the drain voltages of the N-channel cascode transistors N.sub.A and N.sub.B of the class-E power amplifiers such that the peak drain voltages are reduced for all phase angle differences between S.sub.1(t) and S.sub.2(t). This allows increasing the power supply voltage V.sub.DD (thereby also increasing the maximum output power that can be delivered to the load R by each class-E power amplifier) without exceeding the transistor drain voltage reliability limit.

(52) Each inductor L.sub.EEC forms an Efficiency Enhancement Circuit (EEC). The vectors S.sub.1(t) and S.sub.2(t) have in-phase (phase difference is 0) and out-of-phase (phase difference is 180) components. For the in-phase components of the S.sub.1(t) and S.sub.2(t) vectors, the efficiency enhancement circuit EEC does not conduct any current because the voltages on both conductors 32-1 and 32-2 are equal (and the voltages on conductors 32-3 and 32-4 also are equal). But for the out-of-phase components of the S.sub.1(t) and S.sub.2(t) vectors, each inductor L.sub.EEC forms a parallel resonant network with the corresponding capacitor C.sub.P1 and the corresponding inductor L.sub.A and thereby reduces amount of out-of-phase current flowing through the parallel resonant network by presenting a large impedance to the corresponding class-E power amplifier at that resonant frequency. This improves the overall efficiency under large power back-off operating conditions. (Depending on the particular circuit design, the EEC circuit could be a capacitor (C.sub.EEC).

(53) In FIGS. 7A and 7B the switching on and off of the power amplifier switch transistor at the fundamental frequency results in a sinusoidal voltage signal at the fundamental frequency on the drain of the cascode transistor. The above-mentioned power enhancement circuitry (PEC) operates to add a third harmonic (or possibly other harmonics) of the fundamental frequency to the fundamental frequency signal in such a way that the peak drain voltage is reduced. When the phase angle between the RF drive signals S.sub.1(t) and S.sub.2(t) changes with respect to time, the drain voltages also change with respect to time. The third harmonic is added to the fundamental frequency signal in such a way as to decrease the cascode transistor peak drain voltage across all possible values of the phase angle between the S.sub.1(t) and S.sub.2(t) input signals.

(54) Thus, the power enhancement circuitry (PEC) includes L.sub.PEC and C.sub.PEC and operates to reduce the peak drain voltages of the cascode transistors N.sub.A and N.sub.B. This allows the power supply V.sub.DD to be increased without exceeding the allowable transistor drain voltage limits so that a higher amount of peak output power can be delivered to the load resistor R.

(55) FIG. 8 shows simulated curves of efficiency versus output power for the circuitry shown in FIGS. 7A and 7B for different levels of the control signals with and without the efficiency enhancement circuit. FIG. 9 shows an effective (combined) simulated efficiency curve which shows significant improvement in back-off efficiency of the multi-level, multi-branch outphasing power amplifier.

(56) The described asymmetric, multi-level, multi-branch outphasing power amplifiers have a number of advantages over the prior art multi-level outphasing amplifiers. No complex power supply voltage switching circuitry is required. The inefficient supply voltage switching circuitry of prior AMO amplifiers is eliminated and the power loss and undesirably high power inefficiency caused by the power supply voltage switching in the prior AMO amplifiers therefore are avoided. The multi-branch outphasing power amplifier circuit 20-1 is easier to implement than the power supply modulation/switching of the prior AMO amplifiers because generating the multiple power supply voltage levels in prior AMO amplifiers requires multiple regulators circuits and other related circuits which are costly. Also, the power supply switching in the prior AMO amplifiers causes significant signal nonlinearity and also causes another kind of nonlinearity that arises from the inevitable signal timing mismatches between the control signal paths into the power supply switching circuits and the input drive signal paths. The described multi-level, multi-branch outphasing power amplifier avoids such signal timing problems (since all of the signals are applied to the inputs of the switching-mode power amplifiers and they can be easily synchronized) and associated nonlinearity of the outphasing power amplifier output signal by not including such multiple signal paths to supply voltage switching and power amplifier input. Furthermore, the use of multiple separately enabled branch circuits to combine the branch circuit output currents allows a large peak current and a large variation in the amount of total current delivered to the load. Also, the multi-level, multi-branch outphasing amplifier can be operated in either single-level mode or multi-level mode. There is some benefit of having multi-branch structure but operating it in single-level mode, because it can produce higher peak output power levels than a single-branch structure.

(57) While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from its true spirit and scope. It is intended that all elements or steps which are insubstantially different from those recited in the claims but perform substantially the same functions, respectively, in substantially the same way to achieve the same result as what is claimed are within the scope of the invention. For example, some of the disclosed inductors can be interchanged with some of the disclosed capacitors. In some cases, the positions of the L.sub.A, L.sub.B inductors and C.sub.A capacitors may be interchanged. L.sub.EEC can be placed between other branch circuits i.e. one end to 31-1 and other end to 31-2 and for the right side one end to 31-3 and other end to 31-4). In some cases the L.sub.EEC inductor can be replaced by a capacitor. In some cases common components can be utilized to perform the functions of the Efficiency Enhancement Circuit (EEC) and the Power Enhancement Circuit (PEC). Other kinds of combiners can also be used, for example Chireix combiners. The switching power amplifiers could be other types than class-E amplifiers. Also, it would be possible to use RF signals for performing the functions of the disclosed logic signals S.sub.11.sub._Ctrl, S.sub.12.sub._Ctrl, S.sub.13.sub._Ctrl, . . . , S.sub.21.sub._Ctrl, S.sub.22.sub._Ctrl, S.sub.23.sub._Ctrl, . . . , etc. Such RF signals could be configured to appear as switching signals with appropriate phase modulation to the power amplifiers during time intervals in which the receiving power amplifiers should be turned on and to appear as 0s during time intervals in which power amplifiers are to be turned off.