Drift compensation

Abstract

Each realization of an electric circuit design defines a frequency response. For a test lot of the design, frequency responses are measured, each at a stable value of an environment parameter, wherein the totality of the values are distributed over a parameter range. Based on the measurements, a design-specific model is defined that describes a frequency response of the design in dependence of the environment parameter. For a unit in a main lot of realizations of the design, a unit-specific frequency response is measured at a stable value of the environment parameter; the model is fitted to the response, whereby a unit-specific model is obtained; data representing the unit-specific model is stored in association with the unit; and the unit is operated in conjunction with a compensation stage configured to determine a present value of the environment parameter and compensate drift in relation to a parameter-independent reference frequency response.

Claims

1. A method associated with an electric circuit manufactured in accordance with a predefined electric circuit design and defining a frequency response between an input signal and an output signal in a frequency range, the method comprising: ii) defining, based on measurements on a test lot of other electric circuits also manufactured in accordance with the electric circuit design, a design-specific model for the electric circuit design, the design-specific model describing a frequency response of the electric circuit design in dependence of at least one parameter affecting operation of the electric circuit design; and for the electric circuit: iii-1) obtaining a unit-specific frequency response as a frequency response for the electric circuit measured at a certain value of the at least one parameter; iii-2) fitting the design-specific model at said certain value of the at least one parameter to said unit-specific frequency response, whereby a unit-specific model for the electric circuit is obtained describing a frequency response for the electric circuit in dependence of the at least one parameter; and iii-3) storing, in association with the electric circuit, data representing the unit-specific model such that the electric circuit is operable in conjunction with a compensation stage, which is configured to retrieve said data representing the unit-specific model, determine a present value of the at least one parameter and, based on said present value and said unit-specific model, compensate a deviation between a frequency response of said electric circuit and a reference frequency response, wherein the reference frequency response is independent of the at least one parameter.

2. The method of claim 1, further comprising a preceding step of: i) measuring N frequency responses for a test lot of other electric circuits manufactured in accordance with the electric circuit design, wherein each frequency response is measured at a certain value of the at least one parameter and the certain values of the at least one parameter are distributed over a parameter range.

3. The method of claim 1, wherein temperature is one of the at least one parameters.

4. The method of claim 1, wherein: the electric circuit is configured to be powered by a supply voltage; and a voltage of the supply voltage is one of the at least one parameters.

5. The method of claim 1, wherein: the electric circuit is configured for use with a preamplifier; and a gain of said pre-amplifier is one of the at least one parameters.

6. The method of claim 1, wherein step iii-2 includes determining a unit-specific calibration term approximating a deviation between, on the one hand, the design-specific model at said certain value of the at least one parameter and, on the other hand, the unit-specific frequency response.

7. The method of claim 6, wherein the unit-specific model is a sum of three independent contributions: a unit-independent frequency response; a unit-independent compensation term, which varies with the at least one parameter; and the unit-specific calibration term.

8. The method of claim 1, further comprising operating the electric circuit in conjunction with a further electric circuit also manufactured in accordance with the electric circuit design, wherein the reference frequency response is a frequency response of said further electric circuit.

9. The method of claim 8, wherein: the electric circuit is an analog-to-digital converter; and the operating the electric circuit and the further electric circuit includes operating as parallel components of a time-interleaved analog-to-digital conversion system.

10. The method of claim 9, wherein temperature and supply voltage for powering the electric circuit are the at least one parameter.

11. The method of claim 8, wherein: the electric circuit is an analog-to-digital converter; the operating the electric circuit and the further electric circuit includes operating when arranged in parallel branches of an in-phase/quadrature, modulator or I/Q demodulator; and the compensation stage is an I/Q mismatch compensator.

12. The method of claim 11, wherein: a preamplifier is arranged in each branch upstream of a respective one of said electric circuit and said further electric circuit; and temperature and a gain state of the preamplifiers are the at least one parameter.

13. The method of claim 1, wherein: the electric circuit is an analog-to-digital converter, the input signal being an analog signal and the output signal being a digital electric signal; the reference frequency response is unit-independent; the analog-to-digital converter is configured to be powered by a supply voltage; and the at least one parameters are a voltage of the supply voltage and temperature.

14. The method of claim 2, wherein the data stored in step iii-3 represents the unit-specific model in terms of a difference or a ratio with respect to said reference frequency response.

15. The method of claim 1, wherein the electric circuit is a semiconductor circuit, preferably an integrated circuit.

16. A signal processing device comprising: an electric circuit manufactured in accordance with a predefined electric circuit design; a memory storing data representing a unit-specific model for the electric circuit, the unit-specific model describing a frequency response between an input signal and an output signal of the electric circuit, in a frequency range, in dependence of at least one parameter affecting operation of the electric circuit; and a compensation stage configured to retrieve said data from the memory, to determine a present value of the at least one parameter, and, based on said present value and said unit-specific model, to compensate a deviation between a frequency response of said electric circuit and a reference frequency response, wherein the reference frequency response is independent of the at least one parameter, wherein the memory stores at least data of a first type and data of a second type representing the unit-specific model, said first type having been prepared on the basis of a plurality of frequency responses measured for a test lot of other electric circuits also manufactured in accordance with the electric circuit design, and said second type having been prepared on the basis of a measurement of a unit-specific frequency response for the electric circuit at a certain value of the at least one parameter.

17. The signal processing device of claim 16, wherein the compensation stage comprises a sensor for measuring the at least one parameter.

18. A method of operating an electric circuit manufactured in accordance with a predefined electric circuit design, the method comprising: obtaining data representing a unit-specific model for the electric circuit, the unit-specific model describing a frequency response between an input signal and an output signal of the electric circuit, in a frequency range, in dependence of at least one parameter affecting operation of the electric circuit; determining a present value of the at least one parameter; and based on said present value and said unit-specific model, compensating a deviation between a frequency response of said electric circuit and a reference frequency response, wherein the reference frequency response is independent of the at least one parameter, wherein said data includes data of a first type and data of a second type, said first type having been prepared on the basis of a plurality of frequency responses measured for a test lot of other electric circuits also manufactured in accordance with the electric circuit design, and said second type having been prepared on the basis of a measurement of a unit-specific frequency response for the electric circuit at a certain value of the at least one parameter.

19. The method of claim 18, wherein the data represents the unit-specific model as a formula, and said step of compensating a deviation between a frequency response of said electric circuit and a reference frequency response includes evaluating the formula for said present value of the at least one parameter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments will now be described in greater detail and with reference to the accompanying drawings, on which:

(2) FIG. 1A shows an electric circuit design;

(3) FIG. 1B shows an electric circuit design and a corresponding compensation stage, according to one embodiment;

(4) FIG. 2 shows a manufacturing system for realizing an electric circuit design, according to one embodiment;

(5) FIG. 3 shows an electric circuit design with an integrated memory for storing a unit-specific model, according to one embodiment;

(6) FIG. 4 shows a signal processing device with an integrated compensation stage and memory for storing a unit-specific model, according to one embodiment;

(7) FIG. 5 shows a detail of a I/Q demodulator with a compensation stage according to one embodiment;

(8) FIG. 6 shows a time-interleaved ADC with N?2 parallel subconverters and a compensation stage according to one embodiment;

(9) FIGS. 7A, 7B, 7C and 7D show details of time-interleaved ADCs each having four parallel subconverters and at least one compensation stage according to one embodiment; and

(10) FIG. 8 shows a detail of a frequency demodulator with a compensation stage according to one embodiment.

(11) All figures are schematic and generally show only parts that are necessary for the purpose of elucidating the invention, whereas other parts may be omitted or merely suggested.

DETAILED DESCRIPTION OF EMBODIMENTS

(12) FIG. 1A has been briefly discussed above. FIG. 1B shows an identical unit 120.sub.m, which is a realization (in the main lot) of a predefined electric circuit design that is operated in conjunction with a compensation stage 130.sub.m. The compensation stage 130.sub.m may serve the unit 120.sub.m or additional units as well. For the purposes of compensating drift in the unit 120.sub.m, however, the compensation stage 130.sub.m retrieves data representing a unit-specific model Q.sub.m(?; T, V) from a memory 121.sub.m. The unit-specific model predicts a frequency response (including gain, phase or a combination of these quantities) for each value in the allowed range of the operating frequency ? and two environment parameters T and V. The allowed range may for instance be a neighborhood of a triple of nominal values (?.sub.0, T.sub.0, V.sub.0). In the example, the unit-specific model takes into account the effect of one internal and one external quantity, wherein the internal quantity is being read out directly from an electric line, and the external quantity is measured using a sensor 131.sub.m. In variations to this embodiment, the unit-specific model may consider only external or only internal factors, or a combination of any number of each. In the example, the unit-specific model depends of a supply voltage of V [volt], with which the unit 120.sub.m is driven, and a temperature of T [Kelvin]. Here, the voltage can be read out directly from a line parallel to the supply voltage line into the unit 120.sub.m, whereas a dedicated temperature sensor 131.sub.m is arranged in proximity of the unit 120.sub.m and communicatively connected to the compensation stage 130.sub.m.

(13) The compensation stage 130.sub.m may optionally receive the output signal y(t) of the unit 120.sub.m, based on which it may determine a current operating frequency ?. It is emphasized that the compensation stage 130.sub.m need not use the y(t) to determine the current drift of the device; this is instead predicted by the unit-specific model. Alternatively, the compensation stage 130.sub.m receives the input signal x(t) and determines the current operating frequency ? based on that signal. As yet another alternative, the compensation stage 130.sub.m applies frequency-independent compensation, wherein there is no need to determine the current operating frequency ?; in this situation the unit-specific model may be frequency-independent, or may change to such little extent due to frequency, that compensation with reasonable accuracy can be achieved without specific regard to frequency.

(14) By evaluating the unit-specific model for current values of the environment parameters (and optionally, for a current operating frequency), the compensation stage 130.sub.m determines an actual frequency response of the unit 120.sub.m. Based on the actual frequency response and on a predetermined reference frequency response, the compensation stage 130.sub.m outputs a compensation signal, which a summer 132.sub.m adds to the output signal y(t) of the unit 120.sub.m, whereby a compensated output signal z(t) is obtained. In normal operation of the compensation stage 130.sub.m, the drift with respect of the environment parameters of the compensated output signal z(t) (effective drift) is reduced compared to that of the output signal y(t).

(15) As noted previously, the compensation stage 130.sub.m may alternatively access the unit-specific model expressed in terms of an actual deviation from the reference frequency response. One may then typically use a constant multiple of the deviation as the compensation signal to be added to the output signal y(t). This approach may be computationally advantageous and, as explained, advantageous from the point of view of memory usage (efficient quantization/coding; no need to store reference frequency response) as well. If it is expected that the reference frequency response will be substituted over the lifetime of the unit 120.sub.m, however, it may be preferable to store the reference frequency response separately from the unit-specific model.

(16) In an alternative but functionally equivalent implementation, the summer 132 may be replaced by a multiplier (not shown) which acts multiplicatively upon the output signal y(t) in that this signal is rescaled by a factor given by the compensation signal. In this implementation, it may be convenient to represent the unit-specific model as a ratio of a reference frequency response and an actual frequency response of the unit.

(17) FIG. 2 shows a manufacturing system 200, which for simplicity has been drawn as a co-located assembly and in a schematic fashion. It is recalled that the sections of the manufacturing system may well be geographically distributed and/or may be operated in a non-contemporaneous fashion.

(18) In the system, an assembly section 210 produces units 120.sub.1, 120.sub.2, . . . which are realizations of a predetermined electric circuit design. The electric circuit design may be encoded in a memory as a hardware description, a circuit layout or the like, and may optionally be supplemented by instructions concerning raw materials to be used. The units 120.sub.1, 120.sub.2, . . . leave the assembly section in an uncalibrated condition, and drift compensation of the units while still in this condition is only possible on the basis of direct measurements. The system 200 further comprises a calibration section 220, a device programmer 230, a memory 240 storing a design-specific model and an optional testing section 250.

(19) In the calibration section 220, an environment sensor 221 measures a value of one or more environment parameters, on which the design-specific model depends. For purposes of illustration, the environment parameters have been denoted by T and V on the drawing, and the environment sensor 221 has been exemplified by a thermometer symbol; it is recalled that the invention is by no means limited to models dependent on two environment parameters nor environment parameters from which one is temperature. The calibration section 220 may further comprise means (not shown) for actively bringing about desired environment conditions, such as a power source for applying a selected supply voltage. When the measured or applied environment conditions are stable within an applicable accuracy, the analyzer 222 applies a test input signal x(t) to the unit currently present (on the drawing: unit 120.sub.5) and records an output signal y(t) in order to produce a frequency response in a relevant frequency interval [?.sub.a, ?.sub.b]. Data representing the frequency response thus produced are then supplied from the analyzer 222 to the device programmer 230.

(20) The device programmer 230 is configured to retrieve the design-specific model (or relevant portions thereof) from the memory 240 and fit the design-specific model to the frequency response of the unit 120.sub.5 under consideration, so that a unit-specific model is obtained. The device programmer 230 is further configured to store data representing the unit-specific model of a given unit 120.sub.m in a memory 130.sub.m associated with the unit. As noted above, the memory 130.sub.m may be internal or external to the unit 120.sub.m, or may be part of a networked library, from which it may be accessed by one or more compensation stages (not shown in FIG. 2).

(21) In the optional testing section 250 of the manufacturing system 200, there is provided a testing environment sensor 251 arranged in proximity of a testing analyzer 252 together with optional means (not shown) for actively applying a relevant environment condition to a unit under testing. The measurement results, including frequency responses in a relevant interval, are analyzed by a processor 253, which defines the design-specific model based on the results and forwards data representing the model for storage in the memory 240. Under normal cost pressure, it is contemplated that measurements in the testing section 250 are only to be performed on units belonging to a test lot of realizations of the electric circuit design. Units in the main lot are only to be measured in the calibration section 220.

(22) As to products of the manufacturing system 200, FIG. 3 shows a serially produced unit 120.sub.m with an integrated memory 121.sub.m for storing data representing a unit-specific model. The integrated memory 121.sub.m, which is preferably of a non-volatile type that does not require sustained powering to maintain stored data, has been made accessible from a compensation stage (not shown) which can be arranged in conjunction with the unit 120.sub.m and is responsible for compensating drift. For instance, a wireless or wired connection may be established between the integrated memory 121.sub.m and the compensation stage.

(23) As an alternative to the above approach of arranging an integrated memory containing the unit-specific model, FIG. 4 shows a serially produced signal processing device 400 arranged to receive an input signal x(t) and to supply, as its final output, a compensated output signal z(t) that is produced by a summer 432 as a sum of, on the one hand, a raw output signal y(t) from a unit 420, which is a realization of an electric circuit design, and on the other hand, a compensation signal prepared by a compensation processor 430. The compensation processor 430 may be configured to derive the compensation signal on the basis of the unit-specific model retrieved from a first memory 421 and evaluated for a current operating frequency and a present value of an environment parameter, and further on the basis of a reference frequency response Q.sub.ref of the unit, retrieved from a second memory 422, with which the compensation processor 430 compares the predicted frequency response. In the example illustrated in FIG. 4, the current operating frequency is derived from the raw output signal y(t). For an approximately time-invariant electric circuit design, an equivalent result will be obtained if the operating frequency is derived from the input signal x(t). The present value of the environment parameter, on which the unit-specific model depends, is measured by a sensor 431 arranged in proximity of the unit 420.

(24) As has been indicated by a dashed frame on the drawing, the sensor 431, summer 432 and compensation processor 430 may be regarded as a compensation stage 410 being a cooperating assembly comprising these devices. Such compensation stage 410 receives the raw output signal y(t) and produces the compensated output signal z(t). The sensor is included in the compensation stage 410 as an integral part. The compensation stage 410 may be said to process the raw input signal y(t) into a less drift-affected signal, rather than adding a compensation term that cancels (part of) the drift-induced deviation from the reference frequency response.

(25) An industrially useful application of the circuits shown in FIGS. 3 and 4 is ADCs. Cancellation of drift as such is the primary purpose of the compensation arrangements shown or enabled in these circuits. The inventors however envision that a compensation processor or compensation stage of the type exemplified in FIG. 4 can be given further responsibilities, such as the cancellation or reduction of nonlinearity errors.

(26) Turning now to presently contemplated applications where a realization of an electric circuit design is operated in conjunction with further realizations, FIG. 5 shows a detail of an in-phase/quadrature demodulator 500. Such a device has been described in greater detail in the applicants earlier disclosure WO10105694A1. The I/Q demodulator 500, which may be arranged in a quadrature receiver, comprises an upper branch acting as in-phase (I) signal path and a lower path acting as quadrature (Q) signal path. The I signal path comprises a first mixer 514a, and the Q signal path comprises a second mixer 514b. Both mixers 514a and 514b are adapted to process a preamplified radio-frequency (RF) signal on an input port 510. The preamplified RF signal is produced on the basis of a received RF signal supplied at point 506, to which a suitable gain is applied. The gain may be applied either by a common pre-amplifier 508 or by preamplifiers 516a and 516b (shown as variable-gain amplifiers) arranged downstream of the respective mixers 514a and 514b in each branch of the I/Q demodulator. Preferably, the gain is signal-adaptive and may change so as to respond to variations in the received RF signal, in particular variations due to changing reception conditions to achieve a desired swing of the signal at the input port 510.

(27) Furthermore, the I/Q demodulator 500 comprises a local oscillator (LO) unit 517, which is adapted to generate LO signals to the mixers 514a and 514b. The LO signals supplied to the mixers 514a and 514b are provided in quadrature, i.e., ideally, there is a 90-degree mutual phase shift between the LO signals. The mixers 514a and 514b are arranged to perform frequency down-conversion of a signal frequency band of interest of the RF signal to a lower frequency range. According to the embodiment illustrated in FIG. 5, the I/Q demodulator 500 further comprises a first filter 520a and a second filter 520b in the I and Q signal paths respectively, shown downstream of the variable-gain preamplifiers 516a and 516b in FIG. 5. The filters 520a and 520b are arranged to suppress undesired frequency components output from the mixers 514a and 514b and possibly amplified by preamplifiers 516a and 516b. In FIG. 5, the filters 520a and 520b are illustrated as low-pass filters. However, in other embodiments, where the I/Q demodulator may be of a different type (e.g., not necessarily adapted for use in a direct conversion receiver), the filters 520a and 520b may instead be band-pass filters. Moreover, in the embodiment illustrated in FIG. 5, the I/Q demodulator 500 comprises a first ADC 525a and a second ADC 525b in the I and Q signal paths, respectively. The first ADC 525a is adapted to convert the output signal from the filter 520a into a digital representation for generating a real-valued uncompensated digital I component. Similarly, the second ADC 525b is adapted to convert the output signal from the filter 520b into a digital representation for generating a real-valued uncompensated digital Q component. These real-valued signals may together be regarded as an uncompensated complex digital signal.

(28) As explained in WO10105694A1, poor channel balancing, i.e., a condition where the transfer functions of the I and Q signal paths are not approximately equal, limits the achievable image attenuation, which is otherwise a desirable property of an I/Q demodulator. Such imbalance is normally due to temperature variations, manufacturing inaccuracies, and other non-idealities of the physical components in the I and Q signal paths.

(29) To compensate the problems with insufficient image attenuation, the I/Q demodulator 500 further comprises a compensation stage 530, which is adapted to compensate imbalance between the I and Q signal paths. The compensation stage 530 is adapted to receive the uncompensated digital signal from a point 532a, 532 downstream of the ADCs 525a, 525b and to reduce said imbalance. In alternative embodiments, one or more intervening components (not shown) for generating signals based on the output signals from the ADCs 525a and 525b may be connected immediately downstream of these components. Nonlimiting examples of such intervening components may e.g. be filters or components for performing sample-rate conversion, such as interpolation or decimation.

(30) In an example implementation of the setup shown in FIG. 5, the compensation stage 530 compensates outputs of both the first ADC 525a and the second ADC 525b, on the basis of unit-specific models, which are retrieved from memory 521 and take into account at least a present gain state (or gain setting). The present gain state may be a setting of the common preamplifier 508 (illustrated in FIG. 5 by a dashed connection line) or of each of the preamplifiers 516a, 516b arranged in each branch or both of these. (For illustration purposes, it has been suggested in FIG. 5 that the unit-specific models also include the influence of an external environment parameter, which is measured using a sensor 531.) The first ADC 525a is compensated towards a reference frequency response Q.sub.ref,1=Q.sub.ref,1(?) that is independent of the gain state but may otherwise be close to the uncompensated frequency response (in the working range) of the first ADC 525a. The second ADC 525b is compensated towards an identical or approximately identical frequency response as the first ADC 525a, that is, Q.sub.ref,2=Q.sub.ref,1. Configured this way, the compensation stage 530 helps ensure that the I/Q demodulator stays balanced throughout the working range, in particular for different gain states of the pre-amplifier 508 and/or the preamplifiers 516a, 516b.

(31) In a further example implementation, the compensation stage 530 is replaced by two channel-wise compensation stages arranged in the respective branches and operating independently. With regard to the language of the appended claims, the combination of two channel-wise compensation stages functionally constitutes an I/Q mismatch compensator. The two channel-wise compensation stages may have been programmed to apply identical reference frequency responses, so that both channels are compensated towards a common reference point and channel mismatch is reduced or limited. This may lead to a relatively simpler implementation but may in general be associated with more bandwidth-limited performance than the option shown in FIG. 5.

(32) It is believed to be within the abilities of those skilled on the art to adapt, using common general knowledge and/or routine experimentation, the compensation stage described above with reference to FIG. 5 for use in an I/Q modulator.

(33) In FIG. 8, there is illustrated a demodulator. The demodulator differs from the I/Q modulator according to FIG. 5 in that it operates on a single channel or on multiple channels to which a common LO signal is applied. Put differently, the demodulator illustrated in FIG. 8 provides a real-valued scalar or real-valued vector as output. The demodulator may be arranged in an RF receiver or may be associated with an RF receiver.

(34) The demodulator comprises components adapted to process an input signal, preferably an RF signal, supplied to the demodulator at point 806 and to provide a digital signal at point 834 as outcome of the processing. As shown in FIG. 8, the demodulator comprises a first preamplifier 808, a filter 812, a mixer 814, a local oscillator (LO) 817 connected to the mixer 814, a second preamplifier 816, an ADC 825 and a compensation stage 830 at the far downstream end. The components function analogously to their counterparts in FIG. 5. In particular, the filter 812 may be a low-pass filter. With this setup, the signal reaching the input side of the ADC 825 has undergone at least one of the operations mixing, filtration, amplification in the first preamplifier 808 and amplification in the second preamplifier 816. In an embodiment, at least one of the preamplifiers has variable gain and its gain state (or gain setting) is fed to the compensation stage 830 as an environment parameter. As such, the action of the compensation stage 830 at a given point in time may be influenced by the current gain state of the first preamplifier 808 or the current gain state of the second preamplifier 816 or both. More precisely, the compensation stage 830 compensates drift with respect to a (predefined) reference frequency response by predicting the actual behaviour of the ADC 825 in accordance with the unit-specific model evaluated at this value of the current gain state.

(35) FIG. 6 shows a time-interleaved ADC 600, comprising a number N?2 of parallel subconverters 620.sub.1, 620.sub.2, . . . , each being arranged in a signal path extending from an input port 601 to an output port 602 of the time-interleaved ADC 600. The respective, potentially diverging channel frequency responses along the signal path from the input port 601 up to each subconverter 620.sub.m has been schematically indicated by a respective transfer function 610.sub.m. Downstream of the N subconverters 620.sub.1, 620.sub.2, . . . , there is arranged a common compensating stage 630, receiving N inputs and generating N outputs. Downstream of the compensating stage 630, a selector 640 is arranged, which has been schematically drawn as a switch, configured to connect one at a time of the N outputs of the compensating stage 630 to the output port 602 of the time-interleaved ADC 600.

(36) The compensating stage 630 retrieves data representing unit-specific models of the subconverters 620.sub.1, 620.sub.2, . . . and further includes a sensor 631 for sensing a present value of one or more environment parameters on which the unit-specific models depend. The sensor 631 may comprise subsensors associated with each of the subconverters 620.sub.1, 620.sub.2, . . . , so that a local value of the environment parameter(s) can be measured with high accuracy. The compensating stage 630 is capable of compensating drift in the output signal of each of the subconverters 620.sub.1, 620.sub.2, . . . , so that the output signal approaches a reference frequency response Q.sub.ref,m that has been set for a corresponding subconverter 620.sub.m. The designer of the time-interleaved ADC 600 is free to select reference frequency responses that further equalize the subconverters 620.sub.1, 620.sub.2, . . . to one another, and throughout a relevant frequency range; this is discussed below with reference to FIG. 7. The compensation stage 630 may further be responsible for compensating undesired divergences among the channel frequency responses; this problem has been discussed previously in the applicants application EP2158680A1.

(37) In a variation of the structure shown in FIG. 6, the compensation stage 630 may be located downstream of the selector 640.

(38) FIG. 7A shows a detail of a time-interleaved ADC with four parallel subconverters 720.sub.1, 720.sub.2, 720.sub.3, 720.sub.4. In addition to compensating drift in each of the subconverters 720.sub.1, 720.sub.2, 720.sub.3, 720.sub.4, it is desired to limit the mutual drift among the subconverters 720.sub.1, 720.sub.2, 720.sub.3, 720.sub.4. For this purpose, three compensation stages 730.sub.12, 730.sub.23, 730.sub.34 are included. Each of these is connected to a respective environment sensor 731.sub.21, 731.sub.23, 731.sub.34 and to a memory 721.sub.21, 721.sub.23, 721.sub.34 storing data that represents unit-specific models of the subconverters 720.sub.1, 720.sub.2, 720.sub.3, 720.sub.4. Downstream of the compensators 730.sub.12, 730.sub.23, 730.sub.34, there may be provided a selector similar to the selector 640 shown in FIG. 6.

(39) FIG. 7B illustrates a functionally equivalent alternative to the layout according to FIG. 7A. Three compensation stages 730.sub.12, 730.sub.32, 730.sub.42 are included, but unlike the cascade-like layout of FIG. 7A, all three use the frequency response of the second subconverter 720.sub.2 as a reference frequency response. This difference, which implies that the output of the second subconverter 720 is passed through three successive compensation stages, may translate into a reduction in error propagation among the four compensated signals.

(40) FIG. 7C illustrates a functionally equivalent alternative to the layout according to FIG. 7A. Here, a single compensation stage 730.sub.1234 is common to all four subconverters 720.sub.1, 720.sub.2, 720.sub.3, 720.sub.4. Because the single compensation stage 730.sub.1234 has contemporaneous access to signals from all four subconverters, superior performance can be expected. This also makes it possible to carry out sophisticated, possibly signal-adaptive, joint compensation schemes.

(41) Finally, FIG. 7D illustrates a hybrid approach, in which a first pre-compensation stage 730.sub.13 is responsible for reducing mutual drift between the output signals of the first 720.sub.1 and third 720.sub.3 subconverters, and a second pre-compensation stage 730.sub.24 is responsible for reducing mutual drift between the output signals of the second 720.sub.2 and fourth 720.sub.4 subconverters. Downstream of the pre-compensation stages, a common compensation stage 730.sub.1234 applies final compensation to further reduce mutual drift within each mentioned pair of signals and, additionally, between the two pairs. Due to a stabilizing action that may be expected from the pre-compensation stages 730.sub.13 and 730.sub.24, the common compensation stage 730.sub.1234 has a more manageable compensation task to fulfil and is likely to be successful in this under a wider range of operating conditions.

CLOSING REMARKS

(42) Even though the present disclosure describes and depicts specific example embodiments, the invention is not restricted to these specific examples. Modifications and variations to the above example embodiments can be made without departing from the scope of the invention, which is defined by the accompanying claims only.

(43) In the claims, the word comprising does not exclude other elements or steps, and the indefinite article a or an does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs appearing in the claims are not to be understood as limiting their scope.

(44) The devices and methods disclosed above may be implemented as software, firmware, hardware or a combination thereof. In a hardware implementation, the division of tasks between functional units referred to in the above description does not necessarily correspond to the division into physical units; to the contrary, one physical component may have multiple functionalities, and one task may be carried out in a distributed fashion, by several physical components in cooperation. Certain components or all components may be implemented as software executed by a digital processor, signal processor or microprocessor, or be implemented as hardware or as an application-specific integrated circuit. Such software may be distributed on computer readable media, which may comprise computer storage media (or nontransitory media) and communication media (or transitory media). As is well known to a person skilled in the art, the term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, it is well known to the skilled person that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.