ULTRA-WIDEBAND ATTENUATOR WITH LOW PHASE VARIATION AND IMPROVED STABILITY WITH RESPECT TO TEMPERATURE VARIATIONS

Abstract

A method for improving the stability and reducing phase variations of an ultra-wideband attenuator, with respect to temperature variations, comprising the steps of providing an attenuator implemented in π-topology and consisting of a serial path between the input and the output of the attenuator, including a first serial resistor Rs.sub.1 connected to the input, followed by a serial inductor Ls, followed by a second serial resistor Rs.sub.2 connected to the output; a first transistor T.sub.1 bridging between the input and the output, for controlling the impedance of the serial path by a first control input provided to the first transistor T.sub.1; a first parallel path between the input and ground, including a first parallel transistor T.sub.2a followed by first parallel resistor Rp.sub.1; a second parallel path between the output and ground, including a second parallel transistor T.sub.2b followed by second parallel resistor Rp.sub.2; a second control input commonly provided to first parallel transistor T.sub.2a and to the second parallel transistor T.sub.2b, for controlling the impedance of the first and second parallel paths; unifying the serial resistors to a common serial resistor Rs and splitting the serial inductor Ls to two serial inductors Ls.sub.1 and Ls.sub.2, such that one serial inductor is connected between the input and a first contract of the common serial resistor Rs and the other serial inductor is connected between the output and the other contact of the common serial resistor Rs; splitting the parallel resistor Rp.sub.1 to two smaller resistors, connecting a first smaller resistor to the input, connecting a second smaller resistor to the first smaller resistor via the first parallel transistor T.sub.2a and to ground via a third parallel transistor T.sub.3a; splitting the parallel resistor Rp.sub.2 to two smaller resistors, connecting a third smaller resistor to the output, connecting a fourth smaller resistor to the third smaller resistor via the second parallel transistor T.sub.2b and to ground via a fourth parallel transistor T.sub.3b; connecting a first feedback capacitor Cfb.sub.1 between the common point connecting between the ungrounded port of the second parallel transistor T.sub.3a and the first contract of the common serial resistor Rs and connecting a second feedback capacitor Cfb.sub.2 between the common point connecting between the ungrounded port of the fourth parallel transistor T.sub.3b and the second contract of the common serial resistor Rs; upon controlling the first and second parallel transistors T.sub.2a and T.sub.2b by the second control input, simultaneously controlling also the third and the fourth parallel transistors T.sub.3a and T.sub.3b by the second control input; controlling the first and the second control inputs to obtain a desired attenuation between the input and output of the attenuator.

Claims

1. A method for improving the stability and reducing phase variations of an ultra-wideband attenuator, with respect to temperature variations, comprising: a) providing an attenuator implemented in π-topology and consisting of: a.1) a serial path between the input and the output of said attenuator, including a first serial resistor Rs.sub.1 connected to said input, followed by a serial inductor Ls, followed by a second serial resistor Rs.sub.2 connected to said output; a.2) a first transistor T.sub.1 bridging between said input and said output, for controlling the impedance of said serial path by a first control input provided to said first transistor T.sub.1; a.3) a first parallel path between said input and ground, including a first parallel transistor T.sub.2a followed by first parallel resistor Rp.sub.1; a.4) a second parallel path between said output and ground, including a second parallel transistor T.sub.2b followed by second parallel resistor Rp.sub.2; a.5) a second control input commonly provided to first parallel transistor T.sub.2a and to said second parallel transistor T.sub.2b, for controlling the impedance of said first and second parallel paths; b) rearranging the components in said serial path by unifying said serial resistors to a common serial resistor Rs and splitting said serial inductor Ls to two serial inductors Ls.sub.1 and Ls.sub.2, such that one serial inductor is connected between said input and a first contract of said common serial resistor Rs and the other serial inductor is connected between said output and the other contact of said common serial resistor Rs; c) modifying the components in said first parallel path by splitting the parallel resistor Rp.sub.1 to two smaller resistors, connecting a first smaller resistor to the input, connecting a second smaller resistor to said to first smaller resistor via said first parallel transistor T.sub.2a and to ground via a third parallel transistor T.sub.3a; d) modifying the components in said second parallel path by splitting the parallel resistor Rp.sub.2 to two smaller resistors, connecting a third smaller resistor to the output, connecting a fourth smaller resistor to said to third smaller resistor via said second parallel transistor T.sub.2b and to ground via a fourth parallel transistor T.sub.3b; e) connecting a first feedback capacitor Cfb.sub.1 between the common point connecting between the ungrounded port of said second parallel transistor T.sub.3a and the first contract of said common serial resistor Rs and connecting a second feedback capacitor Cfb.sub.2 between the common point connecting between the ungrounded port of said fourth parallel transistor T.sub.3b and the second contract of said common serial resistor Rs; f) upon controlling said first and second parallel transistors T.sub.2a and T.sub.2b by said second control input, simultaneously controlling also said third and said fourth parallel transistors T.sub.3a and T.sub.3b by said second control input; and g) controlling said first and said second control inputs to obtain a desired attenuation between said input and output of said attenuator.

2. A method according to claim 1, wherein the transistors are implemented using MOSFET technology.

3. A method according to claim 1, wherein the attenuator is implemented using differential or single-ended topology.

4. A method according to claim 1, wherein the circuitry for implementing said attenuator is symmetrical, such that: Rs.sub.1=Rs.sub.2; Rp.sub.1=Rp.sub.2; first smaller resistor=third smaller resistor; second smaller resistor=fourth smaller resistor.

5. A method according to claim 1, wherein optimal performance is obtained when the resistors are split to two equal smaller resistors.

6. A method according to claim 1, wherein the phase imbalance is corrected while the attenuation value decreases.

7. A method according to claim 1, wherein essentially constant attenuation is obtained from DC-26 GHz.

8. An ultra-wideband attenuator with improved stability and reduced phase variations, with respect to temperature variations, comprising: a) an attenuator implemented in π-topology consisting of: a.1) a serial path between the input and the output of said attenuator, including a first serial resistor Rs.sub.1 connected to said input, followed by a serial inductor Ls, followed by a second serial resistor Rs.sub.2 connected to said output; a.2) a first transistor T.sub.1 bridging between said input and said output, for controlling the impedance of said serial path by a first control input provided to said first transistor T.sub.1; a.3) a first parallel path between said input and ground, including a first parallel transistor T.sub.2a followed by first parallel resistor Rp.sub.1; a.4) a second parallel path between said output and ground, including a second parallel transistor T.sub.2b followed by second parallel resistor Rp.sub.2; a.5) a second control input commonly provided to first parallel transistor T.sub.2a and to said second parallel transistor T.sub.2b, for controlling the impedance of said first and second parallel paths; b) a common serial resistor Rs in said serial path being unification of said serial resistors and two serial inductors Ls.sub.1 and Ls.sub.2, being a division of said serial inductor Ls, such that one serial inductor is connected between said input and a first contract of said common serial resistor Rs and the other serial inductor is connected between said output and the other contact of said common serial resistor Rs; c) a first resistor being smaller than Rp.sub.1 connected to the input and a second smaller resistor being smaller than Rp.sub.1 connected to said to first smaller resistor via said first parallel transistor T.sub.2a and to ground via a third parallel transistor T.sub.3a; d) a third resistor being smaller than Rp.sub.2 connected to the input and a second smaller resistor being smaller than Rp.sub.2 connected to said to first smaller resistor via said first parallel transistor T.sub.2b and to ground via a third parallel transistor T.sub.3b; e) a first feedback capacitor Cfb.sub.1 connected between the common point connecting between the ungrounded port of said second parallel transistor T.sub.3a and the first contract of said common serial resistor Rs and a second feedback capacitor Cfb.sub.2 connecting between the common point connecting between the ungrounded port of said fourth parallel transistor T.sub.3b and the second contract of said common serial resistor Rs; f) a controller adapted to control said first and second parallel transistors T.sub.2a and T.sub.2b by said second control input, to simultaneously control also said third and said fourth parallel transistors T.sub.3a and T.sub.3b by said second control input, and to control said first and said second control inputs to obtain a desired attenuation between said input and output of said attenuator.

9. An ultra-wideband attenuator according to claim 8, in which the transistors are implemented using MOSFET technology.

10. An ultra-wideband attenuator according to claim 8, implemented using differential or single-ended topology.

11. An ultra-wideband attenuator according to claim 8, in which the circuitry for implementing said attenuator is symmetrical, such that: Rs.sub.1=Rs.sub.2; Rp.sub.1=Rp.sub.2; first smaller resistor=third smaller resistor; second smaller resistor=fourth smaller resistor.

12. An ultra-wideband attenuator according to claim 8, in which optimal performance is obtained when the resistors are split into two equal smaller resistors.

13. An ultra-wideband attenuator according to claim 8, in which the phase imbalance is corrected while the attenuation value decreases.

14. An ultra-wideband attenuator according to claim 8, in which essentially constant attenuation is obtained from DC-26 GHz.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The above and other characteristics and advantages of the invention will be better understood through the following illustrative and non-limitative detailed description of preferred embodiments thereof, with reference to the appended drawings, wherein:

[0060] FIG. 1 shows an example of the error introduced when changing an arbitrary phase and amplitude in a phased array channel:

[0061] FIG. 2 illustrates the basic architecture of a Digitally-Controlled-Attenuator (DCA):

[0062] FIGS. 3A and 3B (prior art) illustrate improved T- and π-networks-based attenuators, respectively, with low phase variation for different attenuations over large frequency range reported;

[0063] FIG. 4 schematically shows a trade-off that exists between the phase variation and the attenuation value over frequency, both limiting the maximum frequency and bandwidth of the attenuator;

[0064] FIGS. 5a and 5b show analysis results of the correction capacitor in the T-topology of FIG. 3 regarding attenuation and phase imbalance, respectively, using only lumped elements and transistors from a CMOS 180 nm technology;

[0065] FIGS. 6a and 6b show analysis results of the correction inductor “Ls” in the π-topology (of FIG. 3) regarding attenuation and phase imbalance, respectively, using only lumped elements and transistors from a CMOS 180 nm technology

[0066] FIG. 7 illustrates an implementation topology of an attenuation bit, according to an embodiment of the invention;

[0067] FIGS. 8a and 8b show analysis results of the distribution values of the parallel resistors Rp between Rp1 and Rp2;

[0068] FIGS. 9a and 9b show analysis results of the effect of the feedback capacitance Cfb;

[0069] FIGS. 10a and 10b show analysis results of phase variation and attenuation value optimization over frequency for different combinations of Cfb and Ls;

[0070] FIGS. 11a and 11b show analysis results of phase variation and attenuation value optimization over frequency for different attenuator topologies:

[0071] FIGS. 12a and 12b present a comparison between simulation results and measurement results for an 8 dB attenuation bit, that has been realized based on the proposed topology;

[0072] FIGS. 13a and 13b illustrate 24 dB attenuation states and relative attenuation states over frequency, respectively;

[0073] FIGS. 14a and 14b illustrate the input and output Return Loss of the attenuator, respectively, at all different attenuation states;

[0074] FIGS. 15a and 15b illustrate measurement results of RMS amplitude error, phase variation and RMS phase variation over frequency, respectively, for the 24 dB attenuator; and

[0075] FIGS. 16a and 16b illustrate measurement results of the 24 dB attenuator phase variation over temperature and amplitude error over frequency, both at all attenuation states.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0076] The present invention proposes a technique for improving the phased-array system accuracy by reducing this amplitude and phase calibration process of large phased-array systems by using an attenuator with very low phase variation and improved stability, with respect to temperature variations over ultra-wideband frequencies, with excellent matching. The proposed technique proposes a method and circuit for further improving the basic π-topology, in order to break the trade-off shown in FIG. 4.

[0077] In one embodiment, a basic π-topology attenuator was chosen over a basic T-topology attenuator.

[0078] FIG. 7 illustrates an implementation topology of an attenuation bit, according to an embodiment of the invention. This new topology improves the phase variation over temperature, attenuation error over frequency and linearity, as will be explained later on.

[0079] In general, a single resistor Rp is used in the branch or parallel path to correct the attenuation value. It was surprisingly found that the distribution of this resistor to Rp1 and Rp2 improves the phase variation of the attenuator and reduces the attenuation error over frequency.

[0080] FIGS. 8a and 8b show analysis results of the distribution values of the parallel resistors Rp between Rp1 and Rp2. FIG. 8a shows changes in the attenuation value over frequency for different distribution values of Rp1 and Rp2 in the range of o<Rp1, Rp2<Rp. FIG. 8b shows changes in the phase error (phase imbalance) over frequency for different distribution values of Rp1 and Rp2 in the range of o<Rp1, Rp2<Rp. As shown, there exists an optimum distribution between Rp1 and Rp2.

[0081] In addition, compared to a basic π-topology, another transistor Trp2 was added in each branch path, for improving the linearity of the attenuator, as shown in FIG. 7. This second transistor (Trp2) plays as well another core function: at OFF-state, it introduces capacitance with a high impedance to the ground. Enhanced by the OFF-state capacitance of second branch transistors (Trp2), a feedback path has been introduced from the branch (or parallel) path to the bridge (or serial) path by a capacitor Cfb (shown in FIG. 7), thereby correcting the phase variation while decreasing the attenuation value.

[0082] It is important to state that the feedback found would still work without Trp2 if Trp1 and Rp1 would be switched, however, it would work with diminished effect and would lose the advantage of the resistors Rp1/Rp2 distribution resulting in overall smaller bandwidth and maximum operating frequency.

[0083] FIGS. 9a and 9b show analysis results of the effect of the feedback capacitance Cfb. FIG. 9a shows changes in the attenuation value over frequency for different values of Cfb. FIG. 9b shows changes in the phase error (phase imbalance) over frequency for different values of Cfb.

[0084] As can be seen, the phase imbalance is corrected while the attenuation value decreases. Using the combination of 2 correcting elements with opposite behavior (i.e., varying the attenuation value and phase imbalance in opposite directions) on the attenuation value, while both correcting the phase will lead to the possibility of designing an attenuator with very low phase variation and still acceptable attenuator error value over ultra-wideband frequencies.

[0085] FIGS. 10a and 10b show analysis results of phase variation and attenuation value optimization over frequency for different combinations of Cfb and Ls. FIG. 10a shows changes in the attenuation value over frequency for different combinations of Cfb and Ls. FIG. 10b shows changes in the phase error (phase imbalance) over frequency for different combinations of Cfb and Ls.

[0086] FIGS. 11a and 11b show analysis results of phase variation and attenuation value optimization over frequency for different attenuator topologies. FIG. 11a shows changes in the attenuation value over frequency for three different topologies. T-topology with one transistor T.sub.2 and compensation by capacitor Cp (FIG. 3a); π-topology with one transistor T.sub.2 in each parallel path and compensation by inductor Ls (FIG. 3b); The new topology with two transistors Trp.sub.1 Trp.sub.2 and compensation by two resistors Rp1, Rp2 in each parallel path and an optimal combination of Ls and feedback capacitors Cfb (FIG. 7). FIG. 11b shows changes in the phase error (phase imbalance) over frequency for the same three different topologies. As can be seen, attenuation value and phase imbalance over frequency are highly improved. The linearity is improved as well, compared to the other topologies thanks to the existence of the second branch transistor (Trp2).

[0087] FIGS. 12a and 12b present a comparison between simulation results and measurement results for an 8 dB attenuation bit, that has been realized based on the proposed topology. FIG. 12a shows changes in the attenuation value over frequency. FIG. 12b shows changes in the phase error (phase imbalance) over frequency. The difference between the results is due to the absence of the deep n-well model in the used transistors (CMOS 180 nm).

[0088] Using the presented topology and the architecture of FIG. 2, a 24 dB attenuator was realized (8 dB-1 dB-1 dB-4 dB-1 dB-1 dB-8 dB). The proposed topology has a very minor contribution to the overall loss of the attenuator which is mainly caused by the “bridge” or serial transistor performances depending on the technology node (180 nm CMOS in this example).

[0089] FIGS. 13a and 13b illustrate 24 dB attenuation states and relative attenuation states over frequency, respectively.

[0090] FIGS. 14a and 14b illustrate the input and output Return Loss of the attenuator, respectively, at all different attenuation states.

[0091] FIGS. 15a and 15b illustrate measurement results of RMS amplitude error, phase variation and RMS phase variation over frequency, respectively, for the 24 dB attenuator.

[0092] FIGS. 16a and 16b illustrate measurement results of the 24 dB attenuator phase variation over temperature and amplitude error over frequency, both at all attenuation states.

[0093] FIG. 13-16 presents the measurement results of the 24 dB attenuator, which has been implemented according to the new topology proposed by the present invention. As can be seen, attenuation values can be kept almost constant from DC-26 GHz. The attenuator has an RMS amplitude error below 0.5 dB with an LSB of only 1 dB. It presents a maximum ±4° phase variation from DC-26 GHz. In addition, the phase variation varies by only ±1° between −35° C. and +100° C. Using the resistor distribution leads to excellent return loss as shown in FIG. 13a-13b, which is an important parameter in accurate phased-array applications. The designed attenuator has an attenuation error from DC-26 GHz, thereby meeting a requirement of ±LSB/2±5%.

[0094] It should be mentioned that the proposed topology works for all MOSFET technologies (such as CMOS, SiGe, GaAs, GaN, InP, etc . . . ) and is compatible with as single-ended or differential design.

[0095] The above examples and description have of course been provided only for the purpose of illustrations, and are not intended to limit the invention in any way. As will be appreciated by the skilled person, the invention can be carried out in a great variety of ways, employing more than one technique from those described above, including the internet, a cellular network or any other wireless data network, all without exceeding the scope of the invention.

1. REFERENCES

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