Transmipedance amplifier circuit, related integrated circuit, receiver circuit and method of operating a transimpedance amplifier circuit

Abstract

A transimpedance amplifier circuit includes a feedback control loop that generates a compensation current at an input of a transimpedance amplifier. The feedback control loop includes a differential integrator with an integration capacitor. A time constant associated with charging the integration capacitor is variable as a function of a pre-charge control signal. During a pre-charge phase, the pre-charge control signal is set to a first value so as to set the time constant associated with charging the integration capacitor to a first time constant value. During an operation phase, the pre-charge control signal is set to a second value so as to increase the time constant associated with charging the integration capacitor to a second time constant value greater than the first time constant value for the pre-charge phase.

Claims

1. A transimpedance amplifier circuit, comprising: an input terminal for receiving an input current and an output terminal for providing an output voltage; a transimpedance amplifier comprising an input connected to said input terminal and configured to provide at an output said output voltage, whereby said output voltage is indicative of an input current received at the input of said transimpedance amplifier; a feedback control loop configured to generate a compensation current at the input of said transimpedance amplifier in order reduce or cancel a DC/low frequency part of said input current, wherein said feedback control loop comprises: a) a differential integrator generating a feedback signal by comparing said output voltage with a reference voltage; and b) a current generator configured to generate said compensation current as a function of said feedback signal; wherein said differential integrator comprises an integrating error amplifier comprising a first operational amplifier, wherein a first input of said first operational amplifier is connected via a first resistor to a reference voltage and a second input of said first operational amplifier is connected to the output voltage, and wherein at least one integration capacitor is connected between an output terminal of said first operational amplifier and said first input of said first operational amplifier; wherein a time constant associated with charging said at least one integration capacitor is variable as a function of a pre-charge control signal; and a processing circuit configured to generate said pre-charge control signal such that: during a pre-charge phase, said pre-charge control signal is set to a first value to set the time constant associated with charging said at least one integration capacitor to a first time constant value; and during an operation phase, said pre-charge control signal is set to a second value to increasing the time constant associated with charging said at least one integration capacitor to a second time constant value greater than the first time constant value for said pre-charge phase.

2. The transimpedance amplifier circuit according to claim 1, wherein said first resistor is a variable resistor having a resistance that is settable as a function of said pre-charge control signal.

3. The transimpedance amplifier circuit according to claim 1, wherein said differential integrator comprises a low-pass filter arranged at said second input of said first operational amplifier, wherein said low-pass filter comprises a second resistor and a second integration capacitor.

4. The transimpedance amplifier circuit according to claim 3, comprising an offset compensation capacitor connected with a first terminal to said second input of said first operational amplifier and with a second terminal to an electronic switch, said electronic switch being configured to connect said second terminal of said offset compensation capacitor either to said reference voltage or said second resistor as a function of an offset compensation signal, wherein said processing circuit is configured to generate said offset compensation signal to connect said offset compensation capacitor in parallel with said second resistor during an offset compensation phase following said pre-charge phase.

5. The transimpedance amplifier circuit according to claim 1, comprising a discharge circuit configured to selectively discharge said at least one integration capacitor as a function of a reset signal, wherein said processing circuit is configured to generate said reset signal in order to discharge said at least one integration capacitor during a reset phase preceding said pre-charge phase.

6. The transimpedance amplifier circuit according to claim 1, wherein said transimpedance amplifier has a variable gain that is set at least as a function of said pre-charge control signal.

7. The transimpedance amplifier circuit according to claim 1, wherein said transimpedance amplifier comprises a second operational amplifier, wherein a first input of said second operational amplifier is connected to said input terminal and a second input of said second operational amplifier is connected to the reference voltage, and wherein a third resistor is connected between an output terminal of said second operational amplifier and said first input of said second operational amplifier.

8. The transimpedance amplifier circuit according to claim 7, wherein said third resistor is a variable resistor having a resistance that is set as a function of said pre-charge control signal.

9. The transimpedance amplifier circuit according to claim 1, comprising a further control loop that is activated during a pre-compensation phase preceding said pre-charge phase, said further control loop comprising: a plurality of constant current sources selectively connectable to the input of said transimpedance amplifier; a comparator configured to generate a comparison signal indicating whether the output voltage is smaller than a threshold; and a control unit configured to selectively connect sub-sets of said constant current sources to the input of said transimpedance amplifier, thereby increasing current provided by said plurality of constant current sources, until said comparison signal indicates that the output voltage is smaller than said threshold.

10. The transimpedance amplifier circuit according to claim 1 implemented as an integrated circuit.

11. The transimpedance amplifier circuit according to claim 1, wherein the transimpedance amplifier circuit is a component of a receiver circuit.

12. A method of operating a transimpedance amplifier circuit including a transimpedance amplifier and a feedback control loop including a differential integrator with an integration capacitor coupled between an input and an output of the differential integrator, the method comprising: during a pre-charge phase, setting a pre-charge control signal to a first value so as to set a time constant associated with charging said integration capacitor to a first time constant value; during an operation phase, setting said pre-charge control signal to a second value so as to increase the time constant associated with charging said integration capacitor to a second time constant value greater than the first time constant value for said pre-charge phase, wherein the feedback control loop has a smaller settling time for reducing or cancelling a DC/low frequency part of an input current applied to the transimpedance amplifier during said pre-charge phase, and wherein the feedback control loop is maintained stable during said operation phase.

13. A circuit, comprising: a transimpedance amplifier having an input and an output; a feedback circuit having an input coupled to the output of the transimpedance amplifier and an output coupled to an input of the transimpedance amplifier, wherein said feedback circuit comprises: a low pass filter including a first capacitor coupled to a first variable resistor, the low pass filter having an input coupled to the input of the feedback circuit; and a differential integrator having a first input coupled to an output of the low pass filter, a second input coupled a second variable resistor, an output coupled to the output of the feedback circuit, and a second capacitor coupled between the output of the differential integrator and the second input of the differential integrator; and a control circuit configured to set first resistance values for the first and second variable resistors when the circuit is operating in a pre-charge phase and set second resistance values for the first and second variable resistors when the circuit is operating is an operating phase.

14. The circuit of claim 13, further comprising: a first discharge circuit configured to discharge the first capacitor; a second discharge circuit configured to discharge the second capacitor; and wherein the control circuit is further configured to actuate the first and second discharge circuits during a reset phase preceding the pre-charge phase.

15. The circuit of claim 13, further comprising: a third capacitor; a first switch circuit configured to selectively couple the third capacitor in parallel with the first variable resistor; a fourth capacitor; a second switch circuit configured to selectively couple the fourth capacitor in parallel with the second variable resistor; and wherein the control circuit is further configured to actuate the first and second switch circuits during an offset phase following the pre-charge phase.

16. The circuit of claim 15, wherein the first and second switch circuits, when not actuated, couple the third and fourth capacitors to a reference voltage.

17. The circuit of claim 13, wherein the transimpedance amplifier comprises a third variable resistor coupled between the input and the output of the transimpedance amplifier, and wherein the control circuit is further configured to set one resistance value for the third variable resistor when the circuit is operating in the pre-charge phase and set another resistance value for the third variable resistor when the circuit is not operating is the pre-charge phase.

18. A transimpedance amplifier circuit, comprising: an input terminal for receiving an input current and an output terminal for providing an output voltage; a transimpedance amplifier comprising an input connected to said input terminal and configured to provide at an output said output voltage, whereby said output voltage is indicative of an input current received at the input of said transimpedance amplifier; a feedback control loop configured to generate a compensation current at the input of said transimpedance amplifier in order reduce or cancel a DC/low frequency part of said input current, wherein said feedback control loop comprises: a) a differential integrator generating a feedback signal by comparing said output voltage with a reference voltage; and b) a current generator configured to generate said compensation current as a function of said feedback signal; wherein said differential integrator comprises at least one integration capacitor; wherein a time constant associated with charging said at least one integration capacitor is variable as a function of a pre-charge control signal; wherein said transimpedance amplifier has a variable gain that is set at least as a function of said pre-charge control signal; a processing circuit configured to generate said pre-charge control signal such that: during a pre-charge phase, said pre-charge control signal is set to a first value to set the time constant associated with charging said at least one integration capacitor to a first time constant value; and during an operation phase, said pre-charge control signal is set to a second value to increasing the time constant associated with charging said at least one integration capacitor to a second time constant value greater than the first time constant value for said pre-charge phase; wherein said transimpedance amplifier comprises a second operational amplifier, a first input of said second operational amplifier being connected to said input terminal and a second input of said second operational amplifier being connected to the reference voltage; and a third resistor connected between an output terminal of said second operational amplifier and said first input of said second operational amplifier.

19. The transimpedance amplifier circuit according to claim 18, wherein said third resistor is a variable resistor having a resistance that is set as a function of said pre-charge control signal.

20. A transimpedance amplifier circuit, comprising: an input terminal for receiving an input current and an output terminal for providing an output voltage; a transimpedance amplifier comprising an input connected to said input terminal and configured to provide at output said output voltage, whereby said output voltage is indicative of an input current received at the input of said transimpedance amplifier; a feedback control loop configured to generate a compensation current at the input of said transimpedance amplifier in order reduce or cancel a DC/low frequency part of said input current, wherein said feedback control loop comprises: a) a differential integrator generating a feedback signal by comparing said output voltage with a reference voltage; and b) a current generator configured to generate said compensation current as a function of said feedback signal; wherein said differential integrator comprises at least one integration capacitor; wherein a time constant associated with charging said at least one integration capacitor is variable as a function of a pre-charge control signal; wherein said transimpedance amplifier has a variable gain that is directly set as a function of said pre-charge control signal; and a processing circuit configured to generate said pre-charge control signal such that: during a pre-charge phase, said pre-charge control signal is set to a first value to set the time constant associated with charging said at least one integration capacitor to a first time constant value; and during an operation phase, said pre-charge control signal is set to a second value to increasing the time constant associated with charging said at least one integration capacitor to a second time constant value greater than the first time constant value for said pre-charge phase.

21. The transimpedance amplifier circuit according to claim 20, further comprising a further control loop that is activated during a pre-compensation phase preceding said pre-charge phase, said further control loop comprising: a plurality of constant current sources selectively connectable to the input of said transimpedance amplifier; a comparator configured to generate a comparison signal indicating whether the output voltage is smaller than a threshold; and a control unit configured to selectively connect sub-sets of said constant current sources to the input of said transimpedance amplifier, thereby increasing current provided by said plurality of constant current sources, until said comparison signal indicates that the output voltage is smaller than said threshold.

22. The transimpedance amplifier circuit according to claim 20, wherein said transimpedance amplifier comprises a second operational amplifier, wherein a first input of said second operational amplifier is connected to said input terminal and a second input of said second operational amplifier is connected to the reference voltage, and wherein a third resistor is connected between an output terminal of said second operational amplifier and said first input of said second operational amplifier.

23. The transimpedance amplifier circuit according to claim 22, wherein said third resistor is a variable resistor having a resistance that is set as a function of said pre-charge control signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the present disclosure will now be described with reference to the annexed drawings, which are provided purely by way of non-limiting example and in which:

(2) FIGS. 1, 2 and 3 show an optical system with details of a receiver circuit;

(3) FIG. 4 shows a first embodiment of a transimpedance amplifier circuit;

(4) FIG. 5 shows an embodiment of a receiver circuit comprising the transimpedance amplifier circuit of FIG. 4;

(5) FIG. 6 shows an exemplary waveform of the output signal of a transimpedance amplifier circuit;

(6) FIGS. 7, 8, 9 and 10 show embodiments of various circuits adapted to be used in the transimpedance amplifier circuit of FIG. 4;

(7) FIG. 11 shows waveforms of various control signals used by the circuits of FIGS. 7, 8, 9 and 10;

(8) FIG. 12 shows a second embodiment of a transimpedance amplifier circuit;

(9) FIG. 13 shows waveforms of various control signals used by the transimpedance amplifier circuit of FIG. 12; and

(10) FIG. 14 shows a third embodiment of a transimpedance amplifier circuit.

DETAILED DESCRIPTION

(11) In the following description, numerous specific details are given to provide a thorough understanding of embodiments. The embodiments can be practiced without one or several specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

(12) Reference throughout this specification to one embodiment or an embodiment means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases in one embodiment or in an embodiment in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

(13) The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

(14) In the following FIGS. 4 to 14, the parts, elements or components which have already been described with reference to FIGS. 1 to 3 are denoted by the same references previously used; the description of such previously described elements will not be repeated in the following in order not to overburden the present detailed description.

(15) As mentioned in the foregoing, various embodiments of the present disclosure relate to a transimpedance amplifier circuit with DC/low frequency input cancellation, to be used, e.g., as a transimpedance amplifier 32 in the optical systems shown in FIGS. 1 and 2. Generally, DC/low frequency input cancellation does not require that the DC/low frequency part of the input current has to be cancelled completely, but is at least reduced, thereby permitting a greater amplification of the variation of the input current.

(16) FIG. 4 shows a first embodiment of a transimpedance amplifier circuit 32a with DC offset cancellation.

(17) As mentioned in the foregoing, a transimpedance amplifier circuit 32a with DC offset cancellation may be implemented with a transimpedance amplifier 320a and a feedback loop generating a compensation current I.sub.DC.

(18) Specifically, in the embodiment considered, the transimpedance amplifier circuit 32a comprises an input IN for receiving an input current I.sub.IN and an output OUT for providing an output voltage V.sub.out.

(19) In the embodiment considered, the input current I.sub.IN may be provided by any current source 20 such as one or more photodiodes PD connected (e.g., directly) to the input IN of the amplifier circuit 32 (see e.g. FIG. 1). Moreover, as mentioned with respect to FIG. 2, a switching means 30 may be interposed between the current source and the input IN of the transimpedance amplifier circuit 32a. Generally, the switching means 30 may also be included in the package of the transimpedance amplifier circuit 32a.

(20) In the embodiment considered, the transimpedance amplifier 320 is thus configured to receive at input a current I.sub.TIA corresponding to the sum of the input current I.sub.IN and the compensation current I.sub.DC and generate an output voltage V.sub.out being indicative of the current I.sub.TIA.

(21) For example, in the embodiment considered, the transimpedance amplifier 320a is implemented with an operational amplifier OpAmp1.

(22) Specifically, in the embodiment considered, a closed loop configuration with negative feedback is used. For example, in various embodiments, the inverting/negative input of the operational amplifier OpAmp1 is connected (e.g. directly) to the input IN, and the non-inverting/positive input of the operational amplifier OpAmp1 is connected to a constant reference voltage V.sub.ref. Finally, the feedback network between the output terminal of the operational amplifier OpAmp1 and the inverting input of the operational amplifier OpAmp1 comprises at least a resistor R.sub.F and optionally a capacitor C.sub.F. For the operation of this circuit, reference can be made, for example, to United States Patent Application Publication No. 2014/0291487 (incorporated by reference), or to the description of a transimpedance amplifier provided at https://en.wikipedia.org/wiki/Transimpedance_amplifier (incorporated by reference). However, in general, also other types of transimpedance amplifiers may be used.

(23) In the embodiment considered, the output voltage V.sub.out will thus correspond to the voltage V.sub.ref when no current I.sub.TIA is provided at the input of the transimpedance amplifier 320a.

(24) In the embodiment considered, the output voltage V.sub.out is provided to a low pass filter 322a, such as a RC low-pass filter. For example, in the embodiment considered, the filter 322a comprises a resistor R.sub.1 and a capacitor C.sub.1 connected in series between the output OUT of the transimpedance amplifier circuit 320a, i.e. the output voltage V.sub.out, and a constant voltage, such as e.g. the reference voltage V.sub.ref.

(25) Accordingly, in the embodiment considered, the intermediate point between the resistor R.sub.1 and the capacitor C.sub.1, generally representing the output of the low-pass filter 324a, provides a filtered version of the output voltage V.sub.out, in which the high-frequency components have been removed. Generally, also other types of low-pass filters, including also active and/or multi-stage filters, may be used.

(26) In the embodiment considered, the output of the filter 322a is connected to an integrating error amplifier 324a, representing a regulator with integral (I) component. Specifically, the error amplifier 324a is configured to generate a feedback control signal FB and vary (i.e. increase or decrease) this control signal FB until the filtered version of the output voltage V.sub.out corresponds to the reference voltage V.sub.ref.

(27) For example, in the embodiment considered, the error amplifier 324a is implemented with a second operational amplifier OpAmp2, with a capacitor C.sub.2 in the feedback network.

(28) Specifically, in the embodiment considered, the filtered version of the output voltage V.sub.out, i.e. the output of the low-pass filter 322a, is connected to the non-inverting/positive input of the operational amplifier OpAmp2 and the reference voltage V.sub.ref is connected via a resistor R.sub.2 to the inverting/negative input of the operational amplifier OpAmp2. In the embodiment considered, the integrating component of the error amplifier is implemented with the capacitor C.sub.2 connected between the output of the operational amplifier OpAmp2 and the inverting/negative input of the operational amplifier OpAmp2.

(29) Accordingly, in the embodiment considered, the low-pass filter 322a together with the analog integrator 324a implement a differential integrator. For this reason, in various embodiments, the resistance of the resistor R.sub.2 corresponds to the resistance of the resistor R.sub.1 and the capacitance of the capacitor C.sub.2 corresponds to the capacitance of the capacitor C.sub.1.

(30) Accordingly, in the embodiment considered, the control signal FB at the output of the error amplifier 324a is a voltage signal.

(31) Finally, in order to generate the compensation current, the control signal FB is sent to a current generator 328a configured to convert the control signal FB provided by the error amplifier 324a in the compensation current I.sub.DC.

(32) For example, in the embodiment considered, the current source 328a may be implemented with a resistor R.sub.3 connected between the output of the error amplifier 324a, i.e. the output of the operational amplifier OpAmp2, and the input of the transimpedance amplifier 320a.

(33) Accordingly, in the embodiment considered, the error amplifier 324a will increase or decrease the control signal FB (and thus the amplitude of the compensation current I.sub.DC injected at the input of the transimpedance amplifier 320a and having opposed sign with respect to the input current I.sub.IN) until the filtered version of the output voltage V.sub.out corresponds to the reference voltage V.sub.ref.

(34) Specifically, in various embodiments considered, the output voltage V.sub.out corresponds to the reference voltage V.sub.ref when the current I.sub.TIA at the input of the transimpedance amplifier 320a is zero. For example, in the embodiment considered, this is ensured by means of the virtual ground of the operational amplifier OpAmp1, because the non-inverting input of the operational amplifier OpAmp1 is connected to the reference voltage V.sub.ref. However, in general, the error amplifier 324a and the transimpedance amplifier 320a may operate with different reference voltages.

(35) Thus, in the embodiment considered, in case a substantially constant current I.sub.IN is provided at the input IN of the amplifier circuit 32a, the error amplifier 324a will create (via the current source 328a, e.g. the resistor R.sub.3) an opposed compensation current I.sub.DC having the same amplitude, thereby cancelling the DC/low frequency part I.sub.IN,DC of the current I.sub.IN at the input IN, i.e.:
I.sub.DC=I.sub.IN,DC(2)

(36) As mentioned in the foregoing, the current I.sub.IN at the input of the transimpedance amplifier circuit 32a may be provided by a photodiode PD connected to the input IN via switching means 30.

(37) For example, FIG. 5 shows an embodiment of an optical receiver circuit 3a comprising a plurality of current sources, e.g. light sensors, such as three photodiodes PD.sub.1, PD.sub.2 and PD.sub.3, e.g. IR photodiodes, which are connected through switching means 30a to the input IN of the transimpedance amplifier circuit 32a.

(38) As mentioned before, the switching means 30a may be configured to connect a one of the light sensors PD.sub.1, PD.sub.2 and PD to the input of the transimpedance amplifier circuit 32a. Accordingly, in various embodiments, at each instant, only a single light sensor PD.sub.1, PD.sub.2 and PD.sub.3 is connected to the input of the transimpedance amplifier circuit 32a.

(39) For example, in the embodiment considered, the switching means 30a comprise an electronic switch SW.sub.1, SW.sub.2 and SW.sub.3 for each of the photodiodes PD.sub.1, PD.sub.2 and PD.sub.3, which permit to: connect the anode of a respective photodiode PD.sub.1, PD.sub.2 and PD.sub.3 to the input IN of the transimpedance amplifier circuit 32a, or disconnect the anode of the respective photodiode PD.sub.1, PD.sub.2 and PD.sub.3 from the input IN of the transimpedance amplifier circuit 32a.

(40) Accordingly, in the example considered, the transimpedance amplifier 32a converts the current I.sub.IN provided by the photodiode PD currently connected to the input IN of the transimpedance amplifier circuit 32a into a corresponding voltage signal V.sub.out being indicative of the intensity of light received by the respective photodiode(s) PD.

(41) In the embodiment considered, a processing circuit 36a, which generally may be any analog and/or digital circuit, such as a micro-processor, e.g. a DSP (Digital Signal Processor), elaborates the voltage signal V.sub.out, e.g. in order to detect and analyze a light pulse in the received signal.

(42) Generally, also further analog and/or digital signal processing stages 34a may be provided between the transimpedance amplifier circuit 32a and the processing circuit 36a, such as one or more amplifier stages and/or filters, such as bandpass filters, and/or an analog-to-digital converter.

(43) In the embodiment considered, the processing circuit 36a may select the light sources PD connected to the input IN of the transimpedance amplifier circuit 32a by controlling the switching of the switching means 30a.

(44) For example, as shown in FIG. 6, the processing circuit 36a may connect to the input IN: during a time frame T.sub.1, only the light source/photodiode PD.sub.1, during a following time frame T.sub.2, only the light source/photodiode PD.sub.2, during a following time frame T.sub.3, only the light source/photodiode PD.sub.3.

(45) For example, in various embodiments, the time frames have the same duration/frame time and are repeated periodically.

(46) As mentioned in the foregoing, the light source/photodiode PD may be used to detect a pulse P transmitted e.g. periodically with a given period T.sub.P. For example, portion a) of FIG. 6 shows an exemplary waveform for the transmitted signal TX comprising pulses P.

(47) In various embodiments, the above frame time may thus correspond to the repetition period T.sub.P or a multiple thereof.

(48) For example, in various embodiments, the repetition period of the pulse P may be fixed and configured within the processing circuit 36a. However, the processing circuit 36a may also determine the repetition period T.sub.P of the pulse P by analyzing the received signal V.sub.out.

(49) In various embodiments, the processing circuit 36a may synchronize the switching of the switching means with the repetition period of the pulse P, e.g. in order to ensure that the pulse P is at the end of the time frame.

(50) Accordingly, as shown in portion b) of FIG. 6, once a given light source/photodiode PD is connected to the transimpedance amplifier circuit 32a, the output voltage V.sub.out will exhibit a potential spike due to the variation of the DC offset in the input current I.sub.IN, which in general may be different for the various light sources/photodiodes PD. Accordingly after a given settling time, the output voltage V.sub.out will stabilize at the voltage V.sub.ref and, once a pulse P is received, the input current I.sub.IN is varied rapidly which is visible in the output voltage V.sub.out. For example, in the embodiment considered in FIG. 4, a negative variation will be created in the output voltage V.sub.out.

(51) Accordingly, in the embodiment considered, the settling time of the transimpedance amplifier circuit 32a, i.e. the time required to generate the current I.sub.DC once a different light source/photodiode PD has been connected to the input IN of the transimpedance amplifier circuit 32a should be smaller than the frame time in order to permit a reliable detection of the pulse P.

(52) For example, assuming ideal operational amplifiers, the loop gain G.sub.LOOP of the circuit of FIG. 4 may be approximated with the following equations, with R.sub.2=R.sub.1 and C.sub.2=C.sub.1:

(53) $\begin{array}{cc}{G}_{\mathrm{LOOP}}=\frac{R_F}{R_3}.Math.\frac{1}{\left(1+s.Math.C_F.Math.R_F\right)}.Math.\frac{1}{s.Math.C_1.Math.R_1}& \left(3\right)\end{array}$

(54) and the gain G may be approximated as:

(55) $\begin{array}{cc}G=\frac{V_{\mathrm{out}}}{I_{\mathrm{IN}}}\frac{s.Math.C_1.Math.R_1.Math.R_3}{\left(1+s\frac{C_1.Math.R_1.Math.R_3}{R_F}\right).Math.\left(1+s.Math.C_F.Math.R_F\right)}& \left(4\right)\end{array}$

(56) The approximation of equation (4) is usually satisfied in a proper amplifier design, because the first pole of equation (4):
p.sub.1=R.sub.F/(C.sub.1.Math.R.sub.1.Math.R.sub.2)

(57) should be significantly smaller than the second pole
p.sub.2=1/(R.sub.F.Math.C.sub.F).

(58) In fact, from a design point of view, the frequency f.sub.2 of the second pole p.sub.2 of the transfer function should be chosen high enough in order to get the main energy contributions of the input current pulse, thereby improving the signal to noise ratio. For the same reason, the first pole frequency f.sub.1 should be properly low. Nevertheless, a too low value for this pole frequency is usually not advisable, because not enough attenuation would be performed at low frequencies. Moreover, the time constant of this pole sets the settling time for the DC input current integration.

(59) Accordingly, the circuit shown in FIG. 4 has the drawback that setting the gain loop unity gain frequency (f1) to optimize the transimpedance gain, the resulting settling time may be longer than the required frame time. A missing (and often non-linear) settling will also degrade overall dynamic range.

(60) For example, choosing f.sub.1=50 kHz to maximize the signal capturing according to its spectral density, the time constant would be in the order of 3.2 us whereas the frame time may be 8 us or less.

(61) Accordingly, the circuit shown in FIG. 4 may be faced with an unsolvable trade-off in the transfer functions between signal integration requirements and settling time.

(62) In various embodiments, the settling time of the transimpedance amplifier circuit 32a is improved by reducing the time constants of the differential integrator 322a/324a during a pre-charge phase.

(63) For example, FIG. 7 shows an embodiment, which is based on the exemplary circuits of the differential integrator 324a/322a of FIG. 4.

(64) Specifically, in the embodiment considered, the modified low-pass filter 322b of the differential integrator uses as resistor R.sub.1, now referred to as a resistor R*.sub.1, a resistor with variable resistance value. For example, in the embodiment considered, the variable resistor R*.sub.1 is implemented with a first resistor R.sub.1a and a second resistor and R.sub.1b, which may be connected through an electronic switch SW.sub.1b in parallel with the first resistor R.sub.1a as a function of a control signal PRE.

(65) Similarly, also the modified error amplifier 324b of the differential integrator may use as resistor R.sub.2, now referred to as a resistor R*.sub.2, with variable resistance value. Similarly, also the variable resistor R*.sub.2 may be implemented with a first resistor R.sub.2a and a second resistor and R.sub.2b, which may be connected through an electronic switch SW.sub.1b in parallel with the first resistor R.sub.2a as a function of a control signal PRE.

(66) Accordingly, when the control signal PRE has a first logic level, the resistances of the variable resistors R*.sub.1 and R*.sub.2 correspond to the resistance of the resistors R.sub.1a and R.sub.2a, respectively, which thus corresponds to the configuration shown in FIG. 4. Conversely, when the control signal PRE has a second logic level, the resistances of the variable resistors R*.sub.1 and R*.sub.2 is reduced by connecting the resistors R.sub.1b and R.sub.2b in parallel with the resistors R.sub.1a and R.sub.2a, respectively.

(67) Accordingly, in the embodiment considered, the time constant of the differential integrator 322b/324b may be reduced, thereby varying the feedback control signal FB faster.

(68) For example, in various embodiments, the control signal PRE may be provided by the processing circuit 36a, which is configured to set the control signal PRE to the second logic level during the initial part of the time frames T.sub.1, T.sub.2, T.sub.3, e.g. when a different light source/photodiode PD has been connected to the input IN of the transimpedance amplifier circuit 32a, and to the first logic level during the remainder of the time frames T.sub.1, T.sub.2, T.sub.3, thereby reducing the settling time at the beginning of the time frame without affecting the signal integration behavior during normal operation when a pulse P may be transmitted.

(69) FIG. 8 shows a second embodiment of differential integrator 322c/324c.

(70) Specifically, in the embodiment considered, the differential integrator 322c/324c is configured to reset its capacitors as a function of a reset signal RESET.

(71) For example, in the embodiment considered, the capacitors C.sub.1 and C.sub.2 have associated therewith respective electronic switches SW.sub.1a and SW.sub.2a configured to short-circuit the respective capacitors C.sub.1 or C.sub.2 as a function of the reset signal RESET.

(72) Accordingly, when the reset signal RESET has a first logic level, the capacitors C.sub.1 or C.sub.2 may be charged as discussed with respect to FIG. 4 and, when the reset signal RESET has a second logic level, the capacitors C.sub.1 or C.sub.2 are discharged.

(73) For example, in various embodiments, the reset signal RESET may be provided by the processing circuit 36a, which is configured to set the control signal RESET to the second logic level before the pre-charge phase is started, i.e. during the initial part of the time frames T.sub.1, T.sub.2, T.sub.3, e.g. when a different light source/photodiode PD has been connected to the input IN of the transimpedance amplifier circuit 32a, and to the first logic level during the remainder of the time frames T.sub.1, T.sub.2, T.sub.3.

(74) Accordingly, in various embodiments, the processing unit 36a may be configured to:

(75) a) when a new time frame starts and/or when a different current source PD is connected to the transimpedance amplifier circuit 32a, set the reset signal RESET to the second logic value, thereby discharging the capacitors of the differential integrator 322c/324c;

(76) b) after a given time period, set the reset signal RESET to the first logic value, thereby permitting a charging of the capacitors of the differential integrator 322c/324c;

(77) c) while the reset signal RESET is set to the second logic value, or even once the reset signal RESET is set again to the first logic value, set the control signal PRE to the second logic level, thereby reducing the time constants of the differential integrator 322c/324c and consequently the duration of the settling time; and

(78) d) after a given time period, setting the control signal PRE to the first logic value, thereby permitting a normal operation of the differential integrator 322c/324c used for the final settling and to detect a pulse P in the received signal V.sub.out, or generally a (higher frequency) variation of the input current I.sub.IN.

(79) Accordingly, during a reset phase (driven by the reset signal RESET), the capacitors of the differential integrator 322c/324c are reset, i.e. discharged, and, during a pre-charge phase (driven by the control signal PRE), the capacitors of the differential integrator 322c/324c are charged with a smaller time constant. Generally, the reset and pre-charge function may be used separately, or preferably in combination as shown with respect to the circuit of FIG. 8 permitting both functions.

(80) In various embodiments, also the behavior of the transimpedance amplifier 320a may be adapted during the reset and/or pre-charge phases.

(81) Specifically, in various embodiments, the gain of the transimpedance amplifier 320 is variable.

(82) For example, FIG. 9 shows an embodiment of a transimpedance amplifier 320b with variable gain, which again is based just by way of example on the circuits shown in FIG. 4.

(83) Specifically, in the embodiment considered, the modified transimpedance amplifier 320b uses as feedback resistor R.sub.F, now referred to as a resistor R*.sub.F, with variable resistance value. For example, in the embodiment considered, the variable resistor R*.sub.F is implemented with a first resistor R.sub.Fa and a second resistor R.sub.Fb, which may be connected through an electronic switch SW.sub.F in parallel with the first resistor R.sub.F.

(84) Accordingly, when the control signal for the electronic switch SW.sub.F has a first logic level, the resistance of the variable resistor R*.sub.F corresponds to the resistance of the resistors R.sub.Fa, which represents the configuration shown in FIG. 4. Conversely, when the control signal for the electronic switch SW.sub.F has a second logic level, the resistance of the variable resistor R*.sub.F is reduced by connecting the resistors R.sub.Fb in parallel with the resistor R.sub.Fa.

(85) Accordingly, in the embodiment considered, the gain of the transimpedance amplifier 320b may be reduced, which may be useful for stability purposes during the pre-charge stage. Moreover, the reduced resistance value of the resistors R*.sub.F may be used to discharge (at least in part) the capacitor C.sub.F during the reset phase.

(86) Accordingly, in various embodiments, the electronic switch SW.sub.F is usually opened and closed when the reset signal RESET is set to the second logic value (reset phase) and/or when the control signal PRE is set to the second logic level (pre-charge phase). For example, this operation may be implemented with a combinational logic 3200 (e.g., within the transimpedance amplifier 320b or the processing unit 36a), such as an OR gate, configured to receive at input the signals RESET and PRE and providing at output the control signal for the switch SW.sub.F.

(87) Accordingly, when using the circuits 320b, 322c and 324c in the arrangement of FIG. 4, the integration capacitances (in particular C.sub.1 and C.sub.2 in the embodiment considered) are discharged first by setting the reset signal RESET to the second logic level. Moreover, for stability issues, the reset signal RESET is used to set the gain of the transimpedance amplifier 320b to a low value. After this phase, the processing unit sets the reset signal RESET to the first logic level and (e.g. contemporaneously) the pre-charge signal PRE to the second logic level, which starts the pre-charge phase. Specifically, in the embodiment considered, the transimpedance amplifier 320b is kept in the low gain configuration through the (small) feedback resistance R*.sub.F, while the reset of the integration capacitances (in particular C.sub.1 and C.sub.2 in the embodiment considered) is released and the integration resistance values (in particular R*.sub.1 and R*.sub.2 in the embodiment considered) are reduced by putting smaller resistors R.sub.1b and R.sub.2b in parallel with the resistors R.sub.1a and R.sub.2a. Finally, after a given time period, the pre-charge phase ends by setting the signal PRE to the first logic value and the circuit is again in the normal configuration discussed with respect to FIG. 4, which may be used to detect a pulse in the received signal.

(88) Accordingly, when looking at the previous formulas (3) and (4), the modified frequency f.sub.1* may be moved to a higher frequency than in the effective configuration, by properly choosing the values of R*.sub.F, R*.sub.1 and R*.sub.2. Accordingly, a faster settling of the transimpedance amplifier circuit 32a may be achieved, while maintaining the circuit topology and the stability during normal operation.

(89) The inventors have observed that the modified circuits may not properly deal with the equivalent input voltage offset of the two operational amplifiers.

(90) For example, in the exemplary circuit shown in FIGS. 7, 8 and 9, once the pre-charge phase ends, it is likely that there will still flow a current through the feedback resistance R.sub.F/R.sub.F*, which is proportional to the sum of the operational amplifier offsets V.sub.OS of the operational amplifier OpAmp1 and OpAmp2. Accordingly, when the transimpedance amplifier 320b is switched to the operative configuration, this current (that usually cannot be integrated quickly) will act as an equivalent step signal over the feedback resistance R.sub.F and the output voltage of the transimpedance amplifier 320b will respond to this signal through its effective transfer function. For example, if R.sub.1*=10 k and V.sub.OS=1 mV, the unwanted current signal is in the order of 100 nA (nano-ampere), which may correspond to 10% of the effective full-scale.

(91) So, the offset voltages may cause a not-negligible perturbation after the pre-charge phase that in most cases may only be recovered through a slow time constant. The resulting settling error before the next pulse transmission may thus be affected by this non-ideality, so compromising the effect of the pre-charge phase.

(92) In various embodiments, this issue may be reduced or solved, by an offset-compensation phase, in which the configuration of the differential integrator 322a/324a may be changed.

(93) For example, FIG. 10 shows an embodiment of a differential integrator 322d/324d, which again is based just by way of example on the circuits shown in FIG. 4. Generally, the circuits may also comprise the reset and/or pre-charge circuit shown in FIGS. 7 and 8.

(94) Specifically, in the embodiment considered, the low-pass-filter 322d of the differential integrator 322d/324d comprises a capacitor C.sub.3 and an electronic switch SW.sub.3 configured to connect the capacitor C.sub.3 in parallel with the resistor R.sub.1/R*.sub.1. Specifically, in the embodiment considered, a first terminal of the capacitor C.sub.3 is connected to the inverting input of the operational amplifier OpAmp2, and the second terminal of the capacitor C.sub.3 is connected via the electronic switch SW.sub.3 either to the reference voltage V.sub.ref or to the resistor R.sub.1/R*.sub.1. Accordingly, the capacitor C.sub.3 can be seen as a fraction of the integration capacitance C.sub.1, so no impact for the chip-area is required.

(95) Similarly, the error amplifier 324d of the differential integrator 322d/324d may comprise a capacitor C.sub.4 and an electronic switch SW.sub.4 configured to connect the capacitor C.sub.4 in parallel with the resistor R.sub.2/R*.sub.2. Specifically, in the embodiment considered, a first terminal of the capacitor C.sub.4 is connected to the non-inverting input of the operational amplifier OpAmp2, and the second terminal of the capacitor C.sub.4 is connected via the electronic switch SW.sub.4 either to the reference voltage V.sub.ref or to the resistor R.sub.2/R*.sub.2. Accordingly, in the embodiment considered, the capacitor C.sub.4 is switched from V.sub.ref to V.sub.ref, which is not required from a functional point of view, but is helpful in order to keep the symmetry of the differential integrator, thereby permitting also second order improvements (such as charge injections, etc.). Generally, the switch SW.sub.4 may thus also be omitted and the capacitor C.sub.4 may always be connected in parallel with the resistor R.sub.2/R*.sub.2.

(96) As mentioned in the foregoing, the low-pass filter 322d and the error amplifier 324d implement together a differential integrator. Accordingly, in various embodiments, the capacitance of the capacitor C.sub.4 corresponds to the capacitance of the capacitor C.sub.3.

(97) Accordingly, when the control signal OFFSET used to drive the switches SW.sub.3 and SW.sub.4 has a first logic level, the capacitors C.sub.3 and C.sub.4 are connected between the inputs of the operational amplifier OpAmp2 and V.sub.ref.

(98) Conversely, when the control signal OFFSET has a second logic level, the capacitors C.sub.3 and C.sub.4 are connected in parallel with the resistors R.sub.1 (in particular R.sub.1a in the embodiment considered) and R.sub.2 (in particular R.sub.ea in the embodiment considered), respectively. In this case, the transfer function and the loop gain function of the amplifier circuit 32a are changed, with C.sub.3=C.sub.4 and R.sub.1=R.sub.2:

(99) $\begin{array}{cc}{G}_{\mathrm{LOOP}}=\frac{R_F}{R_3}.Math.\frac{1}{\left(1+s.Math.C_F.Math.R_F\right)}.Math.\frac{1+s.Math.C_3.Math.R_3}{s.Math.C_1.Math.R_1}& \left(5\right)\end{array}$

(100) and the gain G may be approximated as:

(101) $\begin{array}{cc}G=\frac{V_{\mathrm{out}}}{I_{\mathrm{IN}}}\frac{s.Math.C_1.Math.R_1.Math.R_3}{\left[1+s\left(\frac{C_1.Math.R_1.Math.R_3}{R_F}+C_3.Math.R_1\right)\right].Math.\left(1+s.Math.C_F.Math.R_F\right)}& \left(6\right)\end{array}$

(102) Accordingly, by choosing the capacitances C.sub.3 and C.sub.4, while keeping the stability of the loop, it is possible to strongly attenuate the response to the offset voltage dependent current signal (after the end of the pre-charge phase). In fact, as shown by equation (6), the integration bandwidth will be strongly reduced. Then, the perturbation exploited by the amplifier circuit will be significantly reduced, because the recovery time constant remains (practically) unchanged, but the value to recover is significantly smaller than the previous one, thereby permitting a residual error at the end of the settling time which remains acceptable.

(103) Accordingly, as shown in FIG. 11, the processing unit 36a may be configure to generate the signals RESET, PRE and OFFSET, which are usually set to the first logic level (e.g. low) and sequentially to the second logic level (e.g. high), thereby activating for respective time periods T.sub.RESET, T.sub.PRE-CHARGE and T.sub.OFFSET in sequence the reset, pre-charge and offset-compensation phase. Generally, the pre-charge phase should be sufficiently long in order to permit a smoothing of the output perturbation.

(104) In various embodiments, the settling time may be further reduced. Generally, this mechanism may be used in any of the embodiments shown in FIG. 4, 7, 8, 9 or 10, i.e. with or without the reset, pre-charge and/or offset-compensation phase.

(105) Specifically, as shown in FIG. 12, in various embodiments, the transimpedance amplifier circuit 32a comprises in addition to the previously described control loop 322, 324, 326 and 328 (and the respective embodiments described with respect to FIG. 4, 7, 8, 9 or 10), a second feedback control loop configured to perform a first rough DC offset compensation.

(106) Specifically, in the embodiment considered, the second control loop comprises a control part 40 and a variable current source 42 generating a compensation current I*.sub.Dc. For example, in the embodiment considered, the variable current source 42 is implemented with a plurality of constant current sources 422, which may be connected selectively to the input IN of the transimpedance amplifier circuit 32a via respective switching means 420. Accordingly, the previously described first control loop operates in this case with a current I*.sub.IN=I.sub.INI*.sub.DC. Generally, each of the constant current sources 422 may be configured to provide a respective current, which is different for each constant current sources 422.

(107) In the embodiment considered, the control part 40 comprises a comparator 402, such as a comparator with hysteresis, such as a Schmitt trigger, and a control unit (CU) 400. Generally, the operation amplifier OpAmp1 of the transimpedance amplifier 320 may also be reconfigured and used as comparator 402.

(108) Accordingly, in the embodiment considered, the comparator 402 will generate a signal indicating whether the output voltage V.sub.out is smaller or greater than a given threshold.

(109) Accordingly, during a first compensation phase, the control unit 400 may increase the current I*.sub.DC, e.g. by connecting each time an additional current source 422 to the input IN, or changing the type and/or or number of current sources 422 connected to the input IN, until the comparator 402 indicates that the output voltage V.sub.out is smaller than the respective threshold. In fact, knowing the expected minimum-maximum range of the DC current, the variable current source 42 may be designed quiet easily, e.g. usually a few (3-4) constant current sources 422 are sufficient.

(110) Accordingly, in the embodiment considered, the control unit 400 and the variable current source 42 may represent a SAR (Successive-approximation-register) current digital-to-analog converter.

(111) In various embodiment, the control part 40 is enabled via a control signal PRE-CAL, i.e. the current I*.sub.DC remains stable when the control signal PRE-CAL has a first logic value and may be varied when the control signal PRE-CAL has a second logic value.

(112) In various embodiment, the signal PRE-CAL may also be used to disable the first control loop. For example, in the embodiment considered, an electronic switch 44 is connected between the current generator 328 and the input node, which thus disconnects the current generator 328 when the signal PRE-CAL has the second logic value. Accordingly, the transimpedance amplifier 320 acts as a preamplifier for the comparator 402 and the control unit 400 is able to decide the sign of the difference between the background current and the cancellation current.

(113) For example, this control signal PRE-CAL may also be generate by the processing unit 36a. For example, as shown in FIG. 13, the control signal PRE-CAL may be set to the second logic level before the previously described reset, pre-charge and offset-compensation phases are started, i.e. these phases operate already with the pre-compensate current I*.sub.IN, i.e. only a residual background current has to be canceled through the first control loop.

(114) For example, in various embodiment, the second control loop is configured to maintain a residual background current I*.sub.IN with the same sign of the effective one I.sub.IN.

(115) The previously described embodiment has also the advantage, that the maximum background current to be compensated by the first control loop is limited and e.g. the value of the resistance R.sub.3 may be increased, thereby improving the dynamic range of the whole amplifier circuit 32a.

(116) Finally, as shown in FIG. 14, another minor bottleneck may be found in the parasitic capacitance C.sub.0 associated with the input IN of the transimpedance amplifier circuit 32a. This capacitance C.sub.0 (typically in the order of some tens of pF) depends e.g. on pad capacitance, PCB trace, photodiode capacitance.

(117) Specifically, FIG. 14 shows a modified transimpedance amplifier circuit 32b, which comprises, in addition to any one of the previously described transimpedance amplifier circuit 32a, a circuit 50 connected between the input IN and the input of the transimpedance amplifier circuit 32a.

(118) Specifically, in the embodiment considered, the circuit 50 comprises a regulated cascode 502 with associated regulation (Reg) unit 504 and current bias generator 500. Cascode or regulated-cascode configurations are a well-known solution to read a signal current and they allow performing this current read-out through a quite low input impedance so leading to a good decoupling with respect to input capacitance. Otherwise, this capacitance put at the input of a traditional structure may limit the stability and the bandwidth of the TIA. Basically, the cascode allows decoupling the parasitic capacitance C.sub.0, acting as a simple current transfer.

(119) For example, the steering current DAC 40/42 (see FIG. 12) can be used for both to keep (always) biased the source follower arrangement and to act as current compensation DAC during the effective framework.

(120) Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.