METHOD OF COLLECTING SIGNALS SENSED FROM SENSING TRANSISTORS, CORRESPONDING SENSOR DEVICE AND IMAGING CAMERA

Abstract

Current signals indicative of sensed physical quantities are collected from sensing transistors in an array of sensing transistors. The sensing transistors have respective control nodes and current channel paths therethrough between respective first nodes and a second node common to the sensing transistors. A bias voltage level is applied to the respective first nodes of the sensing transistors in the array and one sensing transistor in the array of sensing transistors is selected. The selected sensing transistor is decoupled from the bias voltage level, while the remaining sensing transistors in the array of sensing transistors maintain coupling to the bias voltage level. The respective first node of the selected sensing transistor in the array of sensing transistors is coupled to an output node, and an output current signal is collected from the output node.

Claims

1. A method for collecting current signals indicative of sensed physical quantities from sensing transistors in an array of sensing transistors, wherein the sensing transistors in the array of sensing transistors have respective control nodes and current channel paths therethrough between respective first nodes and a second node common to the sensing transistors in the array, the method comprising: applying a bias voltage level to the first nodes of all of the sensing transistors in the array; selecting a sensing transistor in the array of sensing transistors; decoupling the first node of the selected sensing transistor from said bias voltage level while simultaneously maintaining coupling of the first nodes of the sensing transistors in the array of sensing transistors other than the selected sensing transistor to said bias voltage level; coupling the first node of the selected sensing transistor to an output node; and collecting an output current signal from said output node.

2. The method of claim 1, wherein selecting comprises sequentially selecting a different sensing transistor in the array of sensing transistors whose first node is decoupled from the bias voltage level, and wherein collecting comprises sequentially collecting current signals provided from each of the sequentially selected sensing transistors.

3. The method of claim 1, wherein a plurality of arrangements of matching transistors in the array of sensing transistors are configured to selectively couple respective first nodes of sensing transistors to a biasing voltage source providing the bias voltage level and to the output node in an alternative manner based on a plurality of control signals, wherein decoupling the selected sensing transistor from said bias voltage level while simultaneously maintaining coupling of the first nodes of the sensing transistors in the array of sensing transistors other than the selected sensing transistor to said bias voltage level comprises: setting a selected control signal of a respective selective arrangement matching the selected sensing transistor to a first value and setting control signals in the plurality of control signals other than the selected control signal to a second value opposite said first value.

4. The method of claim 3, comprising: providing at least one clock signal; producing a binary signal indicative of a number of clock cycles of the at least one clock signal; and producing the control signals based on said binary signal indicative of the number of clock cycles of the at least one clock signal.

5. The method of claim 1, wherein at least one reference sensing transistor is configured to provide a blind reference current, the method further comprising: coupling the selected sensing transistor in the array to the at least one reference sensing transistor; subtracting said blind reference current from a current signal of the selected sensing transistor; and producing a normalized current signal resulting from the subtraction; wherein coupling comprises coupling the normalized current signal to the output node for collection as said output current signal.

6. The method of claim 5, further comprising outputing the blind reference current from the reference sensing transistor to at least one further output terminal for collection.

7. The method of claim 1, wherein the array of sensing transistors is a planar array, a position of a sensing transistor in the array of sensing transistors and of the matching selective arrangements being identified with a tuple of indices, and wherein the method further comprises: providing a biasing voltage level and coupling thereto said respective first nodes of sensing transistors and the at least one reference transistor in the array of sensing transistors; selecting a sensing transistor in every row of the array of sensors; decoupling the selected sensing transistor in every row from said bias voltage level while simultaneously maintaining coupled to the bias voltage level the sensing transistors in the array of sensing transistors other than the sensing transistor selected; and coupling each of the selected sensing transistor in every row of the array of sensing transistors to a respective output node in a plurality of output nodes and collecting the respective current signals in parallel therefrom.

8. A sensor device, comprising: an array of sensing transistors configured to provide respective current signals indicative of sensed physical quantities, wherein the sensing transistors in the array of sensing transistors have respective control nodes and current channel paths therethrough between respective first nodes and a second node common to the sensing transistors in the array; and circuitry coupled to the array of sensing transistors and configured to collect signals from sensing transistors in the array of sensing transistors by: applying a bias voltage level to the first nodes of all of the sensing transistors in the array; selecting a sensing transistor in the array of sensing transistors; decoupling the first node of the selected sensing transistor from said bias voltage level while simultaneously maintaining coupling of the first nodes of the sensing transistors in the array of sensing transistors other than the selected sensing transistor to said bias voltage level; and coupling the first node of the selected sensing transistor to an output node; and collecting an output current signal from said output node.

9. The sensor device of claim 8, wherein said sensing transistors in the array of sensing transistors comprise thermal MOS (TMOS) transistors configured to detect infra-red light.

10. The sensor device of claim 8, wherein said circuitry is further configured to sequentially select a different sensing transistor in the array of sensing transistors, and sequentially collecting current signals provided from said different selected sensing transistors.

11. The sensor device of claim 8, wherein the plurality of arrangements of matching transistors in the array of sensing transistors are configured to selectively couple respective first nodes of sensing transistors to a biasing voltage source and the output node in an alternative manner based on a plurality of control signals, and wherein the circuitry, in decoupling the selected sensing transistor from said bias voltage level while maintaining coupling to said bias voltage level the sensing transistors in the array of sensing transistors other than the selected sensing transistor, is configured to: set a selected control signal of a respective selective arrangement matching the selected sensing transistor to a first value and set control signals in the plurality of control signals other than the selected control signal to a second value opposite said first value.

12. The sensor device of claim 11, wherein the circuitry is further configured to: provide at least one clock signal; produce a binary signal indicative of a number of clock cycles of the at least one clock signal; and produce the control signals based on said binary signal indicative of the number of clock cycles of the at least one clock signal.

13. The sensor device of claim 8, further comprising at least one reference sensing transistor configured to provide a blind reference current, and wherein the circuitry is further configured to: couple the selected sensing transistor in the array to the at least one reference sensing transistor; subtract said blind reference current from a current signal of the selected sensing transistor; and produce a normalized current signal as a result of the subtraction; wherein said coupling comprises coupling the normalized current signal to the output node for collection as said output current signal.

14. The sensor device of claim 13, further comprising at least one further output terminal configured to collect the blind reference current from the reference sensing transistor.

15. The sensor device of claim 8, wherein the array of sensing transistors is a planar array, a position of a sensing transistor in the array of sensing transistors and of the matching selective arrangements being identified with a tuple of indices, and wherein the circuitry is further configured to: provide a biasing voltage level and coupling thereto said respective first nodes of sensing transistors and the at least one reference transistor in the array of sensing transistors; select a sensing transistor in every row of the array of sensors; decouple the selected sensing transistor in every row from said bias voltage level while maintaining coupled to the bias voltage level the sensing transistors in the array of sensing transistors other than the sensing transistor selected; and couple each of the selected sensing transistor in every row of the array of sensing transistors to a respective output node in a plurality of output nodes and collecting the respective current signals in parallel therefrom.

16. An imaging camera equipped with the sensor device of claim 9.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments will now be described, by way of non-limiting example only, with reference to the annexed Figures, wherein:

[0023] FIG. 1 is a circuit diagram exemplary of an array of sensing transistors;

[0024] FIGS. 2 and 3 are diagrams exemplary of properties of sensing transistors; and

[0025] FIGS. 4 and 5 are diagrams exemplary of embodiments as per the present disclosure.

DETAILED DESCRIPTION

[0026] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0027] Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment.

[0028] Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0029] The drawings are in simplified form and are not to precise scale.

[0030] Throughout the figures annexed herein, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for brevity.

[0031] The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0032] FIG. 1 is a circuit diagram of a thermal detector array, comprising a sensing circuit portion 10 and a signal processing circuit portion 100.

[0033] For the sake of simplicity, one or more embodiments discuss detector arrays including TMOS devices configured to detect infra-red (IR) radiation to provide a signal indicative of a temperature of an object, being otherwise understood that such a kind of sensor devices is purely exemplary and in no way limiting. One or more embodiments may use notionally any kind of sensor, for detecting not only temperature but also other physical quantities, such as pressure, for instance.

[0034] As exemplified in FIG. 1, the sensing circuit portion 10 comprises a bidimensional matrix arrangement 10 of a plurality of IR sensors (e.g., TMOS devices) T.sub.11, T.sub.1m, . . . , T.sub.ij, T.sub.nl, T.sub.nm, the matrix arrangement 10 having a number of n rows and m columns, the position of an ij-th IR sensor T.sub.ij in the matrix arrangement 10 being identified via a tuple of indexes comprising a first (e.g., row) index i and a second (e.g., column) index j.

[0035] For instance, IR sensors T.sub.11, T.sub.1m, . . . , T.sub.ij, . . . on a same i-th row have a common source terminal configured to be coupled to a first common voltage node (e.g., ground) and a common gate terminal configured to be coupled to a biasing voltage level Vg.

[0036] The arrangement of thermal sensors as exemplified in FIG. 1 may be used in an IR camera 1000 to produce an image of an object emitting IR radiation by considering the ij-th IR sensor T.sub.ij as a pixel of the IR camera 1000. Specifically, a series of bidimensional images may be produced based on thermal IR detectors T.sub.11, T.sub.1m, . . . , T.sub.ij, T.sub.n1, T.sub.n, arranged two-dimensionally as pixels of the images to detect.

[0037] As exemplified in FIG. 1, the sensing circuitry 10 further comprises: a biasing branch V.sub.g configured to provide proper biasing voltage level Vg at the control nodes (e.g., gates) of IR sensors of the array T.sub.11, T.sub.1m, . . . , T.sub.ij, . . . , T.sub.n1, T.sub.nm; and a plurality of switches comprising a first plurality of (e.g., horizontal) switches and a second plurality of (e.g., vertical) switches, wherein a j-th switch M.sub.yj in the first plurality of switches and a i-th switch M.sub.xi in the second plurality of switches is coupled to an ij-th IR sensor T.sub.ij in the array of sensors 10.

[0038] As exemplified in FIG. 1, the signal processing circuit portion 100 of the detector comprises a multiplexing arrangement 102, 104 including a pair of shift registers 102, 104. For instance: a first (e.g., vertical) shift register 102 in the pair of shift registers 102, 104 is coupled to the first plurality of switches M.sub.yj, the first shift register 102 configured to select the j-th item (e.g., row) of the matrix 10 by activating a j-th switch M.sub.yj; and the second (e.g., horizontal) shift register 104 is coupled to the second plurality of switches, the second shift register 104 configured to select the i-th entry (e.g., column) of the matrix arrangement 10 by activating an i-th horizontal switch M.sub.xi.

[0039] As exemplified in FIG. 1, the processing circuitry 100 further comprises a reference (e.g., MOSFET) transistor M.sub.REF coupled to at least one shift register (e.g., 104) and to a preamplifier stage 106, and a pair of identical resistive loads Z coupled to the preamplifier stage 106 and to the array 10.

[0040] In a conventional IR detector as exemplified in FIG. 1, output signals from pixels T.sub.ij are (e.g., sequentially) read to and output to a common read amplifier 106.

[0041] For instance, the processing circuitry 100 is configured to select (via swiches M.sub.xi, M.sub.yj) an ij-th IR sensor T.sub.ij and to couple reference MOS M.sub.REF and the load Z thereto, forming a Wheatstone-like bridge as a result, the bridge configured to convert drain currents in the ij-th sensor T.sub.ij, in a manner per se known.

[0042] As exemplified in FIG. 1, when an ij-th sensor T.sub.ij is selected and coupled to the bias branch Vg, all remaining non-selected sensors T.sub.11, T.sub.1m, . . . , T.sub.n1, T.sub.nm remain turned off.

[0043] For instance, a (drain) current flowing in the selected sensor T.sub.ij may be received and amplified via the preamplifier stage 106, e.g., an operational amplifier.

[0044] As exemplified in FIG. 1, a serial readout with a single preamplifier 106 provides a relatively simple implementation.

[0045] Sensing performance of a TMOS sensor T.sub.ij varies based on different parameters, among which an important role can be played by: thermal parameter τ, which is inversely proportional to a (residual) pressure inside the TMOS device (e.g., about 0.01-1 Pascal pressure, corresponding to a thermal parameter about 80-100 milliseconds), as exemplified in FIG. 2; and gate-source voltage V.sub.GS evolution over time, in particular a transient interval over time Δt, which is the time interval Δt in which the signal V.sub.GS varies from an initial value V.sub.0 to a steady state value V.sub.∞.

[0046] As exemplified in FIG. 3, in an exemplary case where the TMOS T.sub.ij is biased using a current I.sub.0 provided at an initial time t.sub.0, the gate-source voltage signal V.sub.GS evolves from an initial value V.sub.0, reaching a steady state value V.sub.∞ after the time interval Δt which may be expressed as a multiple of the thermal parameter τ, e.g., Δt=4τ.

[0047] Thermal τ and time Δt parameters can be relevant as it is desirable not to perform thermal sensing during the transient time Δt (which is based on τ) of the TMOS T.sub.ij. This reduces a possibility of obtaining a temperature measurement influenced by the thermal contribution of power dissipated in the TMOS T.sub.ij due to the transient voltage variation from initial value V.sub.0 to steady state value V.sub.∞.

[0048] In one or more embodiments as exemplified in FIGS. 4 and 5, the dependence of the sensing performance from the thermal parameter τ may be reduced.

[0049] As exemplified in FIG. 4, an IR detector array 40, 400 as per the present disclosure comprises a sensing circuit portion 40 and a signal processing circuit portion 400.

[0050] As exemplified in FIG. 4, the sensing circuit portion 40 of the IR detector array comprises a first “active” plurality of TMOS sensors T.sub.11, T.sub.ij, T.sub.1n, T.sub.n1 , T.sub.n2, T.sub.nm arranged in a matrix of n rows and m columns, with an ij-th TMOS sensor T.sub.ij identified by a tuple of indices as discussed in the foregoing with respect to the array 10 of FIG. 1; the TMOS sensors T.sub.11, . . . , T.sub.1n of a i-th row have a common gate terminal, e.g., G.sub.1 for all sensors T.sub.11, . . . , T.sub.1n of a first row, and a common source terminal S. The sensing circuit portion 40 further comprises a biasing node D.sub.B configured to couple the “blind” sensor M.sub.B to a biasing branch VDD configured to provide a biasing voltage, for instance via a current mirror M.sub.mir, M.sub.B, coupled to a first operational amplifier 406 configured to set a value of drain-source voltage of the (e.g., MOSFET) transistors of the current mirror arrangement M.sub.mir, M.sub.B to a reference voltage V.sub.REF. The sensing circuit portion 40 also comprises an array of selective elements M.sub.11, M.sub.ij, M.sub.1n, M.sub.n1, M.sub.n2, M.sub.nm comprising selective elements arranged in the same matrix arrangement of the array of sensors 40, an ij-th array of selective elements identified by a tuple of indexes, each coupled to a sensor T.sub.ij in the array of sensors 40 having a matching tuple of index values, e.g., selective arrangement M.sub.11 coupled to sensor T.sub.11.

[0051] As exemplified herein, a sensor device comprises an array of sensing transistors (for instance, T.sub.11, T.sub.ij, T.sub.1n, T.sub.n1, T.sub.n2, T.sub.nm) configured to provide respective current signals indicative of sensed physical quantities, wherein the sensing transistors in the array of sensing transistors have respective control nodes (for instance, G.sub.1, . . . , G.sub.n) and current channel paths therethrough between respective first nodes and a second node (S) common to the sensing transistors in the array. The sensor device further includes signal processing circuitry coupled to the array of sensing transistors and configured to collect signals from sensing transistors in the array of sensing transistors (for instance, T.sub.11, T.sub.ij, T.sub.1n, T.sub.n1, T.sub.n2, T.sub.nm) according to a method as per the present disclosure.

[0052] For instance, sensing transistors in the array of sensing transistors comprise TMOS transistors configured to detect infra-red light.

[0053] As exemplified herein, an imaging camera (for instance, 1000) is equipped with the sensor device as per the present disclosure.

[0054] As exemplified in FIG. 4, an ij-th selective arrangement M.sub.ij in the selective arrangement of the array of sensors 40 comprises a pair of switches M.sub.ijA, M.sub.ijB configured to operate as a differential pair and having respective control terminals configured to receive driving signals from the signal processing circuit portion 400 of the detector.

[0055] As exemplified in FIG. 4, the signal processing circuit portion 400 comprises a first multiplexing arrangement 402 comprising a m-bit binary counter 401 and a first decoder 402, the m-bit binary counter 401 configured to receive a first clock signal f.sub.CKm and to provide a m-bit signal to the first shift register 402, the m-bit decoder 402 configured to produce a set of 2.sup.m control signals ϕ.sub.11, ϕ′.sub.11, ϕ.sub.ij, ϕ′.sub.ij, ϕ.sub.1m, ϕ′.sub.1m, the set of 2.sup.m control signals comprising a first group of 2.sup.m−1 signals ϕ.sub.11, ϕ.sub.ij, ϕ.sub.1m configured to drive the control terminal of a first transistor (e.g., those labeled with suffix A in FIG. 4) of the pair of transistors in each selective arrangement (e.g., M.sub.11A in selective arrangement M.sub.11) and a second group of 2.sup.m−1 signals ϕ′.sub.11, ϕ′.sub.ij, ϕ′.sub.1n configured to drive the control terminal of a second transistor (e.g., labeled with suffix B in FIG. 4) of the pair of transistors in each selective arrangement (e.g., M.sub.11B in selective arrangement M.sub.11), the second group of signals ϕ′.sub.11, ϕ′.sub.ij, ϕ′.sub.1n produced as a negation (e.g., as an opposite replica) of the signals in the first group of signals, e.g. ϕ′.sub.11=not(ϕ.sub.11); these signals are used to selectively activate/deactivate an ij-th sensor T.sub.ij in the array of sensors 40, as discussed in the following. The signal processing circuit portion 400 further comprises a second multiplexing arrangement 403, 404 comprising a n-bit binary counter 403 and a second decoder 404, the n-bit binary counter 403 configured to receive a second clock signal f.sub.CKn and to provide a n-bit signal to the second shift register 404, the n-bit decoder 402 configured to produce a set of 2.sup.n control signals ϕ.sub.11, ϕ′.sub.11, ϕ.sub.ij, ϕ′.sub.ij, ϕ.sub.n1, ϕ′.sub.n1, the set of 2.sup.n control signals comprising a first group of 2.sup.n−1 signals ϕ.sub.11, ϕ.sub.ij, ϕ.sub.1n configured to drive the control terminal of a first transistor (e.g., labeled with suffix A in FIG. 4) of the pair of transistors in each selective arrangement (e.g., M.sub.11A in selective arrangement M.sub.11) and a second group of 2.sup.n−1 signals ϕ′.sub.11, ϕ′.sub.ij, ϕ′.sub.1n configured to drive the control terminal of a second transistor (e.g., labeled with suffice B in FIG. 4) of the pair of transistors in each selective arrangement (e.g., M.sub.11B in selective arrangement M.sub.11), the second group of signals produced as a negation (e.g., as an opposite replica) of the signals in the first group of signals, e.g. ϕ′.sub.11=not(ϕ.sub.11); these signals are used to selectively activate/deactivate an ij-th sensor T.sub.ij of the array of sensors 40, as discussed in the following.

[0056] As exemplified in FIG. 4, a single active IR sensor T.sub.ij can be selected using the first and second decoder stages 401, 402, 403, 404, as discussed in the following.

[0057] As exemplified in FIG. 4, the IR detector 40, 400 further comprises an “active” pin D.sub.A and a “blind” pin D.sub.B configured to provide signals from a selected, “active” sensor T.sub.ij and from the blind element M.sub.B, respectively, for instance couplable to an amplification chain 50 to read output signals therefrom and to produce IR images based on read/sensed signals. The IR detector 40, 400 further comprises a first amplifier stage 406, e.g., operational transconductance amplifier (OTA) having a non-inverting input node 406a, an inverting input node 406b coupled to a reference voltage level V.sub.REF and an output node 406d, and a second amplifier stage 408, for instance an OTA having a first non-inverting input node 408a, a second non-inverting input node 408b, an inverting input node 406c coupled to the reference voltage level V.sub.REF and an output node 408d. A second biasing node VDD is configured to be coupled to said first and second amplifier stages 406, 408. Transistors M.sub.mir, M.sub.B are in a current mirror arrangement, the transistors M.sub.mir, M.sub.B having a common gate terminal coupled to the output node 406d of the first operational amplifier 406 and having a drain-source current path and being coupled to the second non-inverting input node 408b of the second amplifier stage 408. A bias current generator I.sub.BIAS is coupled to the current mirror arrangement M.sub.mir, M.sub.B and configured to provide biasing to an ij-th thermal sensor T.sub.ij selectively forming a current mirror therewith, as discussed in the following.

[0058] For instance: the first amplifier stage 406 is configured to set a drain-source voltage V.sub.DS of the transistors in the current mirror arrangement; the blind pin D.sub.B is coupled to a drain terminal of transistor M.sub.B in the current mirror arrangement M.sub.mir, M.sub.B and to the second non-inverting node 408b of the second amplifier stage 408; the active pin D.sub.A is configured to be selectively coupled to a target ij-th sensor of the array T.sub.ij; and the second amplifier stage 408 is configured to set a value of drain-source voltage V.sub.DS of the transistors M.sub.mir, M.sub.B in the current mirror arrangement to a reference voltage V.sub.REF.

[0059] As exemplified in FIG. 4, row-wise common gate nodes G.sub.1, . . . , G.sub.n are coupled to a common node, for instance a gate terminal of the transistors in the current mirror arrangement M.sub.mir, M.sub.B. As a result, all sensors T.sub.11, . . . , T.sub.ij, T.sub.nm in the sensing circuit portion 40 can be biased via the biasing current I.sub.BIAS “reflected” via mirror arrangement M.sub.mir, M.sub.B.

[0060] As exemplified in FIG. 4, a method of reading a value of a target ij-th sensor (e.g., T.sub.11) in the plurality of IR sensors T.sub.11, . . . , T.sub.ij, . . . , T.sub.nm in the sensing circuit portion 40 comprises: [0061] setting a first control signal (e.g., ϕ.sub.11) for the target ij-th sensor (e.g., T.sub.11) to a first value, e.g., “0”; [0062] obtaining a second control signal (e.g., ϕ′.sub.11) for the target ij-th sensor (e.g., T.sub.11) having a second value opposite said first value, e.g., “1”; [0063] in response to the second value of the second control signal (e.g., ϕ′.sub.11=1) for the target ij-th sensor (e.g., ϕ′.sub.11), coupling a first (e.g., drain) terminal of the target ij-th sensor (e.g., T.sub.11) to the second OTA 408, in particular to the first non-inverting input 408a thereof; [0064] as a result, setting drain-source voltage of the blind transistor M.sub.B in the current mirror arrangement M.sub.mir, M.sub.B and of the selected target ij-th sensor (e.g., T.sub.11) at the reference voltage V.sub.REF, for instance exploiting the high gain of the OTA 408; and [0065] repeating sequentially the operations above for any ij-th sensor T.sub.ij in the array of sensors.

[0066] It is noted that, when an ij-th control signal (e.g., ϕ.sub.11) is set to the first value (e.g., ϕ.sub.11=0) in order to select the target ij-th IR sensor (e.g., T.sub.11), all other control signals are at the second value (e.g., “1” or VDD.)

[0067] As exemplified in FIG. 4, leakage currents from selective arrangements M.sub.11, . . . , M.sub.1n are reduced, for instance to a value equal to a product of biasing current I.sub.BIAS and on-resistance R.sub.on of the (selected) selective arrangements (e.g., M.sub.11A in the example above).

[0068] As exemplified in FIG. 4, a circuit block 410 comprises the second amplifier stage 408, the blind transistor M.sub.B, the respective blind D.sub.B and active pins D.sub.A and a j-th row of sensors T.sub.n1, . . . , T.sub.nm(and respective selective arrangements M.sub.n1, . . . , M.sub.nm) of the sensor array 40.

[0069] As exemplified in FIG. 5, circuit block 410 may be replicated, with a replica 410a, . . . , 410n for each item (e.g., row) in an alternative embodiment 50 configured to perform reading of multiple sensors T.sub.11, . . . , T.sub.ij, . . . , T.sub.nm in parallel. For instance, this facilitates increasing a speed of processing signals in the signal processing portion 400.

[0070] A method as exemplified herein, comprises: collecting current signals from sensing transistors in an array of sensing transistors (for instance, T.sub.11, T.sub.ij, T.sub.1n, T.sub.n1, T.sub.n2, T.sub.nm) configured to provide respective current signals indicative of sensed physical quantities, wherein the sensing transistors in the array of sensing transistors have respective control nodes (for instance, G.sub.1, . . . , G.sub.n) and current channel paths therethrough between respective first nodes and a second node (for instance, S) common to the sensing transistors in the array.

[0071] For instance, the method comprises: [0072] applying a bias voltage level (for instance, V.sub.REF) to said respective first nodes of the sensing transistors in the array; [0073] selecting (for instance, M.sub.ij) a sensing transistor (for instance, T.sub.ij) in the array of sensing transistors; [0074] decoupling (for instance, ϕ.sub.ij) the selected sensing transistor from the bias voltage level while maintaining coupled (for instance, ϕ.sub.11, ϕ.sub.ij, ϕ.sub.1m, ϕ.sub.n1, ϕ.sub.n1) to the bias voltage level (V.sub.REF) the sensing transistors in the array of sensing transistors other than the sensing transistor selected (for instance, T.sub.ij); and [0075] coupling (for instance, ϕ′.sub.ij) to an output node (for instance, D.sub.A) the respective first node of the sensing transistor selected in the array of sensing transistors and collecting an output current signal from said output.

[0076] As exemplified herein, the method further comprises sequentially selecting a different sensing transistor (for instance, T.sub.ij) in the array of sensing transistors, sequentially collecting current signals provided from said different sensing transistors selected.

[0077] As exemplified herein, the method further comprises providing a plurality of arrangements of matching transistors (for instance, M.sub.11, M.sub.ij, M.sub.1n, M.sub.n1, M.sub.n2, M.sub.nm) in the array of sensing transistors, the arrangements of matching transistors in the array of sensing transistors configured to selectively couple respective first nodes of sensing transistors to a biasing voltage source (for instance, V.sub.REF) or to the output node, alternatively, based on a plurality of control signals (for instance, ϕ.sub.11, ϕ.sub.1m, ϕ.sub.n1, ϕ.sub.n1).

[0078] Decoupling (for instance, ϕ.sub.ij) the selected sensing transistor (for instance, T.sub.ij) from the bias voltage level (for instance, V.sub.REF) while maintaining coupled (for instance, ϕ.sub.11, ϕ.sub.ij, ϕ.sub.1m, ϕ.sub.n1, ϕ.sub.n1) to the bias voltage level the sensing transistors in the array of sensing transistors other than the sensing transistor selected comprises setting a selected control signal (for instance, ϕ.sub.ij) of a respective selective (transistor) arrangement (for instance, M.sub.ij) matching the selected sensing transistor (for instance, T.sub.ij) to a first value and setting control signals in the plurality of control signals (for instance, ϕ.sub.11, ϕ.sub.1m, ϕ.sub.n1, ϕ.sub.n1) other than the selected control signal (ϕ.sub.ij) to a second value opposite said first value.

[0079] For instance, the method comprises: [0080] providing at least one clock signal (e.g., f.sub.CKn, f.sub.CKm); [0081] producing (for instance, 401, 403) a binary signal indicative of a number of cycles of the at least one clock signal; and [0082] producing (for instance, 402, 404) the control signals based on the binary signal indicative of a number of cycles of the at least one clock signal.

[0083] As exemplified herein, the method comprises: [0084] providing at least one reference sensing transistor (for instance, M.sub.B) configured to provide a blind reference current; and [0085] coupling the selected sensing transistor (for instance, T.sub.ij) in the array of sensing transistors to the at least one reference sensing transistor, subtracting said blind reference current from the respective current signal, producing a respective normalized current signal as a result, and coupling the selected sensing transistor (for instance, T.sub.ij) in the array of sensing transistors to the output node (for instance, D.sub.A), collecting the respective normalized current signal therefrom.

[0086] One or more embodiments as exemplified in FIG. 5 exploit to the possibility to select concurrently a group of sensors T.sub.11, . . . , T.sub.1m belonging to an item or entry (e.g., row) of the sensing circuit portion of the array 50, reducing a time for converting drain-source current values to pixel values.

[0087] As exemplified in FIG. 5, an array 50 comprises replicas 410a, . . . , 410n of circuit block 410 as exemplified in FIG. 4 repeated at each row of sensors (e.g., T.sub.11, . . . , T.sub.1n).

[0088] As exemplified in FIG. 5, each row of the array of sensors 50 comprises a respective blind sensor M.sub.B1, . . . , M.sub.Bj and an operational amplifier 408a, . . . , 408n.

[0089] For instance, array 50 comprises: a plurality of blind pixels M.sub.Bj for each j-th row of the array 50; a plurality of second amplifier stages 408a, . . . , 408n, one for each j-th row of the array 50; a plurality of active pins D.sub.A1, . . . , D.sub.An, and a plurality of blind pins D.sub.B1, . . . , D.sub.Bn; and a plurality of selective arrangements M.sub.j1, M.sub.jnn coupled to the respective IR sensor T.sub.j1, . . . , T.sub.jn of the array 50, to the amplifier stages 408a, . . . , 408n and to the respective active pin D.sub.Aj and blind pin D.sub.Aj.

[0090] For instance, selecting a j-th row of sensors of the array 5, comprises: setting all control signals to a first, e.g., “0”, value, e.g., Φ.sub.11=Φ.sub.21=. . . =Φ.sub.j1=0; as a result, coupling all sensors T.sub.n1, . . . T.sub.nm in a j-th row to the respective j-th second amplifier stage (e.g., 408n) and to the respective active pin D.sub.Aj, producing a plurality of reading signals to user circuit 60 as a result.

[0091] For instance, an active pixel T.sub.ij per i-th row can be selected and connected to the output drain of the row D.sub.Aj, while the remaining non-selected pixels T.sub.11, . . . , T.sub.1n are biased on at same current and V.sub.DS.

[0092] It is noted that while selecting a j-th row, remaining IR sensors in the array 50 remain biased via reference voltage V.sub.REF during their inactivity, so that also “blind” (that is, during inactivity) current values may be provided at respective blind pins D.sub.B1, . . . , D.sub.Bj, . . . , D.sub.Bm, for instance at a same time with active currents provided at the active pins D.sub.A1, D.sub.Aj, D.sub.An.

[0093] As exemplified herein, a method comprises providing at least one further output terminal (for instance, D.sub.B) configured to collect the blind reference current from the reference sensing transistor (for instance, M.sub.B).

[0094] As exemplified herein, the array of sensing transistors (for instance, T.sub.11, T.sub.ij, T.sub.1n, T.sub.n1, T.sub.n2, T.sub.nm) is a planar array, a position of a sensing transistor in the array of sensing transistors and of the matching selective arrangements (for instance, M.sub.ij) is identified with a tuple of indices.

[0095] For instance, the method comprises: [0096] providing a biasing voltage level (for instance, V.sub.REF) and coupling thereto said respective first nodes of sensing transistors and the at least one reference transistor (for instance, M.sub.B) in the array of sensing transistors; [0097] selecting (for instance, M.sub.ij) a sensing transistor (for instance, T.sub.ij) in every row of the array of sensors; [0098] decoupling (for instance, ϕ.sub.ij) the selected sensing transistor in every row from the bias voltage level while maintaining coupled (for instance, ϕ.sub.11ϕ.sub.ij, ϕ.sub.1m, ϕ.sub.n1, ϕ.sub.n1) to the bias voltage level the sensing transistors in the array of sensing transistors other than the sensing transistor selected; and [0099] coupling each of the selected sensing transistor in every row of the array of sensing transistors to a respective output node in a plurality of output nodes (for instance, D.sub.A1, . . . , D.sub.Am) and collecting the respective current signals in parallel therefrom.

[0100] It will be otherwise understood that the various individual implementing options exemplified throughout the figures accompanying this description are not necessarily intended to be adopted in the same combinations exemplified in the figures. One or more embodiments may thus adopt these (otherwise non-mandatory) options individually and/or in different combinations with respect to the combination exemplified in the accompanying figures.

[0101] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

[0102] The claims are an integral part of the technical teaching provided herein with reference to the embodiments.

[0103] The extent of protection is determined by the annexed claims.