MULTI-MODE FUSION MULTIPLIER
20220374205 · 2022-11-24
Inventors
- Tuanbao FAN (Shanghai, CN)
- Yuexing JIANG (Shanghai, CN)
- Xiaoshan SHI (Shanghai, CN)
- Zhao YANG (Beijing, CN)
Cpc classification
G06F2207/3828
PHYSICS
International classification
Abstract
A multiplier is configured to implement a binary single-multiplication operation A[m.sub.1-1:0]×B[m.sub.2-1:0], or an accumulated sum operation of 2N binary multiplications A0[m.sub.3-1:0]×B0[m.sub.4-1:0]. The multiplier includes P precoders, Q groups of fusion coders, and a compressor. The P precoders and the Q groups of fusion coders are configured to code a first value and a second value in the single-multiplication operation or the multi-multiplication accumulated sum operation, and output a plurality of partial products to the compressor. The compressor may be configured to compress the plurality of partial products corresponding to the single-multiplication operation or the multi-multiplication accumulated sum operation to obtain two accumulated values.
Claims
1. A multi-mode fusion multiplier, configured to receive inputs A[m.sub.1-1:0] and B[m-1:0] or A0[m.sub.3-1:0] and B0[m.sub.4-1:0] and to perform a binary single-multiplication operation A[m.sub.1-1:0]×B[m.sub.2-1:0] or an accumulated sum operation of 2N binary multiplications A0[m.sub.3-1:0]×B0[m.sub.4-1:0], wherein m.sub.1≥2N×m.sub.3, m.sub.2≥2N×m.sub.4, N is a positive integer, the multi-mode fusion multiplier comprises P precoders, Q groups of fusion coders, and a compressor, and m.sub.1, m.sub.2, m.sub.3, m.sub.4, P, and Q are integers greater than 1; the P precoders are configured to precode a first value based on a single-multiplication indication signal or a multi-multiplication indication signal, to provide a precoding result, wherein the first value is A[m.sub.1-1:0] when the single-multiplication indication signal indicates that the single-multiplication operation is performed, or the first value comprises 2N pieces of A0[m.sub.3-1:0] when the multi-multiplication indication signal indicates that the accumulated sum operation is performed, wherein the 2N pieces of A0[m.sub.3-1:0] are arranged in a sequence from a low digit weight to a high digit weight; the Q groups of fusion coders are configured to code the precoding result and a second value, to provide a plurality of partial products, wherein the second value is B[m.sub.2-1:0] when the single-multiplication indication signal indicates that the single-multiplication operation is performed, or the second value comprises 2N pieces of B0[m.sub.4-1:0] when the multi-multiplication indication signal indicates that the accumulated sum operation is performed, wherein the 2N pieces of B0[m.sub.4-1:0] are arranged in a sequence from a high digit weight to a low digit weight; and the compressor is configured to compress the plurality of partial products, to provide two accumulated values, wherein a sum of the two accumulated values is a result of the single-multiplication operation or the accumulated sum operation.
2. The multi-mode fusion multiplier according to claim 1, wherein when m.sub.1>2N×m.sub.3, first (m.sub.1-2N×m.sub.3) high digit weights in the first value comprise sign bits; and/or when m.sub.2>2N×m.sub.4, last (m.sub.2-2N×m.sub.4) low digit weights in the second value comprise invalid bits.
3. The multi-mode fusion multiplier according to claim 1, wherein the P precoders comprise an i.sup.th precoder, configured to: determine an group of selection signals, an i.sup.th group of single-multiplication selection signals, a single-multiplication control signal SCi, and a first multi-multiplication control signal MCi in the precoding result based on the single-multiplication indication signal, the multi-multiplication indication signal, and at least two bits in the first value when i is an even number and 0≤i≤N×m.sub.3−1; or determine an i.sup.th group of selection signals, an i.sup.th group of single-multiplication selection signals, a single-multiplication control signal (SCi), a second multi-multiplication control signal (MCNi), and a control signal (Si) in the precoding result based on the single-multiplication indication signal, the multi-multiplication indication signal, and at least two bits in the first value when i is an even number and N×m.sub.3≤i≤m.sub.1−1, wherein the i.sup.th group of selection signals comprises a first selection signal M1Mi and a second selection signal M2Mi, and the i.sup.th group of single-multiplication selection signals comprises a first single-multiplication selection signal SM1Mi and a second single-multiplication selection signal SM2Mi.
4. The multi-mode fusion multiplier according to claim 3, wherein when i is equal to 0, the at least two bits comprise a first bit [0] and a second bit all in the first value; and the 0.sup.th precoder is configured to perform coding operations comprising: setting the first selection signal M1M0 to the first bit [0]; setting the second selection signal M2M0 to 1 when the first bit a[0] is 0 and the second bit a[1] is 1, or setting the second selection signal M2M0 to 0 when the first bit a[0] is not 0 or the second bit a[1] is not 1; setting the single-multiplication control signal SC0 to the second bit all when the single-multiplication indication signal is 1, or setting the single-multiplication control signal SC0 to 0 when the single-multiplication indication signal is 0; setting the first multi-multiplication control signal MC0 to the second bit [1] when the multi-multiplication indication signal is 1, or setting the first multi-multiplication control signal MC0 to 0 when the multi-multiplication indication signal is 0; and setting the first single-multiplication selection signal SM1M0 to the first bit a[1] and setting the second single-multiplication selection signal SM2M0 to the second selection signal M2M0 when the single-multiplication indication signal is 1, or setting both the first single-multiplication selection signal SM1M0 and the second single-multiplication selection signal SM2M0 to 0 when the single-multiplication indication signal is 0.
5. The multi-mode fusion multiplier according to claim 3, wherein when 0<i≤N×m.sub.3−1, the at least two bits comprise a first bit a[i−1], a second bit a[i], and a third bit a[i+1] in the first value; and the i.sup.th precoder is configured to perform coding operations comprising: setting the first selection signal M1Mi to 1 when the first bit a[i−1] is not equal to the second bit a[i], or setting the first selection signal M1Mi to 0 when the first bit a[i−1] is equal to the second bit a[i]; setting the second selection signal M2Mi to 1 when the first bit a[i−1] is equal to the second bit a[i] and the second bit a[i] is not equal to the third bit a[i+1], or setting the second selection signal M2Mi to 0 when the first bit a[i−1] is not equal to the second bit a[i] or the second bit a[i] is equal to the third bit a[i+1]; setting the single-multiplication control signal SCi to the third bit a[i+1] when the single-multiplication indication signal is 1, or setting the single-multiplication control signal SCi to 0 when the single-multiplication indication signal is 0; setting the first multi-multiplication control signal MCi to the third bit a[i+1] when the multi-multiplication indication signal is 1, or setting the first multi-multiplication control signal MCi to 0 when the multi-multiplication indication signal is 0; and setting the first single-multiplication selection signal SM1Mi to the first selection signal M1Mi and setting the second single-multiplication selection signal SM2Mi to the second selection signal M2Mi when the single-multiplication indication signal is 1, or setting both the first single-multiplication selection signal SM1Mi and the second single-multiplication selection signal SM2Mi to 0 when the single-multiplication indication signal is 0.
6. The multi-mode fusion multiplier according to claim 3, wherein when i is equal to N×m.sub.3, the at least two bits comprise a first bit a[i−1], a second bit a[i], and a third bit a[i+1] in the first value; and the (N×m.sub.3).sup.th precoder is configured to perform coding operations comprising: setting a fourth bit to the first bit a[i−1] when the single-multiplication indication signal is 1, or setting a fourth bit to 0 when the single-multiplication indication signal is 0; setting the first selection signal M1Mi to 1 when the fourth bit is not equal to the second bit a[i], or setting the first selection signal M1Mi to 0 when the fourth bit is equal to the second bit a[i]; setting the second selection signal M2Mi to 1 when the fourth bit is equal to the second bit a[i] and the second bit a[i] is not equal to the third bit a[i+1], or setting the second selection signal M2Mi to 0 when the fourth bit is not equal to the second bit a[i] or the second bit a[i] is equal to the third bit a[i+1]; setting the single-multiplication control signal SCi to the third bit a[i+1] when the single-multiplication indication signal is 1, or setting the single-multiplication control signal SCi to 0 when the single-multiplication indication signal is 0; setting the second multi-multiplication control signal MCNi to 0 when the multi-multiplication indication signal is equal to the third bit a[i+1], or setting the second multi-multiplication control signal MCNi to 1 when the multi-multiplication indication signal is not equal to the third bit a[i+1]; setting the control signal Si to the third bit a[i+1]; and setting the first single-multiplication selection signal SM1Mi to the first selection signal M1Mi and setting the second single-multiplication selection signal SM2Mi to the second selection signal M2Mi when the single-multiplication indication signal is 1, or setting both the first single-multiplication selection signal SM1Mi and the second single-multiplication selection signal SM2Mi to 0 when the single-multiplication indication signal is 0.
7. The multi-mode fusion multiplier according to claim 3, wherein when N×m.sub.3<i≤m.sub.1−1, the at least two bits comprise a first bit a[i−1], a second bit a[i], and a third bit a[i+1]; and the i.sup.th precoder is configured to perform coding operations comprising: setting the first selection signal M1Mi to 1 when the first bit a[i−1] is not equal to the second bit a[i], or setting the first selection signal M1Mi to 0 when the first bit a[i−1] is equal to the second bit a[i]; setting the second selection signal M2Mi to 1 when the first bit a[i−1] is equal to the second bit a[i] and the second bit a[i] is not equal to the third bit a[i+1], or setting the second selection signal M2Mi to 0 when the first bit a[i−1] is not equal to the second bit a[i] or the second bit a[i] is equal to the third bit a[i+1]; setting the single-multiplication control signal SCi to the third bit a[i+1] when the single-multiplication indication signal is 1, or setting the single-multiplication control signal SCi to 0 when the single-multiplication indication signal is 0; setting the second multi-multiplication control signal MCNi to 0 when the multi- multiplication indication signal is equal to the third bit a[i+1], or setting the second multi-multiplication control signal MCNi to 1 when the multi-multiplication indication signal is not equal to the third bit a[i+1]; setting the first single-multiplication selection signal SM1Mi to the first selection signal M1Mi and setting the second single-multiplication selection signal SM2Mi to the second selection signal M2Mi when the single-multiplication indication signal is 1, or setting both the first single-multiplication selection signal SM1Mi and the second single-multiplication selection signal SM2Mi to 0 when the single-multiplication indication signal is 0; and setting the control signal Si to the third bit a[i+1].
8. The multi-mode fusion multiplier according to claim 3, wherein the Q groups of fusion coders comprise a first coder configured to perform coding operation comprising: setting a partial product p(i, k) to an inversion of the single-multiplication control signal SCi when both the first single-multiplication selection signal SM1Mi and a first bit KM in the second value are 1 or both the second single-multiplication selection signal SM2Mi and a second bit b[k−1] in the second value are 1; or setting a partial product p(i, k) to the single-multiplication control signal SCi when the first single-multiplication selection signal SM1Mi and a first bit KM in the second value are not both 1 and the second single-multiplication selection signal SM2Mi and a second bit b[k−1]in the second value are not both 1.
9. The multi-mode fusion multiplier according to claim 3, wherein the Q groups of fusion coders further comprise a second coder configured to perform coding operations comprising: setting a first intermediate item to 1 when both the multi-multiplication indication signal and the first bit b[k−1] in the second value are 1 or both the single-multiplication indication signal and the second bit KM in the second value are 1, or setting a first intermediate item to 0 when the multi-multiplication indication signal and the first bit b[k−1] in the second value are not both 1 and the single-multiplication indication signal and the second bit b[k] in the second value are not both 1; setting a second intermediate item to 1 when both the first intermediate item and the first selection signal M1Mi are 1 or both the second selection signal M2Mi and the first bit b[k−1] are 1, or setting a second intermediate item to 0 when the first intermediate item and the first selection signal M1Mi are not both 1 and the second selection signal M2Mi and the first bit b[k−1] are not both 1; and setting an inversion of the second multi-multiplication control signal MCNi to a partial product p(i, k) when the second intermediate item is 1, or setting the second multi-multiplication control signal MCNi to a partial product p(i, k) when the second intermediate item is 0.
10. The multi-mode fusion multiplier according to claim 3, wherein the Q groups of fusion coders further comprise a third coder configured to perform coding operation: setting a partial product p(i, k) to an inversion of the single-multiplication control signal SCi when both the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are 1; or setting a partial product p(i, k) to the single-multiplication control signal SCi when the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are not both 1.
11. The multi-mode fusion multiplier according to claim 3, wherein the Q groups of fusion coders further comprise a fourth coder configured to perform coding operations comprising: setting a first intermediate item to 1 when both the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are 1 or both the second single-multiplication selection signal SM2Mi and the second bit b[k−1] in the second value are 1, or setting a first intermediate item to 0 when the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are not both 1 and the second single-multiplication selection signal SM2Mi and the second bit b[k−1] in the second value are not both 1; setting a second intermediate item to an inversion of the single-multiplication control signal SCi when the first intermediate item is 1, or setting a second intermediate item to the single-multiplication control signal SCi when the first intermediate item is 0; and setting a partial product p(i, k) to 1 when the multi-multiplication indication signal is 1, or setting a partial product p(i, k) to the second intermediate item when the multi-multiplication indication signal is 0.
12. The multi-mode fusion multiplier according to claim 3, wherein the Q groups of fusion coders further comprise a fifth coder configured to perform coding operation comprising: setting a partial product p(i, k) to the single-multiplication control signal SCi when both the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are 1 or both the second single-multiplication selection signal SM2Mi and the first bit b[k] in the second value are 1; or setting a partial product p(i, k) to an inversion of the single-multiplication control signal SCi when the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are not both 1 and the second single-multiplication selection signal SM2Mi and the first bit b[k] in the second value are not both 1.
13. The multi-mode fusion multiplier according to claim 3, wherein the Q groups of fusion coders further comprise a sixth coder configured to perform coding operation comprising: setting a partial product p(i, k) to an inversion of the control signal Si when both the first selection signal M1Mi and the first bit b[k] in the second value are 1 or both the second selection signal M2Mi and the first bit b[k] in the second value are 1; or setting a partial product p(i, k) to the control signal Si when the first selection signal M1Mi and the first bit b[k] in the second value are not both 1 and the second selection signal M2Mi and the first bit b[k] in the second value are not both 1.
14. The multi-mode fusion multiplier according to claim 3, wherein the Q groups of fusion coders further comprise a seventh coder configured to perform coding operations comprising: setting a first intermediate item to 1 when both the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are 1 or both the second single-multiplication selection signal SM2Mi and the first bit b[k] in the second value are 1, or setting a first intermediate item to 0 when the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are not both 1 and the second single-multiplication selection signal SM2Mi and the first bit KM in the second value are not both 1; setting a second intermediate item to an inversion of the single-multiplication control signal SCi when the first intermediate item is 1, or setting a second intermediate item to the single-multiplication control signal SCi when the first intermediate item is 0; and setting a partial product p(i, k) to the second intermediate item when the single-multiplication indication signal is 1, or setting a partial product p(i, k) to 0 when the single-multiplication indication signal is 0.
15. The multi-mode fusion multiplier according to claim 3, wherein the Q groups of fusion coders further comprise an eighth coder configured to perform coding operations comprising: setting a first intermediate item to 1 when both the first single-multiplication selection signal SM1Mi and the first bit KM in the second value are 1 or both the second single-multiplication selection signal SM2Mi and the first bit KM in the second value are 1, or setting a first intermediate item to 0 when the first single-multiplication selection signal SM1Mi and the first bit KM in the second value are not both 1 and the second single-multiplication selection signal SM2Mi and the first bit KM in the second value are not both 1; setting a second intermediate item to an inversion of the single-multiplication control signal SCi when the first intermediate item is 1, or setting a second intermediate item to the single-multiplication control signal SCi when the first intermediate item is 0; and setting a partial product p(i, k) to the second intermediate item when the single-multiplication indication signal is 1, or setting a partial product p(i, k) to an inversion of the second intermediate item when the single-multiplication indication signal is 0.
16. The multi-mode fusion multiplier according to claim 3, wherein the Q groups of fusion coders further comprise a ninth coder configured to perform coding operations comprising: setting a first intermediate item to 1 when both the first single-multiplication selection signal SM1Mi and the first bit KM in the second value are 1 or both the second single-multiplication selection signal SM2Mi and the second bit b[k−1] in the second value are 1, or setting a first intermediate item to 0 when the first single-multiplication selection signal SM1Mi and the first bit KM in the second value are not both 1 and the second single-multiplication selection signal SM2Mi and the second bit b[k−1] in the second value are not both 1; setting a second intermediate item to an inversion of the single-multiplication control signal SCi when the first intermediate item is 1, or setting a second intermediate item to the single-multiplication control signal SCi when the first intermediate item is 0; and setting a partial product p(i, k) to 1 when the first multi-multiplication control signal MCi is 1, or setting a partial product p(i, k) to the second intermediate item when the first multi-multiplication control signal MCi is 0.
17. The multi-mode fusion multiplier according to claim 3, wherein the Q groups of fusion coders further comprise a tenth coder configured to perform coding operations comprising: setting a first intermediate item to 1 when both the multi-multiplication indication signal and the first bit b[k−1] in the second value are 1 or both the single-multiplication indication signal and the second bit KM in the second value are 1, or setting a first intermediate item to 0 when the multi-multiplication indication signal and the first bit b[k−1] in the second value are not both 1 and the single-multiplication indication signal and the second bit KM in the second value are not both 1; setting a second intermediate item to 1 when both the first intermediate item and the first selection signal M1Mi are 1 or both the second selection signal M2Mi and the first bit b[k−1] are 1, or setting a second intermediate item to 0 when the first intermediate item and the first selection signal M1Mi are not both 1 and the second selection signal M2Mi and the first bit b[k−1] are not both 1; setting a third intermediate item to an inversion of the second multi-multiplication control signal MCNi when the second intermediate item is 1, or setting a third intermediate item to the second multi-multiplication control signal MCNi when the second intermediate item is 0; and setting a partial product p(i, k) to an inversion of the third intermediate item when the multi-multiplication indication signal is 1, or setting a partial product p(i, k) to the third intermediate item when the multi-multiplication indication signal is 0.
18. A method performed by a multi-mode fusion multiplier comprising P precoders, Q groups of fusion coders, and a compressor, the method comprising: receiving A[m1-1:0] and B[m.sub.2-1:0] as inputs to a binary single-multiplication operation A[m.sub.1-1:0]×B[m.sub.2-1:0] or an accumulated sum operation of 2N binary multiplications A0[m.sub.3−1:0]×B0[m.sub.4-1:0], wherein m.sub.1≥2N×m.sub.3, m.sub.2≥2N×m.sub.4, N is a positive integer, and m.sub.1, m.sub.2, m.sub.3, m.sub.4, P, and Q are integers greater than 1; precoding, by P precoders of the multi-mode fusion multiplier, a first value based on a single-multiplication indication signal or a multi-multiplication indication signal, to provide a precoding result, wherein the first value is A[m.sub.1-1:0] when the single-multiplication indication signal indicates that the single-multiplication operation is performed, or the first value comprises 2N pieces of A0[m.sub.3-1:0] when the multi-multiplication indication signal indicates that the accumulated sum operation is performed, wherein the 2N pieces of A0[m.sub.3-1:0] are arranged in a sequence from a low digit weight to a high digit weight; coding, by Q groups of fusion coders of the multi-mode fusion multiplier, the precoding result and a second value, to provide a plurality of partial products, wherein the second value is B[m.sub.2-1:0] when the single-multiplication indication signal indicates that the single-multiplication operation is performed, or the second value comprises 2N pieces of B0[m.sub.4-1:0] when the multi-multiplication indication signal indicates that the accumulated sum operation is performed, wherein the 2N pieces of B0[m.sub.4-1:0] are arranged in a sequence from a high digit weight to a low digit weight; and compress, by the compressor, the plurality of partial products, to provide two accumulated values, wherein a sum of the two accumulated values is a result of the single-multiplication operation or the accumulated sum operation.
Description
BRIEF DESCRIPTION OF DRAWINGS
[0043]
[0044]
[0045]
[0046]
[0047]
[0048]
[0049]
[0050]
[0051]
[0052]
[0053]
[0054]
[0055]
[0056]
[0057]
DESCRIPTION OF EMBODIMENTS
[0058] In this application, “at least one” means one or more, and “a plurality of” means two or more. The term “and/or” describes an association relationship between associated objects and indicates that three relationships may exist. For example, A and/or B may represent the following cases: Only A exists, both A and B exist, and only B exists, where A and B may be singular or plural. “At least one of the following items (pieces)” or a similar expression thereof means any combination of these items, including any combination of singular items (pieces) or plural items (pieces). For example, at least one (piece) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c may be singular or plural. In addition, in embodiments of this application, the words such as “first” and “second” are used to distinguish between objects whose names or functions are similar. A person skilled in the art may understand that the words such as “first” and “second” do not limit a quantity or an execution sequence. The term “couple” is used to indicate an electrical connection, including a direct connection through a wire or a connection end or an indirect connection through another component. Therefore, “couple” should be considered as a generalized electronic communication connection.
[0059]
[0060] The processor 302 includes but is not limited to a central processing unit (CPU), a network processing unit (NPU), a graphics processing unit (GPU), a digital signal processor (DSP), a general-purpose processor, or the like. The processor 302 includes one or more multipliers, for example, includes a multiplier array. The multiplier is a component that implements a multiplication operation in the processor 302.
[0061] The bus 304 may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, the bus is represented by using only one thick line in
[0062] To further describe the technical solutions,
[0063] The P precoders 401 are configured to precode a first value based on a single-multiplication indication signal or a multi-multiplication indication signal, to obtain a precoding result. The first value is A[m.sub.1-1:0] when the single-multiplication indication signal indicates that the single-multiplication operation is performed, or the first value includes 2N pieces of A0[m.sub.3-1:0] when the multi-multiplication indication signal indicates that the accumulated sum operation is performed, where the 2N pieces of A0[m.sub.3-1:0] are arranged in a sequence from a low digit weight to a high digit weight.
[0064] The single-multiplication indication signal may be used to indicate whether the multiplier performs the single-multiplication operation A[m.sub.1-1:0]×B[m.sub.2-1:0], and the single-multiplication indication signal may be represented by a 1-bit binary number. For example, when the single-multiplication indication signal is 1, the single-multiplication indication signal may be used to indicate that the multiplier performs the single-multiplication operation. When the single-multiplication indication signal is 0, the single-multiplication indication signal may be used to indicate that the multiplier does not perform the single-multiplication operation. The multi-multiplication indication signal may be used to indicate whether the multiplier performs the accumulated sum operation of the 2N binary multiplications A0[m.sub.3-1:0]×B0[m.sub.4-1:0], and the multi-multiplication indication signal may be represented by a 1-bit binary number. For example, when the multi-multiplication indication signal is 1, the multi-multiplication indication signal may be used to indicate that the multiplier performs the accumulated sum operation. When the multi-multiplication indication signal is 0, the multi-multiplication indication signal may be used to indicate that the multiplier does not perform the accumulated sum operation.
[0065] In addition, when the multi-multiplication indication signal indicates that the accumulated sum operation is performed, the 2N pieces of A0[m.sub.3-1:0] included in the first value are arranged in the sequence from the low digit weight to the high digit weight. For example, when N=2, the 2N pieces of A0[m.sub.3-1:0] are four pieces of A0[m.sub.3-1:0]. If the four pieces of A0[m.sub.3-1:0] are respectively represented as A1[m.sub.3-1:0], A2[m.sub.3-1:0], A3[.sub.3-1:0], and A4[m.sub.3-1:0], the first value is obtained by arranging the four pieces of A0[m.sub.3-1:0] in a sequence from a low digit weight to a high digit weight. If the first value is a[4m.sub.3-1:0], A1[n.sub.3-1:0] is mapped to the (m.sub.3−1).sup.th digit weight to the 0.sup.th digit weight (that is, a[m.sub.3]-1:01) in the first value, A2[m.sub.3-1:0] is mapped to the (2m.sub.3−1).sup.th digit weight to the (m.sub.3).sup.th digit weight (that is, a[2m.sub.3-1:m.sub.3]) in the first value, A3[m.sub.3-1:0] is mapped to the (3m.sub.3−1).sup.th digit weight to the (2m.sub.3).sup.th digit weight (that is, a[3m.sub.3-1:2m.sub.3]) in the first value, and A4[m.sub.3-1:0] is mapped to the (4m.sub.3−1).sup.th digit weight to the (3m.sub.3).sup.th digit weight (that is, a[4m.sub.3-1:3m.sub.3]) in the first value.
[0066] Optionally, when m.sub.1 is equal to 2N×m.sub.3, a value obtained by arranging the 2N pieces of A0[m.sub.3-1:0] in the sequence from the low digit weight to the high digit weight is the first value used when the multiplier performs the accumulated sum operation. When m.sub.1 is greater than 2N×m.sub.3, a value obtained by arranging the 2N pieces of A0[m.sub.3-1:0] in the sequence from the low digit weight to the high digit weight is a value from the 0.sup.th digit weight to the (2N×m.sub.3-1).sup.th digit weight in the first value used when the multiplier performs the accumulated sum operation, and the (2N×m.sub.3).sup.th digit weight to the (m.sub.1−1).sup.th digit weight in the first value are filled with sign bits, that is, first (m.sub.1-2N×m.sub.3) high digit weights in the first value are filled with sign bits. This may also be understood as that a value obtained after the value obtained through arrangement is filled with sign bits is the first value, and a quantity of digit weights of the value obtained after filling is equal to m.sub.1. It should be noted that, when the single-multiplication operation is performed, a filled sign bit is a sign bit of A[m.sub.11:0]. If the sign bit of A[m.sub.1-1:0] is 0, the filled sign bit is also 0. If the sign bit of A[m.sub.3-1:0] is 1, the filled sign bit is also 1. When the accumulated sum operation of the plurality of multiplications is performed, a filled sign bit is a sign bit of A0[m.sub.3-1:0]. If the sign bit of A0[m.sub.3-1:0] is 0, the filled sign bit is also 0. If the sign bit of A0[m.sub.3-1:0] is 1, the filled sign bit is also 1.
[0067] Specifically, when the single-multiplication indication signal indicates that the single-multiplication operation is performed, the P precoders 401 are configured to precode the first value A[m.sub.1-1:0] based on the single-multiplication indication signal or the multi-multiplication indication signal. When the multi-multiplication indication signal indicates that the accumulated sum operation is performed, the P precoders 401 are configured to precode, based on the single-multiplication indication signal or the multi-multiplication indication signal, the first value obtained after the 2N pieces of A0[m.sub.3-1:0] are arranged or arranged and filled.
[0068] The Q groups of fusion coders 402 are configured to code the precoding result and a second value, to obtain a plurality of partial products. The second value is B[m.sub.2-1:0] when the single-multiplication indication signal indicates that the single-multiplication operation is performed, or the second value includes 2N pieces of B0[m.sub.4−1:0] when the multi-multiplication indication signal indicates that the accumulated sum operation is performed, where the 2N pieces of B0[m.sub.4−1:0] are arranged in a sequence from a high digit weight to a low digit weight.
[0069] When the multi-multiplication indication signal indicates that the accumulated sum operation is performed, the 2N pieces of B0[m.sub.4-1:0] included in the second value are arranged in the sequence from the high digit weight to the low digit weight. For example, when N=2, the 2N pieces of B0[m.sub.4-1:0] are four pieces of B0[m.sub.4- 1:0]. If the four pieces of B0[m.sub.4-1:0] are respectively represented as B1[m.sub.4-1:0], B2[m.sub.4-1:0], B3[m.sub.4-1:0], and B4[m.sub.4-1:0], the second value is obtained by arranging the four pieces of B0[m.sub.4-1:0] in a sequence from a high digit weight to a low digit weight. If the second value is b[4m.sub.4-1:0], B1[m.sub.4-1:0] is mapped to the (4m.sub.4−1).sup.th digit weight to the (3m.sub.4).sup.th digit weight (that is, b[4m.sub.4-1:3m.sub.4]) in the second value, B2[m.sub.4-1:0] is mapped to the (3m.sub.4−1).sup.th digit weight to the (2m.sub.4).sup.th digit weight (that is, b[3m.sub.4-1:2m.sub.4]) in the second value, B3[m.sub.4-1:0] is mapped to the (2m.sub.4−1).sup.th digit weight to the (m.sub.4).sup.th digit weight (that is, b[2m.sub.4−1:m.sub.4]) in the second value, and B4[m.sub.4-1:0] is mapped to the (m.sub.4-1).sup.th digit weight to the 0.sup.th digit weight (that is, b.sub.4-1:01) in the second value.
[0070] Optionally, when m.sub.2 is equal to 2N×m.sub.4, a value obtained by arranging the 2N pieces of B0[m.sub.4-1:0] in the sequence from the high digit weight to the low digit weight is the second value used when the multiplier performs the accumulated sum operation. When m.sub.2 is greater than 2N×m.sub.4, a value obtained by arranging the 2N pieces of B0[m.sub.4-1:0] in the sequence from the high digit weight to the low digit weight is a value from the (m.sub.2-2N×m.sub.4).sup.th digit weight to the (m.sub.2-1).sup.th digit weight in the second value used when the multiplier performs the accumulated sum operation, and the 0.sup.th digit weight to the (m.sub.22N×m4−1).sup.th digit weight in the second value are filled with invalid bits (for example, filled with 0), that is, last (m.sub.2-2N×m.sub.4) low digit weights in the second value are filled with invalid bits. This may also be understood as that a value obtained after the value obtained through arrangement is filled with invalid bits is the second value, and a quantity of digit weights of the value obtained after filling is equal to m.sub.2.
[0071] Specifically, when the single-multiplication indication signal indicates that the single-multiplication operation is performed, the Q groups of fusion coders 402 are configured to code the second value B[m.sub.2-1:0] and a precoding result that is output by the P precoders 401 by precoding A[m.sub.1-1:0]. When the multi-multiplication indication signal indicates that the accumulated sum operation is performed, the Q groups of fusion coders 402 are configured to code the second value obtained after the 2N pieces of B0[m.sub.4-1:0] are arranged or arranged and filled and a precoding result that is output by the P precoders 401 by precoding the first value obtained after the 2N pieces of A0[m.sub.3-1:0] are arranged or arranged and filled.
[0072] The compressor 403 is configured to compress the plurality of partial products that are output by the Q groups of fusion coders, to obtain two accumulated values, and a sum of the two accumulated values is a result of the single-multiplication operation or the accumulated sum operation.
[0073] The compressor 403 may include W layers of compressors, and W is a positive integer. When W is equal to 1, the compressor 403 includes a compressor at a first layer. The compressor at the first layer is configured to successively compress all digit weights in an arrangement array of the plurality of partial products in a sequence from a low digit weight to a high digit weight, until each digit weight corresponds to fewer than three remaining bits, to obtain a first compression array that includes two rows. Each row corresponds to one accumulated value. When W is an integer greater than 1, the compressor 403 includes a compressor at a first layer and a compressor at each layer up to and including a compressor at a W.sup.th layer. The compressor at the first layer is configured to successively compress all digit weights in an arrangement array of the plurality of partial products in a sequence from a low digit weight to a high digit weight, until each digit weight corresponds to fewer than three remaining bits, to obtain a first compression array. A compressor at a j.sup.th layer is configured to successively compress all digit weights in a (j−1).sup.th compression array in a sequence from a low digit weight to a high digit weight, until each digit weight corresponds to fewer than three remaining bits, to obtain a j.sup.th compression array. A value range of j is 2 to W, a W.sup.th compression array includes two rows, and each row corresponds to one accumulated value.
[0074] In addition, compression performed by a compressor at each layer on each digit weight is performed for three bits on the digit weight, and neither of a carry output bit and a current summation bit that are obtained through compression by the compressor at the layer is compressed.
[0075] In the arrangement array of the plurality of partial products, each row includes one partial product item, and each column includes a plurality of bits corresponding to a same digit weight in the plurality of partial products. One partial product item includes a plurality of partial products that correspond to a same precoder and that are output by a group of fusion coders.
[0076] The adder 404 is configured to: receive the two accumulated values, and calculate a sum of the two accumulated values to obtain the result of the single-multiplication operation or the accumulated sum operation. After the compressor 403 compresses the plurality of partial products to obtain the two accumulated values, the compressor 403 may send the two accumulated values to the adder 404. When receiving the two accumulated values, the adder 404 may obtain a product of the first value and the second value by calculating the sum of the two accumulated values. In this way, when the multiplier performs the single-multiplication operation, a result that is output by the adder 404 is a result of the single-multiplication operation A[m.sub.1-1:0]×B[m.sub.2-1:0]. When the multiplier performs the accumulated sum operation, a result that is output by the adder 404 is a result of the accumulated sum operation of the 2N binary multiplications A0[m.sub.3-1:0]×B0[m.sub.4-1:0].
[0077] In a possible embodiment, if N=1, m.sub.1=2m.sub.3+I (I is a non-negative integer), and m.sub.2=2m.sub.4+J (J is a non-negative integer), the multiplier may be referred to as a single-double fusion multiplier with a single-multiplication mode and a double-multiplication mode. In the single-multiplication mode, the multiplier may be configured to implement a single-multiplication operation of m.sub.1bits×m.sub.2 bits (that is, A[m.sub.1-1:0]×B[m.sub.2-1:0]). In the double-multiplication mode, the multiplier may be configured to implement an accumulated sum operation of two binary multiplications m.sub.3 bits×m.sub.4 bits (that is, two pieces of A0[m.sub.3-1:0]×B0[m.sub.4-1:0]). For ease of description, in the following, the two pieces of A0[m.sub.3-1:0] may be represented as A1[m.sub.3-1:0] and A2[m.sub.3-1:0], and the two pieces of B0[m.sub.4-1:0] may be represented as B1[m.sub.4-1:0] and B2[m.sub.4-1:0].
[0078] As shown in
[0079] In a possible embodiment, if N=2, m.sub.1=4m.sub.3+I (I is a non-negative integer), and m.sub.2=4m.sub.4+J (J is a non-negative integer), the multiplier may be referred to as a single-four fusion multiplier with a single-multiplication mode and a four-multiplication mode. In the single-multiplication mode, the multiplier may be configured to implement a single-multiplication operation of m.sub.1 bits×m.sub.2 bits (that is, A[m.sub.1-1:0]×B[m.sub.2-1:0]). In the four-multiplication mode, the multiplier may be configured to implement an accumulated sum operation of four binary multiplications m.sub.3 bits×m.sub.4 bits (that is, four pieces of A0[m.sub.3-1:0]×B0[m.sub.4-1:0]). For ease of description, in the following, the four pieces of A0[m.sub.3-1:0] may be represented as A1[m.sub.3-1:0], A2[m.sub.3-1:0], A3[m.sub.3-1:0], and A4[m.sub.3-1:0], and the four pieces of B0[m.sub.4-1:0] may be represented as B1[m.sub.4-1:0], B2[m.sub.4-1:0], B3[m.sub.4-1:0], and B4[m.sub.4-1:0].
[0080] As shown in
[0081] In the single-double fusion multiplier shown in
[0082] Further, the P precoders 401 include an i.sup.th precoder, configured to: determine an i.sup.th group of selection signals, an i.sup.th group of single-multiplication selection signals, a single-multiplication control signal SCi, and a first multi-multiplication control signal MCi in the precoder result based on the single-multiplication indication signal, the multi-multiplication indication signal, and at least two bits in the first value when 0≤i≤N×m.sub.3, where ≤ represents less than or equal to, and i is an even number; or determine an ith group of selection signals, an i.sup.th group of single-multiplication selection signals, a single-multiplication control signal SCi, a second multi-multiplication control signal MCNi, and a control signal Si in the precoder result based on the single-multiplication indication signal, the multi-multiplication indication signal, and at least two bits in the first value when N×m.sub.3≤i≤m.sub.1−1, where i is an even number.
[0083] The group of selection signals includes a first selection signal M1Mi and a second selection signal M2Mi, and the i.sup.th group of single-multiplication selection signals includes a first single-multiplication selection signal SM1Mi and a second single-multiplication selection signal SM2Mi. In the following, the single-multiplication indication signal is represented as an SMI, and the multi-multiplication indication signal is represented as an MMI.
[0084] In addition, the P precoders 401 may include a plurality of different types of precoders. The following separately describes logical functions and circuit structures of the plurality of different types of precoders in detail.
[0085] As shown in
[0086] Specifically, the first-type precoder is configured to perform the following coding operations: setting the first selection signal M1M0 to the first bit a[0]; setting the second selection signal M2M0 to 1 when the first bit a[0] is 0 and the second bit a[1] is 1; or setting the second selection signal M2M0 to 0 when the first bit a[0] is not 0 or the second bit a[1] is not 1; setting the single-multiplication control signal SC0 to the second bit a[1] when the single-multiplication indication signal SMI is 1; or setting the single-multiplication control signal SCO to 0 when the single-multiplication indication signal SMI is 0; setting the first multi-multiplication control signal MCO to the second bit a[1] when the multi-multiplication indication signal MMI is 1; or setting the first multi-multiplication control signal MC0 to 0 when the multi-multiplication indication signal MMI is 0; and setting the first single-multiplication selection signal SM1M0 to the first bit a[0] and setting the second single-multiplication selection signal SM2M0 to the second selection signal M2M0 when the single-multiplication indication signal SMI is 1; or setting both the first single-multiplication selection signal SM1M0 and the second single-multiplication selection signal SM2M0 to 0 when the single-multiplication indication signal SMI is 0.
[0087] In a possible implementation, as shown in
[0088] AND gate is configured to receive the single-multiplication indication signal SMI, an output end of the second AND gate is configured to output the single-multiplication control signal SC0, the other input end of the third AND gate is configured to receive the multi-multiplication indication signal MMI, and an output end of the third AND gate is configured to output the first multi-multiplication control signal MC0. One input end of the fourth AND gate and one input end of the fifth AND gate in the five AND gates are configured to receive the single-multiplication indication signal SMI, the other input end of the fourth AND gate is configured to receive the first bit a[0], an output end of the fourth AND gate is configured to output the first single-multiplication selection signal SM1M0, the other input end of the fifth AND gate is coupled to the output end of the first AND gate, and an output end of the fifth AND gate is configured to output the second single-multiplication selection signal SM2M0.
[0089] As shown in
[0090] Specifically, the second-type precoder is configured to perform the following coding operations: setting the first selection signal M1Mi to 1 when the first bit a[i−1] is not equal to the second bit a[i]; or setting the first selection signal M1Mi to 0 when the first bit a[i−1] is equal to the second bit a[i]; setting the second selection signal M2Mi to 1 when the first bit a[i−1] is equal to the second bit a[i] and the second bit a[i] is not equal to the third bit a[i+1]; or setting the second selection signal M2Mi to 0 when the first bit a[i−1] is not equal to the second bit a[i] or the second bit a[i] is equal to the third bit a[i+1]; setting the single-multiplication control signal SCi to the third bit a[i+1] when the single-multiplication indication signal SMI is 1; or setting the single-multiplication control signal SCi to 0 when the single-multiplication indication signal SMI is 0; setting the first multi-multiplication control signal MCi to the third bit a[i+1] when the multi-multiplication indication signal MMI is 1; or setting the first multi-multiplication control signal MCi to 0 when the multi-multiplication indication signal MMI is 0; and setting the first single-multiplication selection signal SM1Mi to the first selection signal M1Mi and setting the second single-multiplication selection signal SM2Mi to the second selection signal M2Mi when the single-multiplication indication signal SMI is 1; or setting both the first single-multiplication selection signal SM1Mi and the second single-multiplication selection signal SM2Mi to 0 when the single-multiplication indication signal SMI is 0.
[0091] In a possible implementation, as shown in
[0092] As shown in
[0093] The third-type precoder is configured to perform the following coding operations: setting a fourth bit c[1] to the first bit a[i−1] when the single-multiplication indication signal SMI is 1; or setting a fourth bit c[1] to 0 when the single-multiplication indication signal SMI is 0; setting the first selection signal M1Mi to 1 when the fourth bit c[1] is not equal to the second bit a[i]; or setting the first selection signal M1Mi to 0 when the fourth bit c[1] is equal to the second bit a[i]; setting the second selection signal M2Mi to 1 when the fourth bit is equal to the second bit a[i] and the second bit a[i] is not equal to the third bit a[i+1]; or setting the second selection signal M2Mi to 0 when the fourth bit is not equal to the second bit a[i] or the second bit a[i] is equal to the third bit a[i+1]; setting the single-multiplication control signal SCi to the third bit a[i +1] when the single-multiplication indication signal SMI is 1; or setting the single-multiplication control signal SCi to 0 when the single-multiplication indication signal SMI is 0; setting the second multi-multiplication control signal MCNi to 0 when the multi-multiplication indication signal MMI is equal to the third bit a[i+1]; or setting the second multi-multiplication control signal MCNi to 1 when the multi-multiplication indication signal MMI is not equal to the third bit a[i+1]; setting the first single-multiplication selection signal SM1Mi to the first selection signal M1Mi and setting the second single-multiplication selection signal SM2Mi to the second selection signal M2Mi when the single-multiplication indication signal SMI is 1; or setting both the first single-multiplication selection signal SM1Mi and the second single-multiplication selection signal SM2Mi to 0 when the single-multiplication indication signal SMI is 0; and setting the control signal Si to the third bit a[i+1].
[0094] In a possible implementation, as shown in
[0095] As shown in
[0096] The fourth-type precoder is configured to perform the following coding operations: setting the first selection signal M1Mi to 1 when the first bit a[i−1] is not equal to the second bit a[i]; or setting the first selection signal M1Mi to 0 when the first bit a[i−1] is equal to the second bit a[i]; setting the second selection signal M2Mi to 1 when the first bit a[i−1] is equal to the second bit a[i] and the second bit a[i] is not equal to the third bit a[i+1]; or setting the second selection signal M2Mi to 0 when the first bit a[i−1] is not equal to the second bit a[i] or the second bit a[i] is equal to the third bit a[i+1]; setting the single-multiplication control signal SCi to the third bit a[i+1] when the single-multiplication indication signal SMI is 1; or setting the single-multiplication control signal SCi to 0 when the single-multiplication indication signal SMI is 0; setting the second multi-multiplication control signal MCNi to 0 when the multi-multiplication indication signal MMI is equal to the third bit a[i+1]; or setting the second multi-multiplication control signal MCNi to 1 when the multi-multiplication indication signal MMI is not equal to the third bit a[i+1]; setting the first single-multiplication selection signal SM1Mi to the first selection signal M1Mi and setting the second single-multiplication selection signal SM2Mi to the second selection signal M2Mi when the single-multiplication indication signal SMI is 1; or setting both the first single-multiplication selection signal SM1Mi and the second single-multiplication selection signal SM2Mi to 0 when the single-multiplication indication signal SMI is 0; and setting the control signal Si to the third bit a[i+1].
[0097] In a possible implementation, as shown in
[0098] Further, the Q groups of fusion coders 402 may include a plurality of different coders. For example, the plurality of different coders may include the following 14 coders. The following separately describes logical functions and circuit structures of the plurality of different coders in detail.
[0099] The Q groups of fusion coders 402 include a first coder. As shown in (a) in
[0100] In a possible implementation, as shown in (b) in
[0101] The Q groups of fusion coders 402 further include a second coder. As shown in (a) in
[0102] In a possible implementation, as shown in (b) in
[0103] The Q groups of fusion coders 402 further include a third coder. As shown in (a) in
[0104] In a possible implementation, as shown in (b) in
[0105] The Q groups of fusion coders 402 further include a fourth coder. As shown in (a) in
[0106] In a possible implementation, as shown in (b)
[0107] The Q groups of fusion coders 402 further include a fifth coder. As shown in (a) in
[0108] In a possible implementation, as shown in (b) in
[0109] The Q groups of fusion coders 402 further include a sixth coder. As shown in (a) in
[0110] In a possible implementation, as shown in (b) in
[0111] The Q groups of fusion coders 402 further include a seventh coder. As shown in (a) in
[0112] In a possible implementation, as shown in (b) in
[0113] The Q groups of fusion coders 402 further include an eighth coder. As shown in (a) in
[0114] In a possible implementation, as shown in (b) in
[0115] The Q groups of fusion coders 402 further include a ninth coder. As shown in (a) in
[0116] In a possible implementation, as shown in (b) in
[0117] The Q groups of fusion coders 402 further include a tenth coder. As shown in (a) in
[0118] In a possible implementation, as shown in (b) in
[0119] The Q groups of fusion coders 402 further include an eleventh coder. The eleventh coder is configured to perform the following coding operation: setting a partial product p(i, k) to 1 when the single-multiplication indication signal SMI is 1; or setting a partial product p(i, k) to 0 when the single-multiplication indication signal SMI is 0. In a possible implementation, the eleventh coder includes an AND gate. Two input ends of the AND gate are separately configured to receive the single-multiplication indication signal SMI and 1, and an output end of the AND gate is configured to output the partial product p(i, k).
[0120] The Q groups of fusion coders 402 further include a twelfth coder. The twelfth coder is configured to perform the following coding operation: setting s(i, 0) to the control signal Si when the single-multiplication indication signal SMI is 1; or setting s(i, 0) to 0 when the single-multiplication indication signal SMI is 0. In a possible implementation, the twelfth coder includes an AND gate. Two input ends of the AND gate are separately configured to receive the single-multiplication indication signal SMI and the control signal Si, and an output end of the AND gate is configured to output s(i, 0).
[0121] The Q groups of fusion coders 402 further include a thirteenth coder. The thirteenth coder is configured to perform the following coding operation: setting s(0, k) to the control signal Si when the multi-multiplication indication signal MMI is 1; or setting s(0, k) to 0 when the multi-multiplication indication signal MMI is 0. In a possible implementation, the thirteenth coder includes an AND gate. Two input ends of the AND gate are separately configured to receive the multi-multiplication indication signal MMI and the control signal Si, and an output end of the AND gate is configured to output s(0, k).
[0122] The Q groups of fusion coders 402 further include a fourteenth coder. The fourteenth coder is configured to perform the following coding operation: setting a partial product item Q(0, 1) to 1 when the multi-multiplication indication signal MMI is 1; or setting s(0, k) to 0 when the multi-multiplication indication signal MMI is 0. In a possible implementation, the fourteenth coder includes an AND gate. Two input ends of the AND gate are separately configured to receive the multi-multiplication indication signal MMI and 1, and an output end of the AND gate is configured to output Q(0, 1).
[0123] For ease of understanding, the following separately describes structures of the multiplier in embodiments of this application with reference to the single-double fusion multiplier shown in
[0124] With reference to
[0125] When the multiplier works in a double-multiplication mode, the first value is a value obtained by arranging two pieces of A0[m.sub.3-1:0] in a sequence from a low digit weight to a high digit weight or a value obtained after the value obtained through arrangement is filled with sign bits, and the second value is a value obtained by arranging two pieces of B0[m.sub.4-1:0] in a sequence from a high digit weight to a low digit weight or a value obtained after the value obtained through arrangement is filled with invalid bits. Specifically, if the two pieces of A0[m.sub.3-1:0] are represented as A1[m.sub.3-1:0] and A2[m.sub.3-1:0], A1[m.sub.3-1:0] is mapped to the (m.sub.3-1).sup.th digit weight to the 0.sup.th digit weight (which correspond to A[m.sub.3-1:0] in the single-multiplication operation) of the first value, and A2[m.sub.3-1:0] is mapped to the (2m.sub.3-1)t.sup.h digit weight to the (m.sub.3).sup.th digit weight (which correspond to A[2m.sub.3-1:m.sub.3] in the single-multiplication operation) of the first value. If the two pieces of B0[m.sub.4-1:0] are represented as B1[m.sub.4-1:0] and B2[m.sub.4-1:0], B1 [m.sub.4-1:0] is mapped to the (2m.sub.4+J-1).sup.th digit weight to the (m.sub.4+J).sup.th digit weight (which correspond to B[2m4 +J — 1:m4 +J] in the single-multiplication operation) of the second value, and B2[m.sub.4-1:0] is mapped to the (m.sub.4+J-1).sup.th digit weight to the J.sup.th digit weight (which correspond to B[2m.sub.4+J-1:J] in the single-multiplication operation) of the second value.
[0126] In addition, when the multiplier works in the double-multiplication mode, number points (which may also be referred to as partial products) corresponding to two binary multiplications A0[m.sub.3-1:0]×B0[m.sub.4−1:0] may form two rhombic arrays. The two rhombic arrays are mapped to a number point array in a single-multiplication mode from top to bottom according to a left-alignment principle. The two rhombic arrays may be specifically shown in
[0127] In addition, when the multiplier works in the double-multiplication mode, input of an (m.sub.3−2).sup.th precoder is A1[m.sub.3−3], A1[m.sub.3−2], and A1[m.sub.3−1], that is, the input of the (m.sub.3−2).sup.th precoder is bits on first three high digit weights in A1[m.sub.3-1:0]; and input of an (m.sub.3).sup.th precoder is 0, A2[0], and A2[1], that is, the input of the (m.sub.3).sup.th precoder is bits on last two low digit weights in A2[m.sub.3-1:0].
[0128] Optionally, when the multiplier works in the double-multiplication mode or the single-multiplication mode, if number points generated through sign bit extension in an operation process in the two modes are constants 1, the constants 1 may be added in advance, and then a sum is mapped to a number point in the single-multiplication mode.
[0129] In
[0130]
[0131] 2.sup.0, 2.sup.1, 2.sup.2, . . . , and 2.sup.m2 represent different digit weights. The digit weight is described with respect to an output result of the compressor 403, and is similar to ones, tens, or hundreds in a decimal system. The digit weight is used to represent a bit in a binary value of the output result. For example, if the output result of the compressor 403 is a 32-bit binary number, the output result includes 32 digit weights. A bit corresponding to the digit weight corresponds to 0 or 1, and represents one piece of binary information. It may be considered that one digit weight is one bit in the output result of the compressor 403.
[0132] For example, as shown in
[0133] When the multiplier is configured to perform the single-multiplication operation, the first value is A[7:0], and the second value is B[7:0]. When the multiplier is configured to perform the accumulated sum operation, A1 [3:0] is mapped to the third digit weight to the 0.sup.th digit weight (which correspond to A[3:0] in the single-multiplication operation) of the first value, and A2[3:0] is mapped to the seventh digit weight to the fourth digit weight (which correspond to A[7:4] in the single-multiplication operation) of the first value. When the multiplier is configured to perform the accumulated sum operation, B1[3:0] is mapped to the seventh digit weight to the fourth digit weight (which correspond to B[7:4] in the single-multiplication operation) of the second value, and B2[3:0] is mapped to the third digit weight to the 0.sup.th digit weight (which correspond to B[3:0] in the single-multiplication operation) of the second value.
[0134] In
[0135] In addition, when the multiplier works in the double-multiplication mode, input of a second precoder R(2) is A1[1], A1[2], and A1[3], and input of a fourth precoder R(4) is 0, A2[0], and A2[1]. Input and/or output of the precoders and the coders 402 are/is controlled, so that the multiplier can be enabled to work in the single-multiplication mode or the double-multiplication mode.
[0136] With reference to
[0137] When the multiplier works in a four-multiplication mode, the first value is a value obtained by arranging four pieces of A0[m.sub.3-1:0] in a sequence from a low digit weight to a high digit weight or a value obtained after the value obtained through arrangement is filled with sign bits, and the second value is a value obtained by arranging four pieces of B0[m.sub.4-1:0] in a sequence from a high digit weight to a low digit weight or a value obtained after the value obtained through arrangement is filled with invalid bits.
[0138] Specifically, if the four pieces of A0[m.sub.3-1:0] are represented as A1[m.sub.3-1:0], A2[m.sub.3-1:0], A3[m.sub.3-1:0], and A4[m.sub.3-1:0], A1[m.sub.3-1:0] is mapped to the (m.sub.3−1).sup.th digit weight to the 0.sup.th digit weight (which correspond to A[m.sub.3-1:0] in the single-multiplication operation) of the first value, A2[m.sub.3-1:0] is mapped to the (2m.sub.3−1).sup.th digit weight to the (m.sub.3)th digit weight (which correspond to A[2m.sub.3-1:m.sub.3] in the single-multiplication operation) of the first value, A3[m.sub.3-1:0] is mapped to the (3m.sub.3-1).sup.th digit weight to the (2m.sub.3)th digit weight (which correspond to A[3m.sub.3-1:2m.sub.3] in the single-multiplication operation) of the first value, and A4[m.sub.3-1:0] is mapped to the (4m.sub.3-1).sup.th digit weight to the (3m.sub.3).sup.th digit weight (which correspond to A[4m.sub.3-1:3m.sub.3] in the single-multiplication operation) of the first value. If the four pieces of B0[m.sub.4-1:0] are represented as B1[m.sub.4-1:0], B2[m.sub.4-1:0], B3[m.sub.4-1:0], and B4[m.sub.4-1:0], B1[m.sub.4-1:0] is mapped to the (4m.sub.4+J−1).sup.th digit weight to the (3m.sub.4+J).sup.th digit weight (which correspond to B[4m.sub.4+J−1:3m.sub.4+J] in the single-multiplication operation) of the second value, B2[m.sub.4-1:0] is mapped to the (3m.sub.4+J−1).sup.th digit weight to the (2m.sub.4+J).sup.th digit weight (which correspond to B[3m.sub.4+J−1:2m.sub.4+J] in the single-multiplication operation) of the second value, B3[m.sub.4-1:0] is mapped to the (2m.sub.4+J−1).sup.th digit weight to the (m.sub.4+J).sup.th digit weight (which correspond to B[2m.sub.4+J−1:m.sub.4+J] in the single-multiplication operation) of the second value, and B4[m.sub.4-1:0] is mapped to the (m.sub.4+J−1).sup.th digit weight to the J.sup.th digit weight (which correspond to B[m.sub.4+J−1:J] in the single-multiplication operation) of the second value.
[0139] In addition, when the multiplier works in the four-multiplication mode, number points (which may also be referred to as partial products) corresponding to four binary multiplications A0[m.sub.3-1:0]×B0[m.sub.4-1:0] may form four rhombic arrays. The four rhombic arrays are mapped to a number point array in a single-multiplication mode from top to bottom according to a left-alignment principle. The four rhombic arrays may be specifically shown in
[0140] In addition, when the multiplier works in the four-multiplication mode, input of an (m.sub.3−2).sup.th precoder is A1[m.sub.3−3], A1[m.sub.3−2], and A1[m.sub.3−1]; input of an (m.sub.3).sup.th precoder is 0, A2[0], and A2[1]; input of a (2m.sub.3−2).sup.th precoder is A2[m.sub.3−3], A2[m.sub.3−2], and A2[m.sub.3−1]; input of a (2m.sub.3).sup.th precoder is 0, A3[0], and A3[1]; input of a (3m.sub.3−2).sup.th precoder is A3[m.sub.3−3], A3[m.sub.3−2], and A3[m.sub.3−1]; and input of a (3m.sub.3).sup.th precoder is 0, A4[0], and A4[1].
[0141] Optionally, when the multiplier works in the four-multiplication mode or the single-multiplication mode, if number points generated through sign bit extension in an operation process in the two modes are constants 1, the constants 1 may be added in advance, and then a sum is mapped to a number point in the single-multiplication mode.
[0142] In
[0143]
[0144] In embodiments of this application, the Q groups of fusion coders 402 may all be configured to code a value in the single-multiplication operation or the multi-multiplication accumulated sum operation, and output the plurality of partial products to the compressor 403. The compressor 403 may be configured to compress the plurality of partial products corresponding to the single-multiplication operation or the multi-multiplication accumulated sum operation to obtain the two accumulated values. Finally, the adder 404 calculates the sum of the two accumulated values to obtain the result of the single-multiplication operation or the accumulated sum operation. Therefore, compared with a multiplier that supports two different multiplication modes in the conventional technology, the multiplier provided in embodiments of this application does not need to separately code and compress values in two different multiplication modes by using different coders or compressors, so that a quantity of coders required by the multiplier is reduced, operation duration is shortened, and power consumption of the multiplier is reduced.
[0145] According to another aspect of this application, a processor or a chip is further provided, and the processor or the chip includes a multiplier. The multiplier may include the multiplier, the precoder, the coder, or the like provided in any one of
[0146] The foregoing descriptions are merely specific implementations of this application, but are not intended to limit the protection scope of this application. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in this application shall fall within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.