RADIO RECEIVER SYNCHRONIZATION

Abstract

A radio apparatus is configured to correlate signal data with stored synchronization data to generate synchronization correlation data. The signal data represents a received radio-frequency signal that encodes a data frame having a synchronization preamble comprising a plurality of instances of a predetermined synchronization sequence. The stored synchronization data represents the predetermined synchronization sequence. The synchronization correlation data is generated by correlating signal data representing the synchronization preamble with the stored synchronization data. While generating the synchronization correlation data, the radio apparatus identifies a first set of one or more peaks in the synchronization correlation data, and determines first synchronization information from the first set of one or more peaks. After generating more of the synchronization correlation data, the radio apparatus identifies a second set of one or more peaks in the synchronization correlation data, and determines second synchronization information from the second set of one or more peaks.

Claims

1. A radio apparatus configured: to correlate signal data with stored synchronization data to generate synchronization correlation data, wherein the signal data represents a received radio-frequency signal that encodes a data frame having a synchronization preamble comprising a plurality of instances of a predetermined synchronization sequence, wherein the stored synchronization data represents the predetermined synchronization sequence, and wherein the synchronization correlation data is generated by correlating signal data representing the synchronization preamble with the stored synchronization data; while generating the synchronization correlation data, to identify a first set of one or more peaks in the synchronization correlation data, and to determine first synchronization information for the radio apparatus from the first set of one or more peaks; and after generating more of the synchronization correlation data, to identify a second set of one or more peaks in the synchronization correlation data, and to determine second synchronization information for the radio apparatus from the second set of one or more peaks.

2. The radio apparatus of claim 1, wherein the first synchronization information comprises symbol timing information.

3. The radio apparatus of claim 1, wherein the first synchronization information comprises a frequency offset estimate.

4. The radio apparatus of claim 1, wherein the second synchronization information comprises symbol timing information.

5. The radio apparatus of claim 1, wherein the second synchronization information comprises a frequency offset estimate.

6. The radio apparatus of claim 1, wherein the radio apparatus comprises a radio receiver for receiving the radio-frequency signal as a radio signal, and wherein the radio apparatus is configured to generate the signal data from the received radio signal while the radio receiver is receiving the radio signal.

7. The radio apparatus of claim 1, wherein the radio apparatus is configured to determine the first and second synchronization information while the radio apparatus is generating the synchronization correlation data from the signal data representing the synchronization preamble.

8. The radio apparatus of claim 1, wherein the radio apparatus is configured to use the first synchronization information for synchronizing the receiving, by the radio apparatus, of at least a first part of the synchronization preamble of the radio-frequency signal, and to use the second synchronization information for synchronizing the receiving, by the radio apparatus, of at least a second part of the synchronization preamble of the radio-frequency signal.

9. The radio apparatus of claim 1, further comprising a symbol detector for detecting symbols from the signal data, and wherein the radio apparatus is configured to use at least the first synchronization information or the second synchronization information to synchronize the symbol detector.

10. The radio apparatus of claim 1, wherein the radio apparatus is configured to accumulate frequency-synchronization information determined from respective sets of one or more peaks, and to use the accumulated information for synchronizing the receiving, by the radio apparatus, of at least part of the radio-frequency signal.

11. The radio apparatus of claim 10, wherein the radio apparatus is configured to determine an averaged frequency offset estimate as a coherent average of a plurality of frequency-offset estimates, determined from respective peaks in the synchronization correlation data, and to use the averaged frequency offset estimate for synchronizing the receiving, by the radio apparatus, of at least part of the radio-frequency signal.

12. The radio apparatus of claim 1, wherein the radio apparatus is configured to select frequency-synchronization information, determined from one peak or from one set of peaks, from a larger quantity of frequency-synchronization information determined from a plurality of respective peaks or respective sets of peaks, and to use the selected frequency offset estimate for synchronizing the receiving, by the radio apparatus, of at least part of the radio-frequency signal.

13. The radio apparatus of claim 1, wherein the radio apparatus is configured to determine whether later-determined synchronization information is to replace earlier-determined synchronization information, and, if the radio apparatus determines that the later-determined synchronization information should replace the earlier-determined synchronization information, to use the later-determined synchronization information for synchronizing the receiving, by the radio apparatus, of at least part of the radio-frequency signal, and, if it determines that the later-determined synchronization information should not replace the earlier-determined synchronization information, to discard the later-determined synchronization information or to accumulate the later-determined synchronization information with the earlier-determined information.

14. The radio apparatus of claim 1, wherein the radio apparatus is configured to detect peaks within the synchronization correlation data as the synchronization correlation data is generated, and to determine respective updated synchronization information in response to detecting a new peak in the synchronization correlation data, for at least one or more peaks.

15. The radio apparatus of claim 1, configured to identify each of the sets of one or more peaks by performing a peak-analysis process on the synchronization correlation data, wherein the peak-analysis process comprises determining whether a new peak satisfies a qualifying condition for inclusion in a set of one or more peaks for determining synchronization information for the radio apparatus.

16. The radio apparatus of claim 15, wherein the qualifying condition comprises a magnitude condition that requires a peak to be associated with a correlation value, in the synchronization correlation data, having a magnitude greater than a threshold.

17. The radio apparatus of claim 15, wherein the qualifying condition comprises a timing condition that requires a peak, in the synchronization correlation data, to be separated from an earlier peak by a time interval that corresponds to the duration of the predetermined synchronization sequence.

18. The radio apparatus of claim 15, wherein the radio apparatus comprises a symbol detector, and wherein the qualifying condition comprises a symbol-detection condition, and the peak-analysis process comprises using the symbol detector to determine whether a peak, in the synchronization correlation data, is consistent with a symbol of the predetermined synchronization sequence.

19. A method of synchronizing a radio apparatus, the method comprising: correlating signal data with stored synchronization data to generate synchronization correlation data, wherein the signal data represents a received radio-frequency signal that encodes a data frame having a synchronization preamble comprising a plurality of instances of a predetermined synchronization sequence, wherein the stored synchronization data represents the predetermined synchronization sequence, and wherein the synchronization correlation data is generated by correlating signal data representing the synchronization preamble with the stored synchronization data; while generating the synchronization correlation data, identifying a first set of one or more peaks in the synchronization correlation data, and determining first synchronization information for the radio apparatus from the first set of one or more peaks; and after generating more of the synchronization correlation data, identifying a second set of one or more peaks in the synchronization correlation data, and determining second synchronization information for the radio apparatus from the second set of one or more peaks.

20. The method of claim 19, wherein: the first synchronization information comprises timing-synchronization information; the second synchronization information comprises frequency-synchronization information; and the first set of peaks contains fewer peaks than the second set of peaks.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Certain preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0054] FIG. 1 is a schematic drawing of a radio communication system including a receiver embodying the invention;

[0055] FIG. 2 is a diagram of a data packet that may be transmitted and received by the radio communication system;

[0056] FIG. 3 is schematic drawing of synchronization and decoding logic of the radio receiver;

[0057] FIG. 4 is schematic graph of correlation amplitude against time in a first example scenario;

[0058] FIG. 5 is schematic graph of correlation amplitude against time in a second example scenario;

[0059] FIG. 6 is plot of magnitude against time for three correlation values to explain a principle of operation of a receiver embodying the invention;

[0060] FIG. 7 is flow chart of operations carried out by a receiver performing a synchronization process embodying the invention;

[0061] FIG. 8 is a plot of packet error rate (PER) against sensitivity for simulations of embodiments using different correlation thresholds; and

[0062] FIG. 9 is a plot of packet error rate (PER) against selectivity for simulations of embodiments using different correlation thresholds.

DETAILED DESCRIPTION

[0063] FIG. 1 shows, by way of an example embodiment, a radio communication system comprising a wireless thermostat 1 which is in short-range radio communication with a wireless-network hub 7. The hub 7 is a radio receiver embodying the present invention.

[0064] The wireless thermostat 1 has a temperature sensor 2 which is connected to a microprocessor 3 (such as an ARM™ Cortex M-series). The microprocessor 3 is connected to a radio transmitter 4. The radio transmitter 4 includes an encoder 5 (among other components). The encoder 5 may be implemented by a dedicated hardware circuit, or by software executing on a processor, or by a combination of hardware and software logic. Other conventional components, such as memory, a battery, etc. are also present, but are omitted from FIG. 1 for the sake of simplicity. The microprocessor 3 and radio transmitter 4 may be integrated on a single silicon chip. The monitor 1 has a radio antenna 6, which may be integrated on such a chip or external to it.

[0065] The hub 7 has, among other conventional components (not shown), an antenna 8 which is connected to a radio receiver 9. The antenna 8 is suitable for receiving short-range radio communications from wireless-personal-area-network devices, including the wireless thermostat 1. The radio receiver 9 includes synchronization and decoding logic 10, among other components. The logic 10 may be implemented by a dedicated hardware circuit, or by software executing on a processor, or by a combination of hardware and software logic. The radio receiver 9 is connected to a microprocessor 11 (such as an ARM™ Cortex M-series), which can output data for display on a screen 12, possibly via other components, such as a further microprocessor (not shown) running an operating system and appropriate software applications.

[0066] In use, the wireless thermostat 1 receives periodic temperature readings from the temperature sensor 2. The microprocessor 3 processes the readings into a suitable format for transmission, and sends the message data to the radio transmitter 4. The radio transmitter 4 determines whether the message data can fit within a single data packet (corresponding to a single data frame), or if it must be split across two or more data packets. The encoder 5 in the radio transmitter 4 encodes part or all of the message data, e.g. using a convolution-based forward-error-correcting code, and adds any headers or other metadata to the encoded message data to create a packet payload. It then direct-sequence-spread-spectrum (DSSS)-encodes this entire payload using a fixed chip sequence. For example, each four-bit symbol might be represented by a different respective 32-bit spreading sequence. Of course, other lengths of chip sequence may be used. The transmitter 4 then prepends a synchronization word to the payload, consisting of a number repetitions of a predetermined sequence. This may be followed by a predetermined start-of-frame delimiter (SFD) and/or a payload-length header, before the data payload containing the message data. The radio transmitter 4 transmits the encoded data packet from the antenna 6, modulated on a radio-frequency carrier (e.g. a carrier in the 2.4 GHz band), using a suitable modulation scheme.

[0067] In some embodiments, the wireless thermostat 1 and hub 7 communicate using a protocol having a physical layer that implements a version of the IEEE 802.15.4 standard. They may, for example, communicate using Thread™ or ZigBee™. In some such embodiments, each 4-bit symbol is mapped onto a 32-chip spreading sequence, and packets are modulated using offset quadrature phase-shift keying (O-QPSK) operating at a data rate of 250 kb/s. Each symbol thus has a duration of 16 μs.

[0068] FIG. 2 shows an exemplary data packet structure used in such 802.15.4 embodiments. It has a 32-bit (8-symbol) preamble synchronization sequence, followed by an 8-bit start-of-frame delimiter (SFD), an 8-bit physical-layer (PHY) header, and a variable-length PHY service data unit (PSDU) of between zero and 127 octets. The preamble sequence consists of eight instances of the zero symbol, 0000′b. After DSSS-encoding this becomes eight instances of the same 32-chip sequence. The SFD field contains the fixed two symbols 1010 0111′b (0xA7) and introduces the start of the substantive content of the frame, which starts with a variable in the PHY header that indicates the length of the PSDU and then provides the PSDU itself.

[0069] In use, the wireless-network hub 7 receives the radio data packet at the antenna 8. The radio receiver 9 down-mixes the received signal to an intermediate frequency or directly to baseband, and then samples the signal to generate a stream of complex digital samples values, representing in-phase and quadrature components of the received signal. The signal may first be filtered in the analog and/or digital domains. The receiver 9 processes the modulated digital signal using the synchronization and decoding logic 10.

[0070] The synchronization and decoding logic 10 performs non-coherent decoding. It first cross-correlates the incoming sample stream, I & Q, with stored data representing the waveform, at baseband, of a single instance of the modulated chip sequence corresponding to the synchronization symbol, 0000′b. It does this by maintaining a buffer of the most recently-generated samples, and calculating a time series of complex inner-product operations between the stored synchronization template and the currently-buffered data, thereby generating a time series of complex correlation values, C.sub.n. It analyses the correlation values over time in order to perform symbol timing recovery and frequency offset correction. This process is explained in more detail below, with reference to FIGS. 3 to 7.

[0071] The repetitive synchronization sequence allows the synchronization and decoding logic 10 to detect and synchronize to a packet based on the separation in time between correlator matches, as well as correlator output amplitude, as described in more detail below.

[0072] The synchronization and decoding logic 10 determines the end of the preamble, and the start of the PSDU, by detecting the SFD field, thereby achieving frame (i.e. packet) synchronization. The radio receiver 9 can then decode the PSDU, using the acquired frame and symbol timing information to do so, before passing the decoded message data to the microprocessor 11 for processing.

[0073] The microprocessor 11 may process the message data in any appropriate way. In some embodiments, it may display temperature information graphically on a display screen 12 of the hub 7 for a user to see.

[0074] In some embodiments, the wireless thermostat 1 and hub 7 may be configured so that temperature message data is transferred from the wireless thermostat 1 to the hub 7 using the Thread™ or ZigBee™ specification. The wireless thermostat 1 and hub 7 may be equipped for two-way radio communication, using corresponding components as those described above for performing radio transmission in the opposite direction. However, this is not essential in all embodiments.

[0075] FIG. 3 schematically represents various digital baseband processing units implemented by the synchronization and decoding logic 10 for detecting and decoding a received data frame. Operations such as filtering and residual frequency-offset tracking are not shown, for reasons of conciseness.

[0076] Complex-valued baseband samples, I & Q, are received into a data-aided joint timing and frequency synchronization unit 33, for determining symbol and frame timing synchronization data and frequency-offset estimation data. The synchronization unit 33 is coupled to a CORDIC (coordinate rotation digital computer) unit 34, for performing carrier frequency offset (CFO) compensation on the incoming samples.

[0077] The CFO-compensated complex samples then pass to a detector 31, which detectors the DSSS-encoded data symbols. The detector 31 outputs a stream of decoded symbols, in groups of four bits, B, to the microprocessor 11. These decision symbols are also fed back to the timing- and frequency-synchronization unit 33.

[0078] FIG. 3 uses the following notation: [0079] n=chip index; [0080] z(n)=complex baseband samples; [0081] z′(n)=carrier-frequency offset (CFO) compensated z(n); [0082] pdata.sub.i(k)=stored data representing the i different 32-bit DSSS chip sequences.

[0083] The timing- and frequency-synchronization unit 33 comprises a correlator 35, referred to herein as a “double” correlator 35, for performing data-aided joint timing and frequency estimation, and associated synchronization logic 36. This exploits knowledge of the data in the received symbols to cancel the effect of the modulation on the estimate of a delay-and-correlate type of carrier frequency offset estimator.

[0084] Because a repetitive synchronization word is received, additional checks on the time domain distances between successive magnitude responses can be used to filter out false detections. This means that a shorter correlator with a lower detection threshold can be used to achieve a given level of sensitivity lowering receiver complexity.

[0085] The synchronization unit 33 in FIG. 3 correlates against the repeated synchronization word in order to calculate the following cross correlation values for every incoming baseband sample, u.sub.n=wI(n)+jQ(n):

[00001]$C_n=\underset{i=0}{\overset{L-1}{.Math.}}\left[z_{n-i}{z}_{n-i-D}^{*}\right]d_i,$

[0086] where the coefficients d.sub.i comprise stored synchronization data, calculated in advance, in which d.sub.i=p*.sub.ip.sub.i+D where pi are samples corresponding to the predetermined synchronization symbol at baseband,

[0087] where D is a lag which is decided at design time (e.g. eight or sixteen samples), and where L corresponds to the length of the synchronization symbol, at the sampling rate used by the logic 10.

[0088] The signal may, in some embodiments, be over-sampled and/or up-sampled, in which case the stored synchronization data may be scaled up correspondingly. The cross-correlation operation may be performed using sample-wise multiplication operations.

[0089] The synchronization unit 33 is also able to generate carrier-frequency offset estimates according to the equation:

[00002]$\Delta \hat{f}=\frac{1}{2\pi \mathrm{DT}}\arg \left\{\underset{i=0}{\overset{L-1}{.Math.}}\left[z_{n-i}{z}_{n-i-D}^{*}\right]d_i\right\},$

[0090] where T is the sample period.

[0091] Assuming that the carrier frequency offset is relatively constant over D samples, this estimate provides a good estimate of the carrier-frequency offset, so long as it is sampled when the correlation is aligned with an incoming synchronization symbol—i.e. at time instants corresponding to peaks in the absolute correlation value |Cn|, or in a normalised magnitude measure such as M given by:

[00003]$M_n=\frac{.Math.C_n.Math.}{P_n},\mathrm{where}{P}_n=\underset{i=0}{\overset{L-1}{.Math.}}{.Math.z_{n-i-D}.Math.}^2.$

[0092] Qualifying peaks in the correlation data may be determined against a magnitude threshold, as explained below. They are stored in a peak pool 60 and processed as described below, to determine what peaks to use for generating carrier frequency offset (CFO) estimates for the CORDIC unit 34 and symbol timing information (strobe time) for synchronizing the detector 31.

[0093] The CORDIC unit 34 receives frequency offset estimates from the synchronization unit 33, and uses the latest frequency offset estimate it receives to rotate subsequent incoming samples by a corresponding phase angle, to compensate for any carrier frequency offset. The resulting CFO-compensated sequence of complex baseband samples z′(n) is then passed to the detector 31.

[0094] The logic 10 may be implemented in hardware and may include a finite state machine (FSM) for orchestrating the synchronization and decoding process.

[0095] FIGS. 4 & 5 illustrate some of the challenges which can arise when using a naïve approach to synchronization, and which are addressed by embodiments as disclosed herein. They show peaks in the correlation amplitude, over time, generated by correlating incoming signals against a predetermined preamble sequence, having the form shown in FIG. 2.

[0096] A naïve approach might identify peaks above a threshold level (represented by the horizontal dashed lines in FIGS. 4 & 5) using any appropriate peak-finding algorithm, and may declare that symbol-timing synchronization has been achieved as soon as three peaks have been identified that satisfy a spacing requirement that each successive peak occurs after the preceding peak by one preamble-symbol period plus/minus a tolerance for jitter (e.g. +/−1%).

[0097] When the output is as shown in FIG. 4, in which a first peak 40, second peak 41 and third peak 42 occur exactly at the preamble-symbol spacing, this approach may work adequately.

[0098] However, the output as shown in FIG. 5 would cause synchronization problems. In this example, a second peak 51 has a sidelobe peak 51a that is above the threshold, but that occurs less than 0.95 of a symbol period after a preceding peak 50, causing both the first peak 50 and the sidelobe peak 51a to be discarded, even though the first peak 50 was a valid peak. This then delays synchronization being declared by one symbol duration, until the second peak 51, a third peak 52 and a fourth peak 53 have been identified. Delayed synchronization is undesirable in itself, but if this situation occurs several times within one packet preamble, then synchronization may fail altogether for that packet. A spurious peak could be a sidelobe of a valid peak, or any other erroneous above-threshold peak such as a peak arising due to noise.

[0099] Conversely, if three spurious peaks occur that satisfy the spacing condition, the receiver could falsely declare synchronization based on the timing of these spurious peaks, which will then not be correct and could lead to loss of the packet.

[0100] In general, if synchronization loss can be reduced, the sensitivity of a radio receiver should improve. Ideally, this would be done without unduly reducing selectivity (that is, the receiver's ability to reject signals on channels outside the desired tuned channel).

[0101] Embodiments disclosed herein therefore take a different approach. They do not declare preamble synchronization completed upon detecting a fixed number of qualifying peaks, calculating and outputting only one set of symbol-timing information and one carrier frequency offset estimate. Instead, they may apply different conditions for determining when to output symbol-synchronization information and when to output frequency offset estimates (i.e. not necessarily always at the same time). They also continue generating and processing subsequently-received synchronization-preamble correlation data, as more of the synchronization preamble is received, so to detect any further qualifying peaks, and potentially generate updated timing- and/or frequency-synchronization information, which may be more accurate.

[0102] This can potentially lead to the receiver 9 synchronizing both faster and more reliably. It may, for instance, enable better frequency-offset estimates to be calculated, by allowing CFO estimates to be calculated based on phase values determined over more than three peaks (e.g. averaged over five or more peaks), while allowing symbol timing to be determined based on a lower number of peaks (e.g. using just three peaks, if noise prevents synchronizing on more than three). This can improve the CFO estimate accuracy without reducing the probability of successful frame synchronization.

[0103] The present synchronization and decoding logic 10 therefore runs unconditionally all the way up to the detection of the SFD, rather than terminating as soon as synchronization can be declared.

[0104] More details of how this may be implemented in some exemplary embodiments will now be provided, along with simulation data that validates the approach.

[0105] 802.15.4 Receiver Design Using Accumulative DouBle Correlation (ADBC)

[0106] The following description is given for an IEEE 802.15.4 receiver 9 that uses a “double” correlator (“DBC”) approach, as introduced above, to accumulate frequency offset estimates repeatedly over the duration of the preamble sequence. The present approach will be referred to herein for convenience as Accumulative DouBle Correlation or “ADBC”. However, it should be appreciated that the same underlying principles may be adapted for receiving different radio protocols or for use in different receiver architectures.

[0107] The double correlator 35 in the synchronization unit 33 here works together with the symbol detector 31, in a cooperative manner, in order to unlock the symbol timing configuration, even in challenging environments, such as a strong co-channel interference signal.

[0108] Assuming a sampling rate of 8 mega-samples per second (or 4 samples per chip), the analogue waveform of symbol 0 (i.e. 0000′b), which is a 32-chip sequence after spreading, and which appears eight times in the synchronization preamble of each frame, can be represented by a column vector w that consists of 128 complex samples, written as

w=[.sub.0,.sub.1, . . . , .sub.127]  (1)

[0109] Using equation (1) and the fact that there should be zero phase difference between the phase at the beginning of the symbol and at the end of the symbol, this can be extended w to a 136 sample sequence v, i.e.

[00004]$\text{?}$$\text{?}\text{indicates text missing or illegible when filed}$

[0110] A 128 sample vector d can be generated, whose i-th element is calculated as

d.sub.i=v.sub.i+8v*.sub.i  (3)

[0111] The values of d are stored in a memory accessible by the synchronization and decoding logic 10, as stored synchronization data representative of the predetermined synchronization sequence, providing a reference waveform which will be used for symbol timing in the preamble-based synchronization process. These values may be calculated by the receiver 9 as needed, or may be precalculated and stored during manufacturing. Different values for the lag, D, other than D=8, may be used in other embodiments, depending on requirements.

[0112] The ADBC receiver 9 calculates the auto-correlation between received IQ samples z.sub.t and z.sub.t-8, i.e. w.sub.t=z.sub.tz*.sub.t-8. As the signal data is generated from the incoming radio signal, the receiver stores the latest 128 values of w.sub.t into a 128 sample register, denoted by a column vector w. After correlating w with the reference sequence d, a ratio γ is calculated be one of two possible methods.

[0113] In a first method, γ is calculated according to

[00005]$\text{?}$$\text{?}\text{indicates text missing or illegible when filed}$

[0114] In a second method, γ is calculated according to

[00006]$\text{?}$$\text{?}\text{indicates text missing or illegible when filed}$

[0115] Equation (5) can be considered as an approximation of Equation (1). Although method 2 uses an approximated calculation result, it is expected to achieve similar performance as the first method. The complexities of both methods are almost the same.

[0116] FIG. 6 illustrates three representative successive cross-correlation samples of the correlation data generated by the double correlator 35, for aiding understanding of the synchronization procedure described below with reference to FIG. 7 and the pseudo code below. In FIG. 6, C stands for the complex correlation value, while γ is a real-valued ratio calculated according to one of Equations (4) or (5) above, or as M further above. Sample index D1 indicates the peak in γ, while D2 indexes the sample immediately preceding the peak, and the unindexed values are the sample immediately following the peak. Considering three samples, rather than just the peak sample, can improve synchronization accuracy by allowing for possible timing errors.

[0117] FIG. 7 illustrates the main steps in the synchronization process, which may be implemented in the synchronization unit 33 by a set of hardware finite state machines (FSM), implementing the procedures shown in the pseudocode below. In variant embodiments, some or all of the steps or procedures may alternatively be implemented by software executing on a processor, or as a combination of hardware and software. For a full understanding, the pseudocode below should be read in conjunction with FIG. 7.

[0118] FIG. 7 and the pseudocode use the following variables, with the following meanings:

[0119] S: a state variable −0=IDLE; 1=accepting new peaks; 2=ignore new peaks in γ

[0120] R=γ.sub.local: maximum peak strength in the past (initial value R=0)

[0121] H.sub.D2, H.sub.D1, H: correlation sums for CFO estimation

[0122] Δf=F: the latest CFO estimate

[0123] N: strobe offset to trigger the detector (initial value N=0)

[0124] C: number of valid bits from the detector (initial value C=0)

[0125] n: a strobe counter, n=0, . . . , 127, wrapping every 128 samples (i.e. every 4-bit symbol)

[0126] m: a symbol boundary variable

[0127] B: latest four bits, xxxx′b, output from the detector 31

[0128] I.sub.DBC: a sync indicator indicating that correlator (DBC) 35 has raised a flag that the symbol timing achieved, meaning that the estimated symbol boundary offset is assigned to m

[0129] I.sub.strobe: a strobe trigger indicating that a strobe signal is triggered. When n==m,

[0130] I.sub.strobe is set to 1, otherwise 0.

[0131] I.sub.invalid: an invalid output indicator, indicating that an invalid output is given by the detector 31 which should be ignored

[0132] I.sub.sync: a frame sync indicator, indicating that a valid frame sync word is captured

[0133] I.sub.drop1peak: an invalid peak indicator, indicating that the correlator (DBC) 35 should ignore the following peak due to a wrong spacing, which may be due to detecting a symbol [1110]. This allows a detection delay to be taken into account, e.g. which may arise when the detector 31 has a pipelined design.

[0134] It uses two threshold parameters, which may be configurable in some embodiments, e.g. under the control of firmware executing in the processor 11:

[0135] A: a threshold for identifying a valid peak

[0136] D: a threshold for deciding whether to accumulate the frequency offset estimate or not

[0137] The process starts in an idle state (S=0) with a waiting 2 for an event. These events may be:

[0138] i) a new peak being detected in the correlation data,

[0139] ii) a trigger from a strobe counter, n, or

[0140] iii) a 4-bit symbol being output by the detector 31.

[0141] In use, the synchronization unit 33 calculates the ratio γ for every incoming IQ sample. It performs a simple peak detection process to detect whenever three successive values of γ rise then fall, as shown in FIG. 6. This signals a peak, albeit not necessarily a peak that qualifies in strength or spacing for use in determining updated timing- and/or frequency-synchronization information.

[0142] Initially, the receiver searches for a valid correlation peak over γ to determine the starting point of a valid 802.15.4 frame.

[0143] When a new peak is detected in γ, the overwrite branch 71 is invoked. This checks if the unit 33 is accepting new peaks, and if the peak has a magnitude that is above the threshold A and also higher than any previously-identified peak. It also checks if the peak is not spaced close to (e.g. within a configurable limit of one or two samples of) an integer number of symbol widths from the last valid peak identified by the overwrite branch 71 (i.e. is not in an expected position). Assuming these checks all pass, this will detect the first peak of a new frame, but thereafter will only detect peaks in unexpected locations if they are very strong peaks. Upon detecting a qualifying peak, this branch 71 starts the detector 31. It also calculates a new frequency offset estimate, Δf (also called Fin the pseudocode below), and outputs this estimate, Δf, to the CORDIC 34. It does not accumulate the frequency offset with earlier frequency offsets, but establishes a new CFO estimate Δf for the CORDIC 34, effectively “overwriting” any earlier estimate. It also outputs initial or updated symbol timing information to the detector 31, by setting N=n. If this is not the first peak of the frame, the symbol timing information will overwrite any earlier symbol timing information—either immediately or when the final frame sync is asserted. Lines 25 to 40 of the ADBC procedure, “Procedure 3”, below, relate particularly to the overwrite branch 71.

[0144] A trigger from the strobe counter initiates an accumulation branch 72. This checks if the unit 33 is accepting new peaks, and if the current peak exceeds the threshold D for accumulating frequency offset estimates. It also checks if the peak is spaced an integer number of symbols, i.e. k×128 samples, away from the preceding qualifying peak. If these checks all pass, it proceeds to update the maximum peak strength variable, R, and to perform a coherent accumulation of the three correlation sample values, C.sub.D2, C.sub.D1, C, around the peak (see FIG. 6), with the respective initial or accumulated values from the preceding peak detection. It calculates an updated frequency offset estimate Δf for the CORDIC 34 to use, based on whichever accumulated complex correlation value has the largest magnitude (to account for any sampling timing errors). Lines 10 to 24 of the ADBC procedure, “Procedure 3”, below, relate particularly to the accumulation branch 72.

[0145] By use of these branches 71, 72, the synchronization unit 33 determines symbol timing information (represented by N) and calculates initial & updated frequency offset estimates, Lf (also called Fin the pseudocode below), and symbol synchronization, based on peak amplitude & spacing alone, without requiring a fixed number of peaks to have been detected. The frequency and symbol estimates may be updated over time, assuming further qualifying new peaks are detected as the preamble is processed. The use of an adaptive threshold for detecting qualifying peaks in the overwrite branch 71 can efficiently reduce the risk that a false frame synchronization peak locks the receiver so that a real peak is lost, while also efficiently reducing the risk that a real peak is overridden by a false one.

[0146] The logic 10 uses the detector 31 to improve the synchronization accuracy compared with what the correlator 35 alone could accomplish, especially in the presence of noise or interference.

[0147] A new symbol from the detector 31 causes the “reset or stop” branch 73 to be followed. This uses the output of the symbol detector 31 to check that the preamble contains only the synchronization symbol, 0000′b, or that the SFD, 0xA7=1110 0101′b has been reached (the bits are presented here in reversed bit order, purely for implementation reasons). If the first SFD symbol is detected, the detection of new peaks is stopped 74, and the arrival of the second SFD symbol as the next-detected symbol results in the synchronization unit 33 to signal to the detector 31 and/or the microprocessor 11 that frame synchronization has been achieved 76. If another symbol is detected during the preamble, or if the first and second SFD symbols are not detected in sequence, an error is detected and the synchronization unit is reset 75. The causes the peak searching process to restart, using the default initial values. The sync-word procedure, “Procedure 2”, below, relates particularly much to the reset or stop branch 73.

[0148] The synchronization unit 33 implements three procedures that work simultaneously: a strobe-counting procedure, a synchronization word capture procedure, and an accumulative correlation procedure. The actions of each procedure will be better understood from studying the following pseudocode.

[0149] The following “strobe counting” procedure manages the strobe counter, used for determining the symbol timing information and for checking the spacing of the peaks.

TABLE-US-00001 Procedure 1: Strobe Counting FSM  1: procedure STROBECOUNTING  2:  Set n ← 0  3:  Set m ← 64  4:  Set strobe offset variable M ← −2  5:  Set output 4-bit symbol X ← [0000]  6:  while a new IQ sample u.sub.t arrives do  7:   Calculate n ← mod(n + 1, 128)  8:   if n == m then  9:    if I.sub.DBC == 1 then 10.     I.sub.strobe ← 1 11:    else 12:     I.sub.strobe ← 0 13:    end if 14:    Copy samples to the shade register 15:    Start the symbol detection 16:   else 17:    if I.sub.DBC == 1 then 18:     if n == mod(m − 2, 128) then 19:      Take the output from the symbol detector and assign it to X 20:     end if 21:    end if 22:    I.sub.strobe ← 0 23:   end if 24:  end while 25: end procedure

[0150] The following “synchronization word” procedure relates particularly to the “reset or stop” branch 73 of FIG. 7. In particular, lines 15-19 relate to the detection of symbols [1110] and [0101] of the “start of frame delimiter” SFD. If the symbol [0101] is output by the detector 31, this is signalled in line 18; and the synchronization unit 33 is reset 75 in line 19, due to the unexpected symbol.

TABLE-US-00002 Procedure 2: Sync-Word Capture  1: procedure FRAMESYNCWORDCAPTURE  2:  Set N.sub.Bit0s ← 4  3:  Set output bit index variable l ← 0  4:  Set 12-bit register R ← [000000000000]  5:  Set I.sub.invalid ← 0  6:  while a new IQ sample u.sub.t arrives do  7:   if I.sub.strobe == 1 then  8:    if I.sub.invalid == 0 then  9:     Set l ← l + 4 10:     if I.sub.sync == 0 then 11:      if X == [0000] then 12:       if l > N.sub.Bit0s then 13:        l ← N.sub.Bit0s 14:       end if 15:      else if X == [1110] && l == N.sub.Bit0s + 4 then 16:       Continue 17:      else if X == [0101] && l == N.sub.Bit0s + 8 then 18:       I.sub.sync ← 1 19:       Stop DBC 20:      else 21:       l ← 0 22:       γ.sub.Local ← γ.sub.Config 23:       I.sub.DBC ← 1 24:       I.sub.drop1peak ← 0 25:       H ← 0, H.sub.D1 ← 0, H.sub.D2 ← 0 26:      end if 27:     end if 28:    else 29:     I.sub.invalid ← 0 30:    end if 31:   end if 32:  end while 33: end procedure

[0151] In the following ADBC procedure, lines 25 to 40 relates particularly the overwrite branch 71 of FIG. 7, while lines 10 to 24 relate to the accumulation branch 72.

TABLE-US-00003 Procedure 3: Accumulative Double Correlator FSM  1: procedure ADBC-FSM  2:  if ADBC-FSM is enabled then  3:   Set DBC ratio variables γ.sub.D1 ← 0, γ.sub.D2 ← 0, γ.sub.Local ← γ.sub.Config  4:   Set DBC sum variables C ← 0, C.sub.D1 ← 0, C.sub.D2 ← 0  5:   Set DBC sum history vaiables H ← 0, H.sub.D1 ← 0, H.sub.D2 ← 0  6:   Set I.sub.drop1peak ← 0  7:   Set frequency offset estimate F ← 0  8:   while a new u.sub.t arrives do  9:    Calculate the ratio γ as (4) or (5) 10:    if I.sub.DBC == 1 && mod(m − n − M, 128) == 0 then 11:     Find [γ.sub.Maxp.sub.Max] = max(γ.sub.D2, γ.sub.D1, γ) 12:     if γ.sub.Max > γ.sub.Config && b ≤ 5 then 13:      H ← H + C, H.sub.D1 ← H.sub.D1 + C.sub.D1, H.sub.D2 ← H.sub.D2 + C.sub.D2 14:      if p.sub.Max == 1 then 15:       Update F based on H.sub.D2 16:      else if p.sub.Max == 2 then 17:       Update F based on H.sub.D1 18:      else 19:       Update F based on H 20:      end if 21:      if γ.sub.Max > γ.sub.Local then 22:       γ.sub.Local ← γ.sub.Max 23:      end if 24:     end if 25:    else if [γ.sub.D1 > γ && γ.sub.D1 ≥ γ.sub.D2 && γ.sub.D1 ≥ γ.sub.Local] then 26:     if γ.sub.D1 > γ.sub.Local then 27:      if I.sub.DBC == 0 || mod(m − n − M, 128) > 1 then 28:       if I.sub.drop1peak == 0 then 29:        m ← mod(n + M, 128) 30:        Update F based on C.sub.D1 31:        H ← C, H.sub.D1 ← C.sub.D1, H.sub.D2 ← C.sub.D2 32:        γ.sub.Local ← γ.sub.D1 33:        Start the detector and set I.sub.DBC ← 1 34:        I.sub.drop1peak ← 1 35:       else 36:        I.sub.drop1peak ← 0 37:       end if 38:      end if 39:     end if 40:    end if 41:   end while 42:  end if 43: end procedure

[0152] Simulation Results

[0153] The relative performance of embodiments using a range of different correlator thresholds were evaluated in Matlab simulations. The different threshold values in FIGS. 8 & 9 are the values of the threshold A, but in the simulations the threshold D was also varied, by setting D=A−0.03.

[0154] FIG. 8 shows the sensitivity performance. It simulates the packet error rate (PER) performance with sensitivity from −105 dBm to −85 dBm. According to the simulation, −103 dBm sensitivity should be achievable with 0.01 packet error rate level by lowering the DBC threshold down to around 0.37, and no error floor is observed in high SNR region.

[0155] FIG. 9 shows the selectivity performance. Performance was simulated with a selectivity level from 0 to −20 dB. According to the simulation, the receiver 9 should achieve around −2 dB selectivity performance at 0.01 PER when the DBC threshold is 0.37.

[0156] The approach described herein has thus been shown to provide good performance by exploiting the long repeating preamble to obtain symbol timing and frequency-offset estimates accurately and reliably.

[0157] It will be appreciated by those skilled in the art that the invention has been illustrated by describing one or more specific embodiments thereof, but is not limited to these embodiments; many variations and modifications are possible, within the scope of the accompanying claims.