DRIVING STRUCTURE FOR DISPLAY PANEL

Abstract

The present application discloses a driving structure for display panel, which comprises at least one driving group and at least one control circuit. The driving group is disposed on a display panel. Each of the driving group includes a plurality of drivers. The drivers are coupled to each other in serial. Each of the drivers is coupled to at least one display component of the display panel. The control circuit is disposed on the display panel, coupled to the driving group, and controls the driving group. The driving structure according to the present application is applied to the display panel, that requires no scan lines disposed on the display panel for reducing the complex of the structure of the display panel.

Claims

1. A driving structure for display panel, comprising: at least one driving group, disposed on a display panel, each said driving group including a plurality of drivers coupled in series, and each driver coupled to at least one display component of said display panel; and at least one control circuit, disposed on said display panel, coupled to said driving group, and controlling said driving group.

2. The driving structure of claim 1, wherein said drivers of each said driving group are disposed on said display panel along a direction.

3. The driving structure of claim 1, wherein said at least one driving group includes a plurality of driving groups, and a driver of a driving group of said driving groups is coupled to a driver of another driving group of said driving groups.

4. The driving structure of claim 1, wherein each said driver includes: a storage circuit, coupled to said control circuit, and storing an input data transmitted by said control circuit; and an enable circuit, coupled to said storage circuit, and enabling said storage circuit for receiving said input data; wherein after said enable circuit enables said storage circuit, said enable circuit disables said storage circuit and drives said enable circuit of another driver to enable said storage circuit of said another driver to receive said input data transmitted by said control circuit.

5. The driving structure of claim 4, wherein said control circuit includes a timing controller coupled to said storage circuit for transmitting said input data to said storage circuit; and said timing controller is further coupled to said enable circuit and drives said enable circuit to enable said storage circuit.

6. The driving structure of claim 1, wherein each said driver includes a driving circuit and said driving circuit drives said at least one display component according to an input data.

7. The driving structure of claim 6, wherein said control circuit includes an adjusting circuit coupled to said driving circuit: said adjusting circuit adjusts the intensity of a driving signal output by said driving circuit; and said driving signal drives said display component of said display panel.

8. The driving structure of claim 1, wherein said at least one driving group includes a plurality of driving groups; said at least one control circuit includes a plurality of control circuits; and said control circuits are coupled to said driving groups and control said driving groups.

9. The driving structure of claim 8, wherein said control circuits are coupled in series; after a control circuit of said control circuits receives an input data, said control circuit drives another control circuit of said control circuits to receive said input data.

10. The driving structure of claim 9, wherein each said control circuit comprises: an input interface, receiving said input data; and an enable circuit, coupled to said input interface, and enabling said input interface for receiving said input data; wherein after said enable circuit enables said input interface, said enable circuit disables said input interface and drives said enable circuit of another control circuit to enable said input interface of said another control circuit to receive said input data.

11. The driving structure of claim 1, wherein said control circuit comprises: an input interface, receiving an input data; a buffer, coupled to said input interface, and buffering said input data; and a timing controller, coupled to said buffer, receiving said input data, outputting said input data to said driving group, and driving a driver of said driving group to receive said input data.

12. The driving structure of claim 1, wherein said control circuit is locate in a display area of said display panel

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 shows a schematic diagram of the driving structure according to an embodiment of the present application;

[0007] FIG. 2 shows a block diagram of the control circuit and the driving group according to an embodiment of the present application; and

[0008] FIG. 3 shows a circuit diagram of the storage circuit and the driver according to an embodiment of the present application.

DETAILED DESCRIPTION

[0009] In order to make the structure and characteristics as well as the effectiveness of the present application to be further understood and recognized, the detailed description of the present application is provided as follows along with embodiments and accompanying figures.

[0010] In the specifications and subsequent claims, certain words are used for representing specific circuits. A person skilled in the art should know that hardware manufacturers might use different names to call the same circuit. In the specifications and subsequent claims, the differences in names are not used for distinguishing circuits. Instead, the differences in entire techniques are the guidelines for distinguishing. In the whole specifications and subsequent claims, the word “comprising/including” is an open language and should be explained as “comprising but not limited to”. Besides, the word “couple” includes any direct and indirect electrical connection. Thereby, if the description is that a first device is coupled to a second device, it means that the first device is connected electrically to the second device directly, or the first device is connected electrically to the second device via other device or other connecting means indirectly.

[0011] Please refer to FIG. 1, which shows a schematic diagram of the driving structure according to an embodiment of the present application. As shown in the figure, the driving structure according to the present application is used for driving a display panel 10 to display images. The driving structure comprises at least one driving group 20 and at least one control circuit 30. According to the present embodiment, a plurality of driving groups 20 and a plurality of control circuits 30 are adopted in the driving structure for describing the driving structure according to the present application. The driving groups 20 and the control circuits 30 are disposed on the display panel 10. The control circuits 30 are coupled to the driving groups 20 and control the driving groups 20. According to an embodiment of the present application, each control circuit 30 may be an independent chip. Nonetheless, the present application is not limited to the embodiment. Instead, the control circuits 30 may be integrated into a chip.

[0012] In addition, each driving group 20 includes a plurality of drivers 22 coupled to each other in series. The drivers 22 of each driving group 20 are disposed on the display panel 10 along a direction. According to the present embodiment, the drivers 22 of each driving group 20 are disposed on the display panel 10 along a vertical direction, meaning that the driving groups 20 are disposed on the display panel 10 along a longitudinal direction, and adjacent to one another. Nonetheless, the present application is not limited to the embodiment. According to an embodiment of the present application, each driver 22 may be an independent chip. Nonetheless, the present application is not limited to the embodiment. Each driver 22 is coupled to at least one display component 14 (as shown in FIG. 2) of the display panel 10 for driving the display component 14 to display images. The display component 14 may be a mini LED or a micro LED. The display panel 10 may be a mini LED display panel or a micro LED display panel. Nonetheless, the driving structure according to the present application is applicable not only to the above two display panel types. The control circuits 30 are coupled to the driving groups 20 for controlling the driving groups 20.

[0013] Please refer again to FIG. 1. The control circuit 30 transmits an input data to the driving group 20. According to an embodiment of the present application, the input data may be a serial data including a plurality of pixel data. The drivers 22 of the driving group 20 are all coupled to a bus (not shown in the figure). The control circuit 30 transmits the input data to the bus. The drivers 22 receive the input data via the bus. The drivers 22 receive the input data at different time. Thereby, the pixel data received by the drivers 22 will be different, respectively. For example, when a driver 22 of the driving group 20 receives the input data, the other drivers 22 do not receive the input data. After this driver 22 receives the pixel data of the input data, another driver 22 is driven by this driver 22 to receive the input data for receiving another pixel data of the input data. Since the above two drivers 22 receive the input data at different time, the pixel data received by the two drivers 22 are different and thus driving a plurality of display components 14 of the display panel 10 to display different images. The operations of the other drivers 22 are the same as the above illustration. According to the above description, after a driver 22 receives the pixel data of the input data, another driver 22 is driven by this driver 22 to receive the other pixel data of the input data. Thereby, no scan line is required to be disposed on the display panel 10 and hence simplifying the structure of the display panel 10.

[0014] In addition, according to another embodiment of the present application, a driver 22 of a driving group 20 of the driving groups 20 may be coupled to a driver 22 of another driving group 20. For example, the last driver 22 of each driving group 20 may be coupled to each other for transmitting data or signal. Nonetheless, the present application is not limited to the embodiment. Besides, the driving groups 20 and the control circuits 30 are disposed in a display area of the display panel 10. Nonetheless, the present application is not limited to the embodiment. The control circuits 30 may be disposed in a non-display area of the display panel 10.

[0015] Please refer to FIG. 2, which shows a block diagram of the control circuit and the driving group according to an embodiment of the present application. For convenience, the driving group 20 according to the present embodiment includes two drivers 22. As shown in the figure, the control circuit 30 includes an input interface 32, an enable circuit 33, a buffer 34, a timing controller 36, a register 38, and an adjusting circuit 39. The control circuit 30 is coupled to a host, for example, the microprocessor of an electronic product, for receiving the input data, control commands, or related control parameters. The input interface 32 receives the input data, the control commands, or the control parameters. The enable circuit 33 is coupled to the input interface 32 and enables the input interface 32 according to a received enable signal for driving the input interface 32 to receive the input data, the control commands, or the control parameters.

[0016] Please refer again to FIG. 2. The buffer 34 is coupled to the input interface 32 and the timing controller 36. The input interface 32 transmits the input data to the buffer 34. The buffer 34 buffers the input data and transmits the buffered input data to the timing controller 36. The timing controller 36 transmits the input data to the driving group 22 via the bus and outputs a timing signal to the driver 22 of the driving group 22 for controlling the operation of the driver 22. The register 38 is coupled to the input interface 32, the timing controller 36, and the adjusting circuit 39. The input interface 32 transmits the control parameters to the register 38. The register 38 stores the control parameters and provides the control parameters to the timing controller 36 and the adjusting circuit 39. The tuning controller 36 generates the timing signal according to the control parameters. The adjusting circuit 39 generates an adjusting signal to the driver 22 according to the control parameters for adjusting the intensity of a driving signal generated by the driver 22. The driving signal is used for driving the display components 14 of the display panel 10. The intensity of the driving signal determines the brightness of the display components 14.

[0017] Please refer again to FIG. 2. Each driver 22 includes an enable circuit 24, a storage circuit 26, and a driving circuit 28. The storage circuit 26 is coupled to the timing controller 36 of the control circuit 30 via the bus for receiving the input data transmitted by the timing controller 36. The enable circuit 24 is coupled to the storage circuit 26 and enables the storage circuit 26 for driving the storage circuit 26 to receive and store the input data. According to an embodiment of the present application, the enable circuit 24 enables the storage circuit 26 for a predetermined time. The storage circuit 26 receives the input data in the predetermined time and stores the received input data. The enable circuit 24 disables the storage circuit 26 after the predetermined time. Then, the storage circuit 26 stops receiving the input data.

[0018] For example, the enable circuit 24 of the first driver 22 is coupled to the timing controller 36 of the control circuit 30. The timing controller 36 transmits an enable signal to the enable circuit 24 of the first driver 22 for driving the enable circuit 24 of the first driver 22 to enable the storage circuit 26 receiving the input data. Namely, the timing controller 36 drives the first driver 22 to receive the input data. The above enable signal of the timing controller 36 may be a clock signal. When the enable circuit 24 of the first driver 22 enables the storage circuit 26 of the first driver 22, the enable circuits 24 of the rest drivers 22 disable the storage circuits 26 of the rest drivers 22 and hence no input data will be received. After the enable circuit 24 of the first driver 22 disables the storage circuit 26 of the first driver 22, it transmits an enable signal to the enable circuit 24 of another driver 22. According to an embodiment of the present application, the enable circuit 24 of the first driver 22 transmits an enable signal to the enable circuit 24 of the second driver 22 for driving the enable circuit 24 of the second driver 22 to enable the storage circuit 26 of the second driver 22 to receive the input signal for the predetermined time. Likewise, after the predetermined time, the enable circuit 24 of the second driver 22 disables the storage circuit 26 of the second driver 22 and transmits an enable signal to the enable circuit 24 of another driver 22, for example, the enable circuit 24 of the third driver 22, for enabling the storage circuit 26 of the another driver 22. According to the above illustration, the storage circuits 26 of the drivers 22 receive the input data at different time, which is equivalent to time-division reception of the input data. Thereby, the pixel data in the input data received by the storage circuits 26 of the drivers 22 are different. For example, the pixel data received and stored by the storage circuit 26 of the first driver 22 is different from the pixel data received and stored by the storage circuit 26 of the second driver 22.

[0019] Furthermore, it is not limited to that the timing controller 36 should transmit the enable signal to the enable circuit 24 of the first driver 22 initially. Instead, the timing controller 36 may transmit the enable signal to the enable circuit 24 of another driver 22 according to the requirements, for example, the enable circuit 24 of the second driver 22. Besides, as described above, after the enable circuit 24 of the first driver 22 disables the storage circuit 26 of the first driver 22, the enable circuit 24 of the first driver 22 transmits an enable signal to the enable circuit 24 of the second driver 22. Nonetheless, the present application is not limited to the embodiment. The order of enabling the drivers 22 to receive the input signal may be arranged according to requirements.

[0020] Please refer again to FIG. 2. The driving circuit 28 of each driver 22 is coupled to the storage circuit 26 and at least one display component 14 of the display panel 10. The driving circuit 28 receives the pixel data of the input data stored in the storage circuit 28 and generates a driving signal according to the received pixel data for driving the display component 14 to display images. In addition, the adjusting circuit 39 of the control circuit 30 is coupled to the driving circuits 28 of the drivers 22. The adjusting circuit 39 outputs an adjusting signal to the driving circuits 28 for adjusting the intensity of the driving signals output by the driving circuits 28 and thus adjusting the brightness of the display components 14. According to an embodiment of the present application, the adjusting signal is a voltage. By changing the voltage level, the intensity of the driving signals may be adjusted.

[0021] Please refer again to FIG. 1 and FIG. 2. The control circuits 30 are coupled to each other in series and arranged along a direction. According to the present embodiment, the control circuits 30 are arranged on the display panel 10 in the transverse direction. Nonetheless, the present application is not limited to the present embodiment. According to an embodiment of the present application, the enable circuit 33 of a control circuit 30 of the control circuits 30 enables the input interface 32 for a predetermined time to drive the input interface 32 for receiving the input data within the predetermined time. After the enable circuit 33 enables the input interface 32 for the predetermined time, the enable circuit 33 disables the input interface 32. Then, the input interface 32 stops receiving the input data. Within the predetermine time, the enable circuits 33 of the rest control circuits 30 disable the input interfaces 32 of the rest control circuits 30 and no input data is received. In addition, after the enable circuit 33 enables the input interface 32 for the predetermined time, the enable circuit 33 disables the input interface 32 and transmits an enable signal to the enable circuit 33 of another control circuit 30 for enabling the input interface 32 of another control circuit 30 to receive the input signal. Thereby, the control circuits 30, like the drivers 22, receive the input signals time-divisionally. The input signals received by the control circuits 30 are different. According to another embodiment of the present application, it is not required that the control circuits 30 should be coupled in series. The control circuits 30 may receive the input data from the host (not shown in the figure). The host may control the control circuits 30, respectively, for driving the control circuits 30 to receive the input data. Thereby, it is not required for the control circuits 30 to include the enable circuits 33.

[0022] Please refer to FIG. 3, which shows a circuit diagram of the storage circuit and the driver according to an embodiment of the present application. As shown in the figure, each storage circuit 26 includes a buffer 261, a controller 263, and a plurality of memories 265. The buffer 261 is coupled to the enable circuit 24 and receives the input data Din and a clock signal DCLK. The enable circuit 24 enables the buffer 261 according to the received enable signal and the clock signal DCLK for driving the buffer 261 to receive the input data Din according to the clock signal DCLK. The buffer 261 buffers the input data Din. The buffer 261 and the memories 265 are coupled to a bus (not shown in the figure). The buffer 261 outputs the input data Din to the bus. The memories 265 may receive the input data Din from the bus and store the input data Din. The controller 263 is coupled to the memories 265, receives the clock signal DCLK, and controls the memories 265 to receive the input data Din from the bus at different time, respectively, according to the clock signal DCLK. In other words, the memories 265 receive the input data. Din from the bus time-divisionally. Thereby, the pixel data of the input data. Din received by the memories 265 are different. According to an embodiment of the present application, the controller 263 may be a counter, which counts according to the clock signal DCLK for controlling the memories 265 to receive the input data Din output by the buffer 261 from the bus at different time.

[0023] Please refer again to FIG. 3. The driving circuit 28 includes a plurality of comparators 281, a counter 283, a plurality of level-shift circuits 285, and a plurality of signal generating circuits. The comparators 281 are coupled to the memories 265 and the counter 283. The counter 283 receives a clock signal PWMCLK and counts according to the clock signal PWMCLK for outputting a counting signal. The counting signal changes according to the counting of the counter 283. Each comparator 281 receives the counting signal and pixel data of the input data Din stored in the memory 265 and compares the counting signal and the pixel data. When the pixel data is greater than the counting signal, the comparator 281 outputs a driving level, for example, a high level. According to another embodiment of the present application, when the pixel data is less than the counting signal, the comparator 281 outputs the driving level.

[0024] The level-shift circuits 285 are coupled to the comparators 281, convert the driving levels output by the comparators 281, and generate an enable level. Each signal generating circuit includes a first transistor 286 and a second transistor 288. The first transistor 286 and the second transistor 288 are coupled to each other in series. One terminal of the first transistor 286 is coupled to a terminal of the display component 14. One terminal of the second transistor 288 is coupled to the ground. The level-shift circuits 285 are coupled to the gate of the second transistor 288 of the signal generating circuits and output the enable level to the gate of the second transistor 288 for turning on the second transistor 288 and hence generating the driving signal for driving the display component 14 to emit light and display images. The driving signal is a current flowing from a supply voltage VDD to the ground. The supply voltage VDD is coupled to the other terminal of the display component 14. In addition, the gate of the first transistor 286 is coupled to the adjusting signal VR transmitted by the adjusting circuit 39 of the control circuit 30. The adjusting signal VR may control the turning-on level of the first transistor 286, and thus controlling the magnitude of the current flowing through the display component 14 and controlling the brightness of the display component 14. According to the above description, the time of the comparators 281 continuously generating the driving level is the driving time, namely, the time for driving the display component 14. The driving time determines the brightness of the display component 14.

[0025] Accordingly, the present application conforms to the legal requirements owing to its novelty, nonobviousness, and utility. Thereby, the present application is filed to the patent office for obtaining the allowance of the present application. Thanks a lot.

[0026] However, the foregoing description is only embodiments of the present application, not used to limit the scope and range of the present application. Those equivalent changes or modifications made according to the shape, structure, feature, or spirit described in the claims of the present application are included in the appended claims of the present application.