Lumped element tensor impedance surfaces

Abstract

A tensor impedance surface including a plurality of unit cells, wherein each unit cell includes a dielectric having a thickness, a first surface of the dielectric having a metallic pattern on the first surface, and at least one lumped element coupled between a first point on the metallic pattern and a second point on the metallic pattern. Each unit cell of the plurality of unit cells has a first thickness and has an identical metallic pattern. Each unit cell of the plurality of unit cells is adjacent to one or more unit cells of the plurality of the unit cells.

Claims

1. A tensor impedance surface comprising: a plurality of unit cells, wherein each unit cell comprises: a dielectric having a thickness; a first surface of the dielectric having a metallic pattern on the first surface; and at least one lumped element coupled between a first point on the metallic pattern and a second point on the metallic pattern; wherein each unit cell of the plurality of unit cells has a first thickness; wherein each unit cell of the plurality of unit cells has an identical metallic pattern; and wherein each unit cell of the plurality of unit cells is adjacent to one or more unit cells of the plurality of the unit cells.

2. The tensor impedance surface of claim 1 wherein a second surface of the dielectric opposite the first surface is coupled to a ground.

3. The tensor impedance surface of claim 1 wherein the dielectric comprises a printed circuit board.

4. The tensor impedance surface of claim 1 wherein the at least one lumped element comprises a capacitor, an inductor, a resistor, or a diode.

5. The tensor impedance surface of claim 1: wherein the at least one lumped element comprises a 3-branch structure comprising: at least a first lumped element, a second lumped element, and a third lumped element, the first lumped element coupled between a first point on the metallic pattern and a second point on the metallic pattern, the second lumped element coupled between a third point on the metallic pattern and a fourth point on the metallic pattern, and the third lumped element coupled between a fifth point on the metallic pattern and a sixth point on the metallic pattern.

6. The tensor impedance surface of claim 5: wherein the first lumped element comprises a capacitor, an inductor, a resistor, or a diode; wherein the second lumped element comprises a capacitor, an inductor, a resistor, or a diode; and wherein the third lumped element comprises a capacitor, an inductor, a resistor, or a diode.

7. The tensor impedance surface of claim 6: wherein values of the first lumped element, the second lumped element, the third lumped element and the fourth lumped element are derived by solving $Z_1=\frac{1}{2\left(\mathrm{Yxx}-\mathrm{Yxy}\right)},Z_2=\frac{1}{2\mathrm{Yxy}},Z_3=\frac{1}{2\left(\mathrm{Yyy}-\mathrm{Yxy}\right)}$ $w^{}$ $Y_{\mathrm{sheet}}=\left(\begin{array}{cc}{Y}_{\mathrm{xx}}& Y_{\mathrm{xy}}\\ Y_{\mathrm{yx}}& Y_{\mathrm{yy}}\end{array}\right)=\left(\begin{array}{cc}\frac{1}{2Z_2}+\frac{1}{2Z_3}& \frac{1}{2Z_2}\\ \frac{1}{2Z_2}& \frac{1}{2Z_2}+\frac{1}{2Z_1}\end{array}\right)$ which is equivalent to: $Z_{\mathrm{sheet}}=\left(\begin{array}{cc}\frac{2Z_3\left(Z_1+Z_2\right)}{Z_1+Z_2+Z_3}& \frac{-2Z_1{Z}_3}{Z_1+Z_2+Z_3}\\ \frac{-2Z_1{Z}_3}{Z_1+Z_2+Z_3}& \frac{2Z_1\left(Z_3+Z_2\right)}{Z_1+Z_2+Z_3}\end{array}\right)$ where the first lumped element is Z1; where the second lumped element is Z2; and where the third lumped element is Z3.

8. The tensor impedance surface of claim 1: wherein the at least one lumped element comprises a 4-branch structure comprising: at least a first lumped element, a second lumped element, a third lumped element and a fourth lumped element, the first lumped element coupled between a first point on the metallic pattern and a second point on the metallic pattern, the second lumped element coupled between a third point on the metallic pattern and a fourth point on the metallic pattern, the third lumped element coupled between a fifth point on the metallic pattern and a sixth point on the metallic pattern, and the fourth lumped element coupled between a seventh point on the metallic pattern and a eighth point on the metallic pattern.

9. The tensor impedance surface of claim 8: wherein values of the first lumped element, the second lumped element, the third lumped element and the fourth lumped element are derived by solving $\left(\begin{array}{cc}\frac{1}{2Z2}+\frac{1}{2Z3}+\frac{1}{2Z4}& \frac{1}{2Z2}-\frac{1}{2Z4}\\ \frac{1}{2Z2}-\frac{1}{2Z4}& \frac{1}{2Z2}+\frac{1}{2Z1}+\frac{1}{2Z4}\end{array}\right)=-\left(\begin{array}{cc}Y0\frac{k0}{\mathrm{kz}0}& 0\\ 0& Y0\frac{\mathrm{kz}0}{k0}\end{array}\right)+j*Y1*\cot \left(\mathrm{kz}1*d\right)*\left(\begin{array}{cc}\frac{k1}{\mathrm{kz}1}& 0\\ 0& \frac{\mathrm{kz}1}{k1}\end{array}\right)\frac{1}{\mathrm{kz}1k1}\left(\begin{array}{cc}\left(k1-\mathrm{ky}\right).Math.2& \mathrm{kxky}\\ \mathrm{kx}\mathrm{ky}& \left(k1-\mathrm{kx}\right).Math.2\end{array}\right)$ where the first lumped element is Z1; where the second lumped element is Z2; where the third lumped element is Z3; where the fourth lumped element is Z4; and where Ysheet is the homogenized sheet admittance representing the lumped elements, Y0 is the wave admittance of free space=1/(120*pi ohms), Y1 is the wave admittance in the dielectric medium, k0 is the wavenumber of free space, k1 is the wave number in the dielectric medium, kz0 is the wavenumber component that is normal to the lumped element surface in free space, kz1 is the wavenumber component that is normal to the lumped element surface in the dielectric medium, kx and ky are components of the transverse wavenumber such that k0^2=kx^2+ky^2+kz0^2 and k1^2=kx^2+ky^2+kz1^2, and d is the thickness of the dielectric substrate.

10. The tensor impedance surface of claim 8: wherein the first lumped element comprises a capacitor, an inductor, a resistor, or a diode; wherein the second lumped element comprises a capacitor, an inductor, a resistor, or a diode; wherein the third lumped element comprises a capacitor, an inductor, a resistor, or a diode; and wherein the fourth lumped element comprises a capacitor, an inductor, a resistor, or a diode.

11. The tensor impedance surface of claim 1: wherein the unit cell is configured to control one or more of phase direction, power flow direction, and polarization.

12. A method of providing a tensor impedance surface comprising: providing a plurality of unit cells, wherein each unit cell comprises: a dielectric having a thickness; a first surface of the dielectric having a metallic pattern on the first surface; and at least one lumped element coupled between a first point on the metallic pattern and a second point on the metallic pattern; wherein each unit cell of the plurality of unit cells has a first thickness; wherein each unit cell of the plurality of unit cells has an identical metallic pattern; and wherein each unit cell of the plurality of unit cells is adjacent to one or more unit cells of the plurality of the unit cells.

13. The method of claim 12 wherein a second surface of the dielectric opposite the first surface is coupled to a ground.

14. The method of claim 12 wherein the dielectric comprises a printed circuit board.

15. The method of claim 12 wherein the at least one lumped element comprises a capacitor, an inductor, a resistor, or a diode.

16. The method of claim 12: wherein the at least one lumped element comprises a 3-branch structure comprising: at least a first lumped element, a second lumped element, and a third lumped element, the first lumped element coupled between a first point on the metallic pattern and a second point on the metallic pattern, the second lumped element coupled between a third point on the metallic pattern and a fourth point on the metallic pattern, and the third lumped element coupled between a fifth point on the metallic pattern and a sixth point on the metallic pattern.

17. The method of claim 16: wherein the first lumped element comprises a capacitor, an inductor, a resistor, or a diode; wherein the second lumped element comprises a capacitor, an inductor, a resistor, or a diode; and wherein the third lumped element comprises a capacitor, an inductor, a resistor, or a diode.

18. The method of claim 17: wherein values of the first lumped element, the second lumped element, the third lumped element and the fourth lumped element are derived by solving $Z_1=\frac{1}{2\left(\mathrm{Yxx}-\mathrm{Yxy}\right)},Z_2=\frac{1}{2\mathrm{Yxy}},Z_3=\frac{1}{2\left(\mathrm{Yyy}-\mathrm{Yxy}\right)}$ $w^{}$ $Y_{\mathrm{sheet}}=\left(\begin{array}{cc}{Y}_{\mathrm{xx}}& Y_{\mathrm{xy}}\\ Y_{\mathrm{yx}}& Y_{\mathrm{yy}}\end{array}\right)=\left(\begin{array}{cc}\frac{1}{2Z_2}+\frac{1}{2Z_3}& \frac{1}{2Z_2}\\ \frac{1}{2Z_2}& \frac{1}{2Z_2}+\frac{1}{2Z_1}\end{array}\right)$ which is equivalent to: $Z_{\mathrm{sheet}}=\left(\begin{array}{cc}\frac{2Z_3\left(Z_1+Z_2\right)}{Z_1+Z_2+Z_3}& \frac{-2Z_1{Z}_3}{Z_1+Z_2+Z_3}\\ \frac{-2Z_1{Z}_3}{Z_1+Z_2+Z_3}& \frac{2Z_1\left(Z_3+Z_2\right)}{Z_1+Z_2+Z_3}\end{array}\right)$ where the first lumped element is Z1; where the second lumped element is Z2; and where the third lumped element is Z3.

19. The method of claim 12: wherein the at least one lumped element comprises a 4-branch structure comprising: at least a first lumped element, a second lumped element, a third lumped element and a fourth lumped element, the first lumped element coupled between a first point on the metallic pattern and a second point on the metallic pattern, the second lumped element coupled between a third point on the metallic pattern and a fourth point on the metallic pattern, the third lumped element coupled between a fifth point on the metallic pattern and a sixth point on the metallic pattern, and the fourth lumped element coupled between a seventh point on the metallic pattern and a eighth point on the metallic pattern.

20. The method of claim 19: wherein values of the first lumped element, the second lumped element, the third lumped element and the fourth lumped element are derived by solving $\left(\begin{array}{cc}\frac{1}{2Z2}+\frac{1}{2Z3}+\frac{1}{2Z4}& \frac{1}{2Z2}-\frac{1}{2Z4}\\ \frac{1}{2Z2}-\frac{1}{2Z4}& \frac{1}{2Z2}+\frac{1}{2Z1}+\frac{1}{2Z4}\end{array}\right)=-\left(\begin{array}{cc}Y0\frac{k0}{\mathrm{kz}0}& 0\\ 0& Y0\frac{\mathrm{kz}0}{k0}\end{array}\right)+j*Y1*\cot \left(\mathrm{kz}1*d\right)*\left(\begin{array}{cc}\frac{k1}{\mathrm{kz}1}& 0\\ 0& \frac{\mathrm{kz}1}{k1}\end{array}\right)\frac{1}{\mathrm{kz}1k1}\left(\begin{array}{cc}\left(k1-\mathrm{ky}\right).Math.2& \mathrm{kxky}\\ \mathrm{kx}\mathrm{ky}& \left(k1-\mathrm{kx}\right).Math.2\end{array}\right)$ where the first lumped element is Z1; where the second lumped element is Z2; where the third lumped element is Z3; where the fourth lumped element is Z4; and where Ysheet is the homogenized sheet admittance representing the lumped elements, Y0 is the wave admittance of free space=1/(120*pi ohms), Y1 is the wave admittance in the dielectric medium, k0 is the wavenumber of free space, k1 is the wave number in the dielectric medium, kz0 is the wavenumber component that is normal to the lumped element surface in free space, kz1 is the wavenumber component that is normal to the lumped element surface in the dielectric medium, kx and ky are components of the transverse wavenumber such that k0^2=kx^2+ky^2+kz0^2 and k1^2=kx^2+ky^2+kz1^2, and d is the thickness of the dielectric substrate.

21. The method of claim 19: wherein the first lumped element comprises a capacitor, an inductor, a resistor, or a diode; wherein the second lumped element comprises a capacitor, an inductor, a resistor, or a diode; wherein the third lumped element comprises a capacitor, an inductor, a resistor, or a diode; and wherein the fourth lumped element comprises a capacitor, an inductor, a resistor, or a diode.

22. The method of claim 12: wherein the unit cell is configured to control one or more of phase direction, power flow direction, and polarization.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows an analytical model for a printed-circuit tensor impedance surface (PCTIS) consisting of a sub-wavelength patterned metallic cladding over a grounded dielectric substrate in accordance with the prior art;

(2) FIG. 2 shows a table comparing features of scalar impedance surfaces to features of tensor impedance surfaces in accordance with the prior art;

(3) FIGS. 3A and 3B show diagrams of a lumped element unit cell having a fixed metallic structure with lumped element loading, FIG. 3C shows a circuit model of the unit cell with lumped element loading for a 4-branch structure, or 4 circuit transmission line model, FIG. 3D shows a circuit model of the unit cell with lumped element loading for a 3-branch structure, or 3 circuit transmission line model, and FIGS. 3E and 3F show 3 circuit transmission-line models used to represent a 3-branch structure lumped element unit cell in accordance with the present disclosure;

(4) FIG. 4 shows a design flow for realizing lumped element metasurfaces based on a set of desired properties such as frequency, direction of desired phase flow, direction of desired power flow, and proportion of TM to TE field in accordance with the present disclosure;

(5) FIGS. 5A and 5B show two different dispersion diagrams at 10 GHz for two different tensor surface unit cells with the same physical geometry but different lumped elements for Z1, Z2, and Z3 in accordance with the present disclosure; and

(6) FIG. 6 shows a top view of a tensor impedance surface showing a tensor impedance surface with adjacent unit cells in accordance with the present disclosure.

DETAILED DESCRIPTION

(7) In the following description, numerous specific details are set forth to clearly describe various specific embodiments disclosed herein. One skilled in the art, however, will understand that the presently claimed invention may be practiced without all of the specific details discussed below. In other instances, well known features have not been described so as not to obscure the invention.

(8) The present disclosure describes tensor impedance surfaces capable of achieving a wider range of impedance values and greater degrees of anisotropy than the prior art using printed circuit board-based impedance surfaces, such as those described in References 1, 2 and 12 above. The tensor impedance surfaces of the present disclosure allow control of phase direction, power flow direction, and polarization, and may be realized on a dielectric substrate, which may or may not be grounded. The dielectric substrate may be a printed-circuit board. In the present disclosure unit cells are provided and each unit cell has a metallic pattern on the surface. The metallic pattern may be loaded with surface mount lumped elements, such as capacitors, inductors, diodes or resistors. The present disclosure method of loading the metallic pattern with lumped elements provides an inverse design procedure that allows the lumped element values to be directly derived to provide a desired impedance surface. This is in contrast to the prior art, which requires cataloging the behavior of hundreds or thousands of unit cell geometries through simulation, and then selecting unit cells that approximately provide a desired impedance property.

(9) Impedance surfaces have many applications including electrically-scanned antennas, electromagnetic scattering, reflector arrays, and waveguides, as described in References 3 to 9 above, which are incorporated herein by reference. The present disclosure increases design flexibility by relaxing the constraints on realizable impedance surfaces.

(10) While impedance surfaces properties in the prior art have been achieved by patterning metal over a grounded dielectric substrate, the present disclosure describes devices and methods for achieving a wider range of properties beyond those achievable with just metallic patterning. Impedance surfaces formed in accordance with the present disclosure can have larger impedance ranges and greater ranges of anisotropy than previously available in the prior art using just patterned metallic claddings. Further, a circuit model can be used to aids synthesis of the tensor impedance surfaces, which may also be scalar impedance surfaces. Also, the tensor impedance surfaces of the present disclosure avoid the high fabrication cost, complexity, and losses incurred using prior art varactor loaded impedance surfaces. An added advantage is that the present disclosure allows tensor impedance surfaces to be made thinner since capacitance is no longer dependent on only a substrate thickness. Also, although the present disclosure is used to control surface waves rather than guided transmission line modes, devices designed using the present disclosure may resemble a transmission line loaded with lumped elements.

(11) FIG. 1 shows an analytical model for a printed-circuit tensor impedance surface (PCTIS) consisting of a sub-wavelength patterned metallic cladding 16 on a dielectric substrate 10, which may have a thickness d 12. The side 14 of the dielectric substrate 10 opposite the patterned metallic cladding 16 may be grounded. The dispersion equation of a printed-circuit tensor impedance surface consisting of a patterned metallic cladding over a grounded dielectric substrate in accordance with the prior art is given by the following equation

(12) $Y_{\mathrm{sheet}}\left(\right)=-\left(\begin{array}{cc}Y0\frac{k0}{\mathrm{kz}0}& 0\\ 0& Y0\frac{\mathrm{kz}0}{k0}\end{array}\right)+j*Y1*\cot \left(\mathrm{kz}1*d\right)*\left(\begin{array}{cc}\frac{k1}{\mathrm{kz}1}& 0\\ 0& \frac{\mathrm{kz}1}{k1}\end{array}\right)\frac{1}{\mathrm{kz}1k1}\left(\begin{array}{cc}\left(k1-\mathrm{ky}\right).Math.2& \mathrm{kxky}\\ \mathrm{kx}\mathrm{ky}& \left(k1-\mathrm{kx}\right).Math.2\end{array}\right)$ where Ysheet is the homogenized sheet admittance representing the lumped elements, Y0 is the wave admittance of free space=1/(120*pi ohms), Y1 is the wave admittance in the dielectric medium, k0 is the wavenumber of free space, k1 is the wave number in the dielectric medium, kz0 is the wavenumber component that is normal to the lumped element surface in free space, kz1 is the wavenumber component that is normal to the lumped element surface in the dielectric medium, kx and ky are components of the transverse wavenumber such that k0^2=kx^2+ky^2+kz0^2 and k1^2=kx^2+ky^2+kz1^2, and d is the thickness of the dielectric substrate.

(13) In the prior art, the metallic cladding 16 is modeled as a tensor sheet impedance, as shown in FIG. 1. The values of surface impedance achievable are limited due to substrate thickness d 12 and fabrication tolerances. The sheet impedance is typically found for a given metallic pattern by using an extraction method as described in References 2 and 13 above, which are incorporated herein by reference.

(14) The table in FIG. 2 compares features of scalar impedance surfaces to features of tensor impedance surfaces in the prior art. A scalar impedance surface may be isotropic, provide control of wave speed or the phase front, have unit cells with metallic patterning, use analytic electro-magnetic (EM} and transmission line techniques, and use relatively quick computational techniques. A tensor impedance surface may be anisotropic, and provide control of phase front, power density, power routing, and polarization. Prior art tensor impedance surface may also have unit cells with metallic patterning; however, as discussed above the procedures to attain a desired impedance surface in the prior art are computationally expensive, time consuming and approximate. Properties may be varied by varying geometrical parameters like gap-spacing; however, as discussed above, in the prior art the impedance ranges and anisotropy may be limited due to fabrication tolerances.

(15) FIGS. 3A and 3B show diagrams of a lumped element unit cell having a fixed metallic structure with lumped element loading in accordance with the present disclosure. FIG. 3C shows a circuit model of the unit cell of FIG. 3A with lumped element loading, and shows a 4-branch structure or 4 circuit transmission-line model used to represent the lumped element unit cell in accordance with the present disclosure. FIG. 3D also shows a circuit model of the unit cell of FIG. 3A with lumped element loading, and shows a 3-branch structure or 3 circuit transmission-line model used to represent the lumped element unit cell in accordance with the present disclosure.

(16) Using the circuit model depicted in FIG. 3C, the sheet impedance can be found as a function of lumped circuit elements for a 4-branch structure by using the following dispersion equation.

(17) $Y_{\mathrm{sheet}}=\left(\begin{array}{cc}\frac{1}{2Z2}+\frac{1}{2Z3}+\frac{1}{2Z4}& \frac{1}{2Z2}-\frac{1}{2Z4}\\ \frac{1}{2Z2}-\frac{1}{2Z4}& \frac{1}{2Z2}+\frac{1}{2Z1}+\frac{1}{2Z4}\end{array}\right)$

(18) The dispersion equation to solve then becomes:

(19) $\left(\begin{array}{cc}\frac{1}{2Z2}+\frac{1}{2Z3}+\frac{1}{2Z4}& \frac{1}{2Z2}-\frac{1}{2Z4}\\ \frac{1}{2Z2}-\frac{1}{2Z4}& \frac{1}{2Z2}+\frac{1}{2Z1}+\frac{1}{2Z4}\end{array}\right)=-\left(\begin{array}{cc}Y0\frac{k0}{\mathrm{kz}0}& 0\\ 0& Y0\frac{\mathrm{kz}0}{k0}\end{array}\right)+j*Y1*\cot \left(\mathrm{kz}1*d\right)*\left(\begin{array}{cc}\frac{k1}{\mathrm{kz}1}& 0\\ 0& \frac{\mathrm{kz}1}{k1}\end{array}\right)\frac{1}{\mathrm{kz}1k1}\left(\begin{array}{cc}\left(k1-\mathrm{ky}\right).Math.2& \mathrm{kxky}\\ \mathrm{kx}\mathrm{ky}& \left(k1-\mathrm{kx}\right).Math.2\end{array}\right)$ where Ysheet is the homogenized sheet admittance representing the lumped elements, Y0 is the wave admittance of free space=1/(120*pi ohms), Y1 is the wave admittance in the dielectric medium, k0 is the wavenumber of free space, k1 is the wave number in the dielectric medium, kz0 is the wavenumber component that is normal to the lumped element surface in free space, kz1 is the wavenumber component that is normal to the lumped element surface in the dielectric medium, kx and ky are components of the transverse wavenumber such that k0^2=kx^2+ky^2+kz0^2 and k1^2=kx^2+ky^2+kz1^2, and d is the thickness of the dielectric substrate.

(20) The dispersion equation above can be used to derive the lumped element impedances (Z.sub.n) rather than the surface impedances/admittances (Ysheet/Zsheet matrices). Once the lumped impedances Z1, Z2, Z3, and Z4 are found, the appropriate lumped element values, which may be capacitors, inductors, diodes and/or resistors can be found. Advantageously, lumped elements such as capacitors, inductors, and resistors are low cost and are available in a large range of values. However, such lumped elements are generally only available in discrete values, so that factor can also be taken into account.

(21) The above equations are for a 4-branch structure, but a similar model may be derived for a 3-branch structure, or 3 circuit transmission line model, as shown in FIG. 3D. For a 3-branch structure, the equation for Y.sub.sheet is the following.

(22) $Y_{\mathrm{sheet}}=\left(\begin{array}{cc}{Y}_{\mathrm{xx}}& Y_{\mathrm{xy}}\\ Y_{\mathrm{yx}}& Y_{\mathrm{yy}}\end{array}\right)=\left(\begin{array}{cc}\frac{1}{2Z_2}+\frac{1}{2Z_3}& \frac{1}{2Z_2}\\ \frac{1}{2Z_2}& \frac{1}{2Z_2}+\frac{1}{2Z_1}\end{array}\right)$

(23) which is equivalent to:

(24) $Z_{\mathrm{sheet}}=\left(\begin{array}{cc}\frac{2Z_3\left(Z_1+Z_2\right)}{Z_1+Z_2+Z_3}& \frac{-2Z_1{Z}_3}{Z_1+Z_2+Z_3}\\ \frac{-2Z_1{Z}_3}{Z_1+Z_2+Z_3}& \frac{2Z_1\left(Z_3+Z_2\right)}{Z_1+Z_2+Z_3}\end{array}\right)$

(25) The impedance of the circuit elements may be found in terms of the desired surface admittance, as follows.

(26) $Z_1=\frac{1}{2\left(\mathrm{Yxx}-\mathrm{Yxy}\right)},Z_2=\frac{1}{2\mathrm{Yxy}},Z_3=\frac{1}{2\left(\mathrm{Yyy}-\mathrm{Yxy}\right)}$

(27) FIGS. 3E and 3F show 3 circuit transmission-line models used to represent the lumped element unit cell for a 3-branch structure in accordance with the present disclosure. FIG. 3E shows the circuit model for the transverse electric surface modes, as shown by dotted line 20 in FIG. 3B. FIG. 3F shows the circuit model for the transverse magnetic surface modes, as shown by dotted line 22 in FIG. 3B. The transverse electric circuit model of FIG. 3E needs to be used together with the transverse magnetic circuit model shown in FIG. 3F to capture the mixed modes of the structure. In the circuit models Y.sub.sheet is as shown above for the 3-branch structure and

(28) $\mathrm{Ysurf}=-\left(\begin{array}{cc}Y0\frac{k0}{\mathrm{kz}0}& 0\\ 0& Y0\frac{\mathrm{kz}0}{k0}\end{array}\right)$
The plane 24 with lumped elements is modeled as a homogenous sheet impedance using Y.sub.sheet or equivalently Z.sub.sheet, as shown above.

(29) Lumped element tensor impedance surfaces along with the circuit models aid direct synthesis and provide a complete design flow. FIG. 4 shows a design flow for realizing lumped element metasurfaces based on a set of desired properties. The desired properties may include frequency, direction of desired phase flow, direction of desired power flow, and polarization control by controlling the proportion of TM to TE field.

(30) FIGS. 5A and 5B show examples of two different dispersion diagrams at 10 GHz for two different tensor surface unit cells with the same physical geometry but different lumped elements for Z1, Z2, and Z3. In FIG. 5A the tensor surface unit cells are loaded with all capacitors having values of C1=80 fF, C2=50 fF and C3=0.15 pF. In FIG. 5B the tensor surface unit cells are loaded with 2 capacitors and one inductor having values of C1=0.2 pF, L2=4.5 nH and C3=0.18 pF. In FIGS. 5A and 5B the arrows 40 and 50 represent phase velocity direction, and the arrows 42 and 52 represent the Poynting vector direction, which is the power flow direction. The dispersion diagrams of FIGS. 5A and 5B are anisotropic dispersion diagrams, because an isotropic dispersion diagram would be a perfect circle with the arrows 40 and 42, and the arrows 50 and 52 overlapping exactly at all points along the circle.

(31) FIGS. 5A and 5B demonstrate how with the units cells described in this disclosure, two unit cells, which may look physically identical, can yield two very different sets of dispersion properties. Both unit cells may look like a metallic grid loaded with surface mount lumped elements. The reason for different sets of dispersion properties is because the anisotropic capacitive and inductive loading is achieved using a fixed metal grid but with varying lumped element values.

(32) In prior art, achieving two dramatically different dispersion properties requires that the metallic patterns be geometrically different since the inductance and capacitance in the prior art is achieved from the widths of the metallic gaps and traces. In this disclosure, the inductance and capacitance is achieved primary from the lumped elements with the grid providing a negligible contribution.

(33) A 3-branch structure was used to derive the lumped elements for FIGS. 5A and 5B. The advantage of a 3 branch structure is that fewer lumped elements are needed. However, a 4-branch structure, as illustrated by the example shown in FIGS. 3A and 3B, has more design flexibility because one of the impedances is a free parameter.

(34) FIG. 6 shows a top view of a tensor impedance surface showing a tensor impedance surface 60 with adjacent unit cells 62 in accordance with the present disclosure. Each of the unit cells 62 may have an identical metallic pattern, or a few different metallic patterns. Visually, the tensor impedance surface may look uniform throughout. The surface properties are varied locally at a unit cell 62 by loading the metallic patterns of the unit cell 62 with lumped element values that may be different than the lumped element values for another unit cell 62. The result is an inhomogeneous and anisotropic surface.

(35) Having now described the invention in accordance with the requirements of the patent statutes, those skilled in this art will understand how to make changes and modifications to the present invention to meet their specific requirements or conditions. Such changes and modifications may be made without departing from the scope and spirit of the invention as disclosed herein.

(36) The foregoing Detailed Description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will be apparent to practitioners skilled in the art. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom. Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean one and only one unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the Claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase means for . . . and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase comprising the step(s) of . . . .