Board terminal and board connector

Abstract

A board terminal 1 includes a base material 11 made of a metal material and a plating film 12 covering a surface of the base material 11. The plating film 12 includes an outermost layer 120 having a Sn mother phase 120a and SnPd-based alloy phases 120b dispersed in the Sn mother phase 120a, the Sn mother phase 120a and the SnPd-based alloy phases 120b being present on an outer surface. A Pd content in the outermost layer 120 is not more than 7 atomic %. A board connector 2 includes the board terminal 1 and a housing 20 for holding the board terminal 1.

Claims

1. A board terminal, comprising: a base material made of a metal material; and a plating film covering a surface of the base material; wherein: the plating film includes an outermost layer having a Sn mother phase and Sn-Pd-based alloy phases dispersed in the Sn mother phase, the Sn mother phase and the Sn-Pd-based alloy phases being present on an outer surface; the outermost layer has a Pd content of not more than 7 atomic %, and the outermost layer is in contact with an inner layer having a double layer structure composed of a Ni layer in contact with the base material and a Ni-Sn alloy layer in contact with the Ni layer or is in contact with the base material.

2. A board terminal according to claim 1, wherein: the base material has a fracture surface formed during processing into a terminal shape; and the plating film covers the surface of the base material including the fracture surface.

3. A board terminal according to claim 1, wherein the base material is Cu or Cu alloy.

4. A board terminal according to claim 1, wherein an area ratio of the Sn-Pd alloy phases occupying the outer surface of the outermost layer is not less than 10% and not more than 80%.

5. A board connector, comprising: a board terminal according to claim 1; and a housing for holding the board terminal.

6. A board connector according to claim 5, wherein the board terminal is used by being mounted on a printed circuit board by solder bonding.

7. A board terminal, comprising: a base material made of a metal material; and a plating film covering a surface of the base material, the plating film including an inner layer having a double layer structure composed of a Ni layer in contact with the base material and a Ni-Sn alloy layer in contact with the Ni layer or is in contact with the base material and an outermost layer in contact with the inner layer and having a Sn mother phase and Sn-Pd-based alloy phases dispersed in the Sn mother phase, the Sn mother phase and the Sn-Pd-based alloy phases being present on an outer surface of the outermost layer so that an area ratio of Sn-Pd alloy phases occupying the outer surface is not less than 10% and not more than 80%; wherein: the outermost layer is formed by performing a reflow process after a Pd plating layer having a thickness of not smaller than 10 nm and smaller than 20 nm and a Sn plating layer having a thickness of not smaller than 1 m and not larger than 2m are successively formed, the outermost layer has a Pd content of not more than 7 atomic %.

8. A board terminal according to claim 7, wherein: the base material has a fracture surface formed during processing into a terminal shape; and the plating film covers the surface of the base material including the fracture surface.

9. A board terminal according to claim 7, wherein the base material is Cu or Cu alloy.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram of board terminals and a board connector of a first embodiment.

(2) FIG. 2 is a section along II-II of FIG. 1.

(3) FIG. 3 is a diagram schematically showing a base material and a plating film in the board terminal and the board connector of the first embodiment.

(4) FIG. 4 is a diagram schematically showing a base material and a plating film in a board terminal and a board connector of a second embodiment.

(5) FIG. 5 is a graph showing a measurement result of a friction coefficient of a plated member fabricated in Example 1.

(6) FIG. 6 is a graph showing a relationship between a Pd content in an outermost layer and a zero-cross time.

DETAILED DESCRIPTION

(7) Hereinafter, board terminals and board connectors of embodiments are described using the drawings. Note that the same members are described using the same reference signs.

(8) Board terminals and a board connector of a first embodiment are described using FIGS. 1 to 3. As shown in FIGS. 1 to 3, a board terminal 1 of this embodiment includes a base material 11 made of a metal material and a plating film 12 covering a surface of the base material 11. The plating film 12 includes an outermost layer 120 having a Sn mother phase 120a and SnPd-based alloy phases 120b dispersed in the Sn mother phase 120a, the Sn mother phase 120a and the SnPd-based alloy phases 120b being present on an outer surface. A Pd content in the outermost layer 120 is not more than 7 atomic %. This is described in detail below.

(9) In this embodiment, the board terminal 1 is applied to a board connector 2. The board terminal 1 specifically includes a fitting connection portion 101 to be fitted and connected to a mating terminal (not shown), a board connection portion 102 to be connected to a printed circuit board P and an L-shaped bent portion 103 coupling between the fitting connection portion 101 and the board connection portion 102. The board terminal 1 is formed by bending a Cu or Cu alloy wire material formed with the plating film 12 into an L shape. Note that the board terminal 1 may be formed by, after a Cu or Cu alloy plate material is punched out into a wire shape, forming the plating film 12 on the plate material and bending the plate material into an L shape.

(10) In this embodiment, the plating film 12 specifically includes the outermost layer 120 and an inner layer 121 interposed between the base material 11 and the outermost layer 120. The inner layer 121 has a double layer structure composed of a Ni layer 121a in contact with the base material 11 and a NiSn alloy layer 121b in contact with the Ni layer 121a. The outermost layer 120 is in contact with the NiSn alloy layer 121b constituting this inner layer 121.

(11) Note that the plating film 12 is formed by successively forming a Ni plating layer having a thickness of 1 to 3 m, a Pd plating layer having a thickness of 10 to 20 nm and a Sn plating layer having a thickness of 1 to 2 m on a surface of the base material 11 made of Cu or Cu alloy by an electroplating method and performing a reflow process at a heating temperature of 230 to 400 C.

(12) Further, the board connector 2 of this embodiment includes the above board terminals 1 and a housing 20 for holding the board terminals 1.

(13) In this embodiment, the board connector 2 specifically includes the housing 20 fixed to the printed circuit board P and a plurality of board terminals 1 mounted in the housing 20.

(14) The housing 20 is made of synthetic resin, a receptacle 201 for accommodating a mating connector (not shown) at the time of connection is formed on a front side of the housing 20 and a back wall 202 is integrally formed on the back of the receptacle 201. The board terminals 1 are held by being press-fitted through the back wall 202 of the housing 20.

(15) In the board connector 2, a part of the board terminal 1 projecting into the receptacle 201 is the fitting connection portion 101 to be fitted and connected to a female terminal provided in the mating connector, and an opposite end part serves as the board connection portion 102 to be connected to a land of the printed circuit board P by soldering.

(16) Next, functions and effects of the board terminal and the board connector of this embodiment are described.

(17) The board terminal 1 of this embodiment has the above configuration. Particularly, in the board terminal 1, not only the relatively soft Sn mother phase 120a, but also the SnPd-based alloy phases 120b having a relatively high hardness are present on the outer surface of the outermost layer 120 of the plating film 12. Thus, a friction coefficient on the outer surface of the outermost layer 120 is reduced in the board terminal 1 and an insulation force at the time of connection to the mating terminal can be suppressed to be low.

(18) Further, since the Pd content of the outermost layer 120 is not more than 7 atomic % in the board terminal 1, good solder wettability can be ensured.

(19) Further, the plating film 12 of the board terminal 1 includes the inner layer 121. Thus, it is possible to improve the close contact of the plating film 12 with the base material 11 and suppress the dispersion of base material components into the outermost layer 120 and the like.

(20) The board connector 2 of this embodiment has the above configuration and, particularly, includes the board terminals 1. Thus, the board connector 2 can be connected to the mating connector with a low insertion force. Particularly, since the board connector 2 includes the plurality of board terminals 1 in this embodiment, an increase of the insertion force due to an increase in the number of the terminals at the time of connector connection can be effectively suppressed by reducing the friction of the individual board terminals 1. Further, in the board connector 2, the board terminals 1 can be satisfactorily bonded when being mounted on the printed circuit board P by solder bonding.

(21) A board terminal and a board connector of a second embodiment are described using FIG. 4. As shown in FIG. 4, a board terminal 1 of the second embodiment differs from the board terminal 1 of the first embodiment in that a plating film 12 does not include the inner layer 121 and is composed of an outermost layer 120. Further, a board connector 2 of the second embodiment differs from the board connector 2 of the third embodiment in that the board terminals 1 of the second embodiment are used. The other configuration is as in the first embodiment.

(22) Even if the above configuration is adopted, it is possible to realize a low insertion force and obtain a board terminal with good solder wettability and a board connector using the board terminal.

EXPERIMENTAL EXAMPLES

(23) The present invention is more specifically described using experimental examples below.

Example 1

(24) A Ni plating layer having a thickness of 2.0 m, a Pd plating layer having a thickness of 20 nm and a Sn plating layer having a thickness of 1.0 m were successively formed on a surface of a clean copper board (size of 40 mm100 mm, thickness of 300 m). Thereafter, this is heated at 300 C. in the atmosphere to fabricate a plated member of sample 1.

(25) A cross-section of the obtained plated member of sample 1 was observed by a scanning ion microscope (SIM). As a result, as shown in FIG. 3, a plating film was composed of an outermost layer and an inner layer having a double layer structure. The outermost layer specifically has a Sn mother phase and SnPd-based alloy phases dispersed in the Sn mother phase and the Sn mother phase and the SnPd-based alloy phases were present on the outer surface. Further, the inner layer was specifically composed of two layers, i.e. a Ni layer in contact with a base material and a NiSn alloy layer in contact with the Ni layer. Further, in this experimental example, a Pd content in the outermost layer calculated using the thicknesses of the Sn plating layer and the Pd plating layer before the reflow process, densities and atomic weights of elements was 3.0 atomic %.

(26) Note that, in the fabrication of the plated member of sample 1, only the Sn plating layer having a thickness of 1.0 m was formed to obtain a plated member of comparative sample.

(27) A dynamic friction coefficient was evaluated as an index of a terminal insertion force for the plated members of sample 1 and comparative sample. Specifically, a frictional force was measured using a load cell by holding the plated member in the form of a flat plate and an embossed plated member having a radius of 1 mm in contact in a vertical direction and pulling the embossed plated member in a horizontal direction at a speed of 10 mm/min while applying a load of 5 N in the vertical direction using a piezo actuator. At this time, a pulled distance was set as a friction distance. Then, a value obtained by dividing the above frictional force by the load was set as a friction coefficient.

(28) FIG. 5 shows a measurement result of the friction coefficients of the plated members of sample 1 and comparative sample. As shown in FIG. 5, the plated member of comparative sample is found to exhibit a high friction coefficient since the plating film is composed of the conventional Sn plating film. In contrast, since the plating film had the above configuration in the plated member of sample 1, it was confirmed that the friction coefficient was reduced as compared to the plated member of the comparative sample.

Example 2

(29) Similarly to the fabrication of the plated member of sample 1, plated members of samples 2 to 4 having different Pd contents in the outermost layer were fabricated. At this time, the Pd content was adjusted by setting the thickness of the Sn plating layer at 1.0 m and setting the thickness of the Pd plating layer at 10 nm (sample 2), at 20 nm (sample 3) and at 50 nm (sample 4). The Pd content of sample 2 was 1.6 atomic %, that of sample 3 is 3.0 atomic % and that of sample 4 is 6.4 atomic %.

(30) The plated members of each sample and comparative sample were dipped in a solder bath and a zero cross time was measured using a meniscograph method in accordance with JIS Z 3198-4. The above measurement conditions were; used solder: Sn-3.0Ag-0.5Cu (J3 produced by Ishikawa Metal Co., Ltd.), solder temperature: 250 C., dipping depth: 2 mm, dipping speed: 5 mm/sec and dipping time: 10 sec. The result is shown in FIG. 6.

(31) As shown in FIG. 6, it is found that the zero cross time can be not longer than 2.5 seconds if the Pd content of the outermost layer is not more than 7 atomic %. In other words, if the Pd content of the outermost layer exceeds 7 atomic %, the zero cross time exceeds 2.5 seconds, the solder wettability of the board terminal is deteriorated and connection reliability is reduced. Further, it is also found that the Pd content should be not more than 5.5% to set the zero cross time at 2 seconds or shorter in order to further improve the solder wettability of the board terminal.

(32) Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments and various changes can be made within a range not impairing the gist of the present invention.

(33) For example, an example of applying the above board terminal to the board connector was described in the above embodiments. Without limitation to this, the above board terminal can be formed into an optimal shape and can be used by being directly connected to the printed circuit board without being held in the housing.