Electronic latch, a method for an electronic latch, a frequency division by two and a 4-phase generator

Abstract

The present invention relates to an electronic latch circuit, a method, and a 4-phase generator. The electronic latch circuit comprises an output circuit comprising an output X, and an output Y. The electronic latch circuit further comprises an input circuit, comprising an input A, an input B, and a clock signal input. The input circuit is connected to the output circuit, and configured to select a state of the output circuit from the group of a first state, a second state, and a third state. The input circuit is further configured to select the first state upon detecting a high state on the input B, a transition on the clock signal input from a low state to a high state, and a low state on the input A, and that the electronic latch circuit is in the second state. The input circuit is further configured to select the second state upon detecting a high state on the input A, a low state on the input B, a low state on the clock signal input, and that the electronic latch circuit is in the first state; The input circuit is further configured to select the third state upon detecting a high state on the input A, a transition on the clock signal input from a low state to a high state, and a low state on the input B, and that the electronic latch circuit is in the second state. The input circuit is further configured to select the second state upon detecting a high state on the input A, a low state on the input B, a low state on the clock signal input, and that the electronic latch circuit is in the first state.

Claims

1. A four phase generator for generating four phase signals, comprising a first and a second electronic latch circuit, wherein the first and the second electronic latch circuit each comprises: an output circuit, comprising: an output X; and an output Y; an input circuit, comprising: an input A an input B a clock signal input wherein the input circuit is connected to the output circuit, and configured to select a state of the output circuit from the group of: a first state comprising output of a high state at the output X, and output of a low state at the output Y; a second state comprising output of a high state at the output X and at the output Y; a third state comprising output of output of a low state at the output X and a high state at the output Y; wherein the input circuit is further configured to: select the first state upon detecting a high state on the input B, a transition on the clock signal input from a low state to a high state, and a low state on the input A, and that the electronic latch circuit is in the second state; select the second state upon detecting a high state on the input A, a low state on the input B, a low state on the clock signal input, and that the electronic latch circuit is in the first state; select the third state upon detecting a high state on the input A, a transition on the clock signal input from a low state to a high state, and a low state on the input B, and that the electronic latch circuit is in the second state; select the second state upon detecting a high state on the input B, a low state on the input A, a low state on the clock signal input, and that the electronic latch circuit is in the third state; and wherein the four phase generator further comprises means for receiving a first clock signal at the clock signal input of the first electronic latch circuit, the four phase generator further comprises means for receiving a second clock signal at the clock signal input of the second electronic latch circuit, wherein the second clock signal is the inverse of the first clock signal, wherein the input A of the first electronic latch circuit is connected to the output X of the second electronic latch circuit, the input B of the first electronic latch circuit is connected to the output Y of the second electronic latch, the input A of the second electronic latch circuit is connected to the output Y of the first electronic latch circuit, and the input B of the second electronic latch circuit is connected to the output X of the first electronic latch, wherein a first phase signal is provided at the output X of the first electronic latch circuit, a second phase signal is provided at the output Y of the first electronic latch circuit, a third phase signal is provided at the output X of the second electronic latch circuit, and a fourth phase signal is provided at the output Y of the second electronic latch circuit, wherein in each of the first and second electronic latch circuits: the input circuit comprises a first P-MOS transistor with a gate connected to the input A, and a second P-MOS transistor with a gate connected to the input B, a source of the first P-MOS transistor and a source of the second P-MOS transistor are connected to a supply voltage, a drain of the first P-MOS transistor is connected to a first node of the output circuit, and a source of the second P-MOS transistor is connected a second node of the output circuit, the input circuit comprises a third N-MOS transistor with a gate connected to the clock signal input, a source connected to a second voltage potential, and a drain connected to the output circuit, and the output circuit comprises a regenerative device connected to the first node and to the output X, the regenerative device is further connected to the second node and to the output Y, the regenerative device further comprises a third node connected to the input circuit, the regenerative device comprises a fourth N-MOS transistor with a drain connected to the first node, a gate connected to the second node, and a source connected to the third node, the regenerative device further comprises a fifth N-MOS transistor with a drain connected to the second node, a gate connected to the first node, and a source connected to the third node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram of an electronic latch circuit according to embodiments.

(2) FIG. 2 is a graph illustrating the different signals of an electronic latch circuit according to embodiments.

(3) FIG. 3 is a state diagram illustrating a method according to embodiments.

(4) FIG. 4 is a flow chart illustrating a method according to embodiments.

(5) FIG. 5 is a circuit diagram of a four phase generator according to embodiments.

(6) FIG. 6 is a graph illustrating the different signals of a four phase generator according to embodiments.

DETAILED DESCRIPTION

(7) In this disclosure the definition of logical levels should be interpreted as follows: A low state should be interpreted as a voltage level indicating a value of 0 or logical low. A high state should be interpreted as a voltage level indicating a value of 1 or logical high.

(8) In the following, different aspects will be described in more detail with references to certain embodiments and to accompanying drawings. For purposes of explanation and not limitation, specific details are set forth, such as particular scenarios and techniques, in order to provide a thorough understanding of the different embodiments. However, other embodiments that depart from these specific details may also exist.

(9) FIG. 1 is a circuit diagram of a latch circuit, generally designated 100, according to one embodiment. The latch circuit 100 comprises an input circuit 101 and an output circuit 105. The input circuit 101 comprises an input A 102, and an input B 103 for receiving signals comprising low states or high states from connectable external circuits. The input circuit 101 further comprises a clock signal input 104 configured to receive a clock signal from an external clock circuit. The clock signal provides alternating states between the low state and the high state at a predetermined frequency and duration.

(10) The input circuit 101 further comprises a first MOS transistor (M1) with a gate connected to the input A. A gate of a second MOS transistor (M2) is connected to the input B. A source of the first MOS transistor and source of the second MOS transistor are connected to a supply voltage (108). Finally, a drain of the first MOS transistor is connected to a first node 111 of the output circuit, and a drain of the second MOS transistor is connected a second node 112 of the output circuit.

(11) In this embodiment, the first and the second MOS transistors may be P-MOS transistors.

(12) The input circuit further comprise a third MOS transistor (M3) with a gate connected to the clock signal input 104, a source connected to a second voltage potential (109), and a drain connected to a third node 113 of the output circuit.

(13) The second voltage may in one embodiment be a ground potential. The second voltage may in another embodiment be a potential lower than the supply voltage 108.

(14) The output circuit may further comprise a regenerative device 110 connected to the first node 111 and to the output X 106, the regenerative device is further connected to the second node 112 and to the output Y 107, the latch circuit further comprises a third node 113 connected to the input circuit 101.

(15) The regenerative device 110 comprise a fourth MOS transistor M4 with a drain connected to the first node 111, a gate connected to the second node 112, and a source connected to the third node 113. The regenerative device further comprises a fifth MOS transistor M5 with a drain connected to the second node 112, a gate connected to the first node 111, and a source connected to the third node 113. The third MOS transistor M3, the fourth MOS transistor M4, and the fifth MOS transistor M5 may be N-MOS transistors.

(16) The function of the electronic latch circuit 100 will now be discussed with reference made to FIG. 2 in order to fully disclose the operation of the electronic latch circuit 100 according to FIG. 1.

(17) FIG. 2 illustrates a Spice simulation of the electronic latch circuit 100. The stimuli to the electronic latch circuit 100 in the Spice simulation consists of a clock signal, illustrated in FIG. 2f) connected to the clock signal input 104. Furthermore, the stimuli to the electronic latch circuit 100 further consists of two pulse generators connected to input A 102 and input B 103, respectively. The pulse train signals from these two pulse generators are illustrated in FIG. 2a) and FIG. 2b), respectively. The output X 106 and the output Y 107 from the electronic latch circuit 100, are shown in FIG. 2c) V(X) and FIG. 2d) V(Y). In FIG. 2e) is a signal derived from the output X 106 and the output Y 107, this signal indicates a state of the electronic latch circuit 100 i.e. 1, 2 or 3 based on the output X 106 and the output Y 107. This state will later be discussed with reference made to FIG. 3. The horizontal axes of FIG. 2 are time axes and the corresponding vertical axes indicate voltages between a low voltage indicating a low state and a high voltage indicating a high state.

(18) In order to provide a concise description, it is convenient to introduce a shorthand notation for the signals of the electronic latch circuit 100 as follows. A=0 means that input A 102 is at a low state, indicating a logical 0. A=1 means that input A 102 is at a high state, indicating a logical 1. Hence, CLK=0 should be interpreted as a low state on the clock signal input 104, indicating a logical 0. X=1 should be interpreted as a high state on the output X 106, etc. A transition from A=0 to A=1 is indicated by A=011. The Boolean operator AND is written as &. Thus, A=0 & B=1 indicates a low state on input A 102 and a high state on input B 103.

(19) At a first time t=t1 (201), indicated with a vertical line through the sub plots of FIG. 2, the electronic latch circuit 100 is in a second state S2 (X=1 and Y=1), which can be seen in FIG. 2e). Furthermore, A=1 and B=0, which causes the first MOS transistor M1 to be off, and the second MOS transistor M2 to be on, and CLK=0 which causes the third MOS transistor M3 to be off. This condition pull up the node 112.

(20) At a second time t=t2 (202) the electronic latch circuit 100 changes state from the second state S2 (X=1 and Y=1) to a third state S3 (X=0 and Y=1) at the rising edge of the transition from CLK=011. At the rising edge of the clock signal the regenerate device 110 turns on. The circumstances of the signals A=1 and B=0 increase the probability for the regenerative device 110 to tilt towards pulling down 111, which gives X=0 and accordingly Y=1, as can be seen in FIG. 2c). Consequently the electronic latch circuit 100 changes state from the second state S2 to the third state S3.

(21) At a third time t=t3 (203) the electronic latch circuit 100 change state from the third state S3 to the second state S2. This change of state is initiated upon a falling edge of CLK=1|0, which turns off the third MOS transistor M3. The input A=0 which causes the first MOS transistor M1 turns on, which in turn causes a high state on the first node 111 and on the output X.

(22) At a fourth time t=t4 (204) the electronic latch circuit 100 changes state from the second state S2 to the first state S1, at the rising edge of the transition from CLK=011. At the rising edge of the clock the regenerate device 110 will turn on. The circumstances of the signals A=0 and B=1 increase the probability for the regenerative device to tilt towards pulling down 112, Y=0 and hence X=1, as can be seen in FIG. 2d). Consequently the electronic latch circuit 100 changes state from the second state S2 to the first state S1.

(23) It is possible to define a state machine from the inner workings of the electronic latch circuit 100. A state machine is generally described with a state diagram as shown in FIG. 3, designated 300. This state diagram 300 defines three different states for the output circuit 105, of the electronic latch circuit 100, from the group of:

(24) A first state S1, comprising output of a low state at the output Y 107, and output of a high state at the output X 106.

(25) A second state S2, comprising output of a high state at the output X 106 and at the output Y 107.

(26) A third state S3, comprising output of a high state at the output Y 107, and output of a low state at the output X 106;

(27) Each of these states is illustrated as ellipses in FIG. 3.

(28) The transition from a state to another state is controlled by the input signals to the input circuit 101 as well as by the present state of the output circuit 105. The electronic latch circuit 100 is configured to: Select 306 the first state S1 upon detecting a transition on the clock signal input 104 from a low state to a high state, a high state on the input B 103, a low state on the input A 102, and the output circuit 105 is in the second state S2. This condition can be expressed as CLK=0|1 & B=1 & A=0 & State=S2 using the above defined short-hand notation. Select 304 the second state S2 upon detecting a high state on the input A 102, a low state on the input B 103, a low state on the clock signal input 104, and that the output circuit 105 is in the first state S1. Which is denoted A=1 & CLK=0 & B=0 & State=S1 using the short-hand notation. Select 305 the third state S3 upon detecting a transition on the clock signal input 104 from a low state to a high state, a high state on the input A 102, and a low state on the input B 103, and that the output circuit 105 is in the second state S2. Which is denoted A=1 & CLK=0|1 & B=0 & State=S2. Select 307 the second state S2 upon detecting a high state on the input B 103, a low state on the input A 102, and low state on the clock signal input 104 and that the output circuit 105 is in the third state S3. Which is denoted A=0 & CLK=0 & B=1 & State=S3.

(29) The state diagram 300 may be transformed into a corresponding flowchart shown in FIG. 4, and commonly designated 400. This flowchart discloses a method for an electronic latch circuit 100.

(30) The method comprises: 401: Select the first state S1 upon detecting 404 a high state on the input B 103, a low state on the input A 102, a transition of the clock signal input 104 from a low state to a high state, and that the electronic latch circuit 100 is in the second state S2. 402: Select the second state S2 upon detecting 405 a high state on the input A 102, a low state on the clock signal input 104, a low state on the input B 103, and that the electronic latch circuit 100 is in the first state S1. 403: Select the third state S3 upon detecting 406 a high state on the input A 102, a transition of the clock signal input 104 from a low state to a high state, a low state on the input B 103, and that the electronic latch circuit 100 is in the second state S2. 408: Select the second state S2 upon detecting 407 a high state on the input B 103, a low state on the input A 102, low state on the clock signal input 104, and that the electronic latch circuit 100 is in the third state S3.

(31) In FIG. 5 one embodiment of a 4-phase generator is disclosed, the 4-phase generator is commonly designated 500. The 4-phase generator 500 comprises a first and a second electronic latch circuit 100, 100 according to embodiments of an electronic latch circuit 100.

(32) The clock signals input 104 of the first electronic latch circuit 100 is configured to be connected to a clock generator 501 via a transmission gate 503.

(33) The clock generator 501 is further connected to the clock signal input 104 of the second electronic latch circuit 100 via an inverter 502.

(34) The transmission gate 503 and the inverter 502 may be configured to introduce a delay of the same length to the clock signal. This causes the outputs from the inverter and the transmission gate to be 180 degrees out of phase.

(35) But, the clock signal input 104 of the second electronic latch circuit 100 may of course also be connected to a second clock generator configured to generate a clock signal that is 180 degrees out of phase with respect to the clock generator 501.

(36) The input A 102 of the first electronic latch circuit 100 is connected to the output X 106 of the second electronic latch circuit 100.

(37) The input B 103 of the first electronic latch circuit 100 is connected to the output Y 107 of the second electronic latch 100.

(38) The input A 102 of the second electronic latch circuit 100 is connected to the output Y 107 of the first electronic latch circuit 100, and the input B 103 of the second electronic latch circuit 100 is connected to the output X 106 of the first electronic latch.

(39) This 4-phase generator 500 provides a first phase signal Va at the output X of the first electronic latch circuit 100, a second phase signal Vb at the output Y of the first electronic latch circuit, a third phase signal Vc is provided at the output X of the second electronic latch circuit, and a fourth phase signal Vd is provided at the output Y of the second electronic latch circuit.

(40) Another embodiment of a 4-phase generator may be obtained by modifying the first embodiment of a 4-phase generator disclosed above. This modification involves connecting the input A to output X, the input B to output Y, the output X to input B, and output Y to input A. The primed inputs and outputs belongs to the second electronic latch circuit 100, and the un-primed inputs and outputs belongs to the first electronic latch circuit 100.

(41) In FIG. 6 the four phase signals are shown as outputs from a SPICE simulation of the embodiment of a 4-phase generator disclosed with reference made to FIG. 5.

(42) FIG. 6a) shows the clock signal relayed to the clock signal input 104 of the first electronic latch circuit 100.

(43) FIG. 6b) shows the clock signal relayed to the clock signal input 104 of the second electronic latch circuit 100. This clock signal is the inverse of the clock signal relayed to the clock signal input 104 of the first electronic latch circuit 100.

(44) FIG. 6c) shows the first phase signal Va.

(45) FIG. 6d) shows the second phase signal Vb.

(46) FIG. 6e) shows the third phase signal Vc.

(47) FIG. 6f) shows the fourth phase signal Vd.

(48) The 4-phase generator according to embodiments may provide four phase signals at a higher clock frequency compared to other 4-phase generators for a given generation of transistors with a minimum gate length.

(49) The 4-phase generator according to embodiments may provide a more efficient solution that requires less power due to the smaller total transistor peripheri used in the electronic latch circuit 100 compared to the prior art.

(50) The above mentioned and described embodiments are only given as examples and should not be limiting. Other solutions, uses, objectives, and functions within the scope of the accompanying patent claims may be possible.