BAND-PASS ANALOG-TO-DIGITAL CONVERTER USING BIDIRECTIONAL VOLTAGE-CONTROLLED OSCILLATOR

Abstract

The present disclosure discloses a band-pass analog-to-digital converter (ADC) using a bidirectional voltage-controlled oscillator (VCO) including a first converter configured to receive an analog input signal and quantize the analog input signal according to a first clock signal to output a first digital signal, a second converter configured to receive the analog input signal and quantize the analog input signal in a time-interleaving manner according to a second clock signal, which has a phase opposite to that of the first clock signal, to output a second digital signal, and a multiplexer configured to receive the first and second digital signals and select one of the two signals in response to the first clock signal to finally output a digital output signal.

Claims

1. A band-pass analog-to-digital converter (ADC) using a bidirectional voltage-controlled oscillator (VCO), the ADC comprising: a first converter configured to receive an analog input signal and quantize the analog input signal according to a first clock signal to output a first digital signal; a second converter configured to receive the analog input signal and quantize the analog input signal in a time-interleaving manner according to a second clock signal, which has a phase opposite to that of the first clock signal, to output a second digital signal; and a multiplexer configured to receive the first and second digital signals and select one of the two signals in response to the first clock signal to finally output a digital output signal.

2. The ADC of claim 1, wherein the first converter comprising: a first sampling/holding part configured to sample a voltage level of the analog input signal at a rising edge of the first clock signal and hold the voltage level of the analog input signal until a next rising edge of the first clock signal to output a first sampling signal; a first VCO configured to output a first oscillation signal having a frequency proportional to a voltage level of the first sampling signal in response to a third clock signal and a fourth clock signal each having a frequency of half of a frequency of the first clock signal; and a first counter configured to count the number of pulse signals in the first oscillation signal to output the first digital signal.

3. The ADC of claim 2, wherein the first VCO comprising: a first time delayer configured to delay a time of the first sampling signal by operating a plurality of inverters connected in a forward direction or a plurality of inverters connected in a reverse direction according to a clock signal applied by receiving the first sampling signal; and a first oscillation frequency controller connected to the first time delayer and configured to control a frequency of the first oscillation signal using a frequency of the first sampling signal to output a voltage swing.

4. The ADC of claim 3, wherein the first time delayer comprising: a first delayer configured to delay the time of the first sampling signal by supplying a power supply voltage to the plurality of inverters, which are built-in and connected in the forward direction, and simultaneously operating the plurality of inverters when the third clock signal is applied; and a second delayer configured to delay the time of the first sampling signal by supplying the power supply voltage to the plurality of inverters, which are built-in and connected in the reverse direction, and simultaneously operating the plurality of inverters when the fourth clock signal having a phase opposite to that of the third clock signal is applied.

5. The ADC of claim 4, wherein at a time point at which the applied clock signal is changed from the third clock signal to the fourth clock signal: a voltage of the first oscillation signal at a corresponding node is held; and a phase of the first oscillation signal is changed and proceeds in a direction opposite to a direction in which the phase initially proceeds.

6. The ADC of claim 2, wherein the first counter counts rising edges of the pulse signals in the first oscillation signal.

7. The ADC of claim 1, wherein the second converter comprising: a second sampling/holding part configured to sample a voltage level of the analog input signal at a rising edge of the second clock signal and hold the voltage level of the analog input signal until a next rising edge of the second clock signal to output a second sampling signal; a second VCO configured to output a second oscillation signal having a frequency proportional to a voltage level of the second sampling signal in response to a third clock signal and a fourth clock signal each having a frequency of half of a frequency of the second clock signal; and a second counter configured to count the number of pulse signals in the second oscillation signal to output the second digital signal.

8. The ADC of claim 7, wherein the second VCO comprising: a second time delayer configured to delay a time of the second sampling signal by operating a plurality of inverters connected in a forward direction or a plurality of inverters connected in a reverse direction according to a clock signal applied by receiving the second sampling signal; and a second oscillation frequency controller connected to the second time delayer and configured to control a frequency of the second oscillation signal using a frequency of the second sampling signal to output a voltage swing.

9. The ADC of claim 8, wherein the second time delayer comprising: a first delayer configured to delay the time of the second sampling signal by supplying a power supply voltage to the plurality of inverters, which are built-in and connected in the forward direction, and simultaneously operating the plurality of inverters when the third clock signal is applied, and a second delayer configured to delay the time of the second sampling signal by supplying the power supply voltage to the plurality of inverters, which are built-in and connected in the reverse direction, and simultaneously operating the plurality of inverters when the fourth clock signal having a phase opposite to that of the third clock signal is applied.

10. The ADC of claim 9, wherein at a time point at which the applied clock signal is changed from the third clock signal to the fourth clock signal: a voltage of the second oscillation signal at a corresponding node is held; and a phase of the second oscillation signal is changed and proceeds in a direction opposite to a direction in which the phase initially proceeds.

11. The ADC of claim 7, wherein the second counter counts rising edges of the pulse signals in the second oscillation signal.

12. A band-pass analog-to-digital converter (ADC) using a bidirectional voltage-controlled oscillator (VCO), the ADC comprising: a first converter configured to quantize an analog input signal according to a first clock signal to output a first digital signal; a second converter configured quantize the analog input signal in a time-interleaving manner according to a second clock signal to output a second digital signal; and a multiplexer configured to receive the first and second digital signals and select one of the two signals in response to the first clock signal to finally output a digital output signal.

13. The ADC of claim 12, wherein the first converter comprising: a first sampling/holding part configured to sample a voltage level of the analog input signal at a rising edge of the first clock signal and hold the voltage level of the analog input signal until a next rising edge of the first clock signal to output a first sampling signal; a first VCO configured to output a first oscillation signal having a frequency proportional to a voltage level of the first sampling signal in response to a third clock signal and a fourth clock signal each having a frequency of half of a frequency of the first clock signal; and a first counter configured to count the number of pulse signals in the first oscillation signal to output the first digital signal.

14. The ADC of claim 13, wherein the first VCO comprising: a first time delayer configured to delay a time of the first sampling signal by operating a plurality of inverters connected in a forward direction or a plurality of inverters connected in a reverse direction according to a clock signal applied by receiving the first sampling signal; and a first oscillation frequency controller connected to the first time delayer and configured to control a frequency of the first oscillation signal using a frequency of the first sampling signal to output a voltage swing.

15. The ADC of claim 14, wherein the first time delayer comprising: a first delayer configured to delay the time of the first sampling signal by supplying a power supply voltage to the plurality of inverters, which are built-in and connected in the forward direction, and simultaneously operating the plurality of inverters when the third clock signal is applied; and a second delayer configured to delay the time of the first sampling signal by supplying the power supply voltage to the plurality of inverters, which are built-in and connected in the reverse direction, and simultaneously operating the plurality of inverters when the fourth clock signal having a phase opposite to that of the third clock signal is applied.

16. The ADC of claim 15, wherein at a time point at which the applied clock signal is changed from the third clock signal to the fourth clock signal: a voltage of the first oscillation signal at a corresponding node is held; and a phase of the first oscillation signal is changed and proceeds in a direction opposite to a direction in which the phase initially proceeds.

17. The ADC of claim 12, wherein the second converter comprising: a second sampling/holding part configured to sample a voltage level of the analog input signal at a rising edge of the second clock signal and hold the voltage level of the analog input signal until a next rising edge of the second clock signal to output a second sampling signal; a second VCO configured to output a second oscillation signal having a frequency proportional to a voltage level of the second sampling signal in response to a third clock signal and a fourth clock signal each having a frequency of half of a frequency of the second clock signal; and a second counter configured to count the number of pulse signals in the second oscillation signal to output the second digital signal.

18. The ADC of claim 17, wherein the second VCO comprising: a second time delayer configured to delay a time of the second sampling signal by operating a plurality of inverters connected in a forward direction or a plurality of inverters connected in a reverse direction according to a clock signal applied by receiving the second sampling signal; and a second oscillation frequency controller connected to the second time delayer and configured to control a frequency of the second oscillation signal using a frequency of the second sampling signal to output a voltage swing.

19. The ADC of claim 18, wherein the second time delayer comprising: a first delayer configured to delay the time of the second sampling signal by supplying a power supply voltage to the plurality of inverters, which are built-in and connected in the forward direction, and simultaneously operating the plurality of inverters when the third clock signal is applied, and a second delayer configured to delay the time of the second sampling signal by supplying the power supply voltage to the plurality of inverters, which are built-in and connected in the reverse direction, and simultaneously operating the plurality of inverters when the fourth clock signal having a phase opposite to that of the third clock signal is applied.

20. The ADC of claim 19, wherein at a time point at which the applied clock signal is changed from the third clock signal to the fourth clock signal: a voltage of the second oscillation signal at a corresponding node is held; and a phase of the second oscillation signal is changed and proceeds in a direction opposite to a direction in which the phase initially proceeds.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above and other features and advantages will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:

[0046] FIG. 1 is a block diagram of a conventional analog-to-digital converter (ADC) using a voltage-controlled oscillator (VCO);

[0047] FIG. 2 is a graph illustrating amplitudes of intrinsic first-order noise-shaping with respect to a change in frequency at an output stage of the conventional ADC using a VCO illustrated in FIG. 1;

[0048] FIG. 3 is a schematic block diagram of a band-pass ADC using a bidirectional VCO according to the present disclosure;

[0049] FIG. 4 is an internal circuit diagram of a first VCO (120) in the ADC illustrated in FIG. 3;

[0050] FIG. 5 is an internal circuit diagram illustrating an operation that is activated according to a clock signal applied to the first VCO (120) illustrated in FIG. 3;

[0051] FIG. 6 is a graph illustrating a phase of a first oscillation signal (OS1), which is inverted at a time point when the clock signal is changed and proceeds, when the circuit illustrated in FIG. 3 is driven;

[0052] FIG. 7 is a two-dimensional graph illustrating relative phase changes in an output signal of the VCO when the circuit illustrated in FIG. 4 is driven;

[0053] FIG. 8 is a set of timing diagrams illustrating waveforms and phases of an output signal at each node according to a change in clock signal when the circuit illustrated in FIG. 3 is driven;

[0054] FIG. 9 is a waveform diagram illustrating an experimental result of a q-noise signal output with respect to a change in operating frequency of a first converter (100) or a second converter (200) when the circuit illustrated in FIG. 3 is driven; and

[0055] FIG. 10 is a waveform diagram illustrating an experimental result of a q-noise signal and an effective signal output with respect to a change in operating frequency when the circuit illustrated in FIG. 3 is driven.

[0056] In the following description, the same or similar elements are labeled with the same or similar reference numbers.

DETAILED DESCRIPTION

[0057] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0058] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “includes”, “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. In addition, a term such as a “unit”, a “module”, a “block” or like, when used in the specification, represents a unit that processes at least one function or operation, and the unit or the like may be implemented by hardware or software or a combination of hardware and software.

[0059] Reference herein to a layer formed “on” a substrate or other layer refers to a layer formed directly on top of the substrate or other layer or to an intermediate layer or intermediate layers formed on the substrate or other layer. It will also be understood by those skilled in the art that structures or shapes that are “adjacent” to other structures or shapes may have portions that overlap or are disposed below the adjacent features.

[0060] In this specification, the relative terms, such as “below”, “above”, “upper”, “lower”, “horizontal”, and “vertical”, may be used to describe the relationship of one component, layer, or region to another component, layer, or region, as shown in the accompanying drawings. It is to be understood that these terms are intended to encompass not only the directions indicated in the figures, but also the other directions of the elements.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0062] Preferred embodiments will now be described more fully hereinafter with reference to the accompanying drawings. However, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0063] FIG. 3 is a schematic block diagram of a band-pass analog-to-digital converter (ADC) using a bidirectional voltage-controlled oscillator (VCO) according to the present disclosure, and the ADC includes a first converter 100, a second converter 200, and a multiplexer 300.

[0064] The first converter 100 includes a first sampling/holding part 110, a first VCO 120, and a first counter 130, and the second converter 200 includes a second sampling/holding part 210, a second VCO 220, and a second counter 230.

[0065] FIG. 4 is an internal circuit diagram of the first VCO 120 in the ADC illustrated in FIG. 3, and the first VCO 120 includes a first time delayer including a first delayer 121 and a second delayer 122, and a first oscillation frequency controller 123.

[0066] The first delayer 121 includes a plurality of inverters connected in a forward direction from an input stage to an output stage, and the second delayer 122 includes a plurality of inverters connected in a reverse direction from an output stage to an input stage, and the first oscillation frequency controller 123 includes a variable current source I.sub.s.

[0067] FIG. 5 is an internal circuit diagram illustrating an operation that is activated according to a clock signal applied to the first VCO 120 illustrated in FIG. 3, and illustrates a case (FIG. 5A) in which the applied clock signal is a first pulse ϕ.sub.1 and a case (FIG. 5B) in which the applied clock signal is a second pulse ϕ.sub.2.

[0068] FIG. 6 is a graph illustrating a phase of a first oscillation signal OS1, which is inverted at a time point when the clock signal is changed and proceeds when the circuit illustrated in FIG. 3 is driven.

[0069] Since a configuration and a function of each component of the second VCO 220 are the same as those of the first VCO 120, in FIGS. 4 to 6, only the configuration and the function of each component of the first VCO 120 are described, and the contents thereof are applied to the second VCO 220.

[0070] FIG. 7 is a two-dimensional graph illustrating relative phase changes in an output signal of the VCO when the circuit illustrated in FIG. 4 is driven.

[0071] FIG. 8 is a set of timing diagrams illustrating waveforms and phases of an output signal at each node according to a change in clock signal when the circuit illustrated in FIG. 3 is driven.

[0072] A structure and function of each component of the band-pass ADC using a bidirectional VCO according to the present disclosure will be described below with reference to FIGS. 3 and 8.

[0073] In FIGS. 3 and 8, X1[n] and X2[n] refer to signals generated by an analog input signal x(t) respectively passing through the first and second sampling/holding parts 110 and 210, OS1 and OS2 respectively represent output signals of the first and second VCOs 120 and 220, and Y1[n] and Y2[n] respectively represent output signals of the first and second counters 130 and 230.

[0074] As shown in FIG. 8, a first clock signal CLK1 and a second clock signal CLK2 have opposite phases while each having a frequency of half of a sampling frequency, and a third clock signal CLK3 and a fourth clock signal CLK4 have opposite phases while each having a frequency of half of each of the first clock signal CLK1 and the second clock signal CLK2.

[0075] A sampling signal is represented by a square wave having a voltage level similar to that of a waveform of the analog input signal.

[0076] The first converter 100 receives the analog input signal x(t) and quantizes the analog input signal x(t) according to the first clock signal CLK1 to output a first digital signal Y1[n].

[0077] The second converter 200 receives the analog input signal x(t) and quantizes the analog input signal x(t) in a time-interleaving manner according to the second clock signal CLK2 to output a second digital signal Y2[n].

[0078] That is, when the analog input signal x(t) is input, the first and second sampling/holding parts 110 and 210 hold a voltage level value of the analog input signal x(t) at rising edges of the first and second clock signals CLK1 and CLK2 until next rising edges thereof to output first and second sampling signals X1(n) and X2(n), respectively.

[0079] The first and second VCOs 120 and 220 receive the first and second sampling signals X1(n) and X2(n) and provide the first and second oscillation signals OS1 and OS2, each of which has a frequency proportional to the voltage level of the sampling signal, to the first and second counters 130 and 230, respectively.

[0080] The first and second counters 130 and 230 count the number of rising edges present in the first and second oscillation signals OS1 and OS2 for one period of the sampling clock signal to provide the first and second digital signals Y1[n] and Y2[n], respectively.

[0081] The multiplexer 300 receives the first and second digital signals Y1[n] and Y2[n] from the first and second counters 130 and 230 and selects one of the two signals in response to the first clock signal CLK1 to finally output a digital output signal y[n].

[0082] FIG. 9 is a waveform diagram illustrating an experimental result of a q-noise signal output with respect to a change in operating frequency of the first converter 100 or the second converter 200 when the circuit illustrated in FIG. 3 is driven.

[0083] FIG. 10 is a waveform diagram illustrating an experimental result of a q-noise signal and an effective signal output with respect to a change in operating frequency when the circuit illustrated in FIG. 3 is driven.

[0084] Operations of the band-pass ADC using a bidirectional VCO according to an embodiment of the present disclosure will be described in detail with reference to FIGS. 3 to 10.

[0085] The first sampling/holding part 110 samples a voltage level of the analog input signal x(t) at a rising edge of the first clock signal CLK1 and holds a value of the voltage level until a next rising edge to output the first sampling signal X1[n].

[0086] The first VCO 120 outputs the first oscillation signal OS1 having a frequency proportional to the voltage level of the first sampling signal X1[n] in response to the third clock signal CLK3 and the fourth clock signal CLK4.

[0087] That is, as shown in FIG. 5A, when the first pulse 1,that is, the third clock signal CLK3, is applied to the first VCO 120, a power supply voltage is supplied to the first delayer 121 of the first time delayer, and the first oscillation frequency controller 123 is connected to the first delayer 121 so that the plurality of inverters connected in the forward direction operate simultaneously.

[0088] Accordingly, the first oscillation signal OS1 is output as a voltage swing regulated at a frequency of the first sampling signal X1[n], which is an input signal.

[0089] On the other hand, as shown in FIG. 5B, when the second pulse ϕ.sub.2 having a phase opposite to that of the third clock signal CLK3 is applied to the first VCO 120, that is, the fourth clock signal CLK4 is applied to the first VCO 120, the power supply voltage is supplied to the second delayer 122 of the first time delayer, and the first oscillation frequency controller 123 is connected to the second delayer 122 so that the plurality of inverters connected in the reverse direction operate simultaneously.

[0090] Accordingly, as shown in FIG. 6, at a time point at which the applied clock signal is changed from the third clock signal CLK3 to the fourth clock signal CLK4, a voltage of the first oscillation signal OS1 at the corresponding node is held, and a phase of the first oscillation signal OS1 is changed and proceeds in a direction opposite to a direction in which the phase initially proceeds.

[0091] Thus, a starting point of a next phase becomes a time point obtained by subtracting a residual phase remaining after the current sampling is performed from 2π.

[0092] In FIG. 7, ϕ.sub.x[n] represents a phase proceeding during a current clock signal, ϕ.sub.q[n] represents a residual phase after current sampling is performed, and ϕ.sub.q[n−1] represents a residual phase remaining after previous sampling is performed.

[0093] Further, proceeding in a direction opposite to a direction in which the phase originally proceeds may be viewed as a process proceeding in an initial direction as the phase proceeds to points symmetrical about a y-axis.

[0094] At this point, since edges must be counted with respect to 2π, that is, a positive x-axis, the first and second counters 130 and 230 must count rising edges after the direction of the phase is changed.

[0095] Accordingly, under the condition of 0<ϕ.sub.q[n−1]<π, the counted digital output y[n] is expressed as Equation 1,

[00001]$\begin{array}{cc}y\left[n\right]=\frac{1}{2\pi }\left({\varphi }_x\left[n\right]+\left(2\pi -{\varphi }_q\left[n\right]\right)-{\varphi }_q\left[n-1\right]\right)& \left[\mathrm{Equation}1\right]\end{array}$

[0096] When the digital output y[n] calculated in Equation 1 is z-transformed, the digital output y[n] is expressed as Equation 2.

[00002]$\begin{array}{cc}Y\left(z\right)=\frac{1}{2\pi }\left({\Phi }_x\left(z\right)-\left(1+z^{-1}\right){\Phi }_q\left(z\right)\right)& \left[\mathrm{Equation}2\right]\end{array}$

[0097] In FIG. 3, the first counter 130 counts the number of pulse signals in the first oscillation signal OS1 to output the first digital signal Y1[n].

[0098] Meanwhile, the second sampling/holding part 210 samples a voltage level of the analog input signal x(t) at a rising edge of the second clock signal CLK2 having a phase opposite to that of the first clock signal CLK1 and holds a value of the voltage level until a next rising edge to output the second sampling signal X2[n].

[0099] The second VCO 220 outputs the second oscillation signal OS2 having a frequency proportional to the voltage level of the second sampling signal X2[n].

[0100] The second counter 230 counts the number of pulse signals in the second oscillation signal OS2 to output the second digital signal Y2[n].

[0101] The multiplexer 300 selects one of the first digital signal Y1[n] and the second digital signal Y2[n] in response to the first clock signal CLK1 to finally output the digital output y[n].

[0102] A phase in each of the first VCO 120 and the second VCO 220 is proportional to the number of pulses in the oscillation signal in the corresponding period, as shown in FIG. 8.

[0103] Accordingly, since the bidirectional VCO structure of the present disclosure is a structure in which time-interleaving is performed in both directions in the same VCO as compared with a unidirectional VCO structure, quantization noise is reduced.

[0104] Further, as shown in FIG. 9, since q-noise according to the change in operating frequency is low pass filtered, a noise transfer function that may not be generated with a conventional VCO-based ADC structure, in which quantization noise is high-pass filtered, may be generated.

[0105] Further, as shown in FIG. 10, instead of band-rejecting the q-noise according to the change in operating frequency, an effective signal is band-pass filtered. This is in contrast to the structure of the conventional VCO-based ADC, which requires time-interleaving on at least four channels to produce a band-pass ADC.

[0106] Thus, according to the present disclosure, power consumption may be reduced, and interleaving spurs caused by a mismatch between interleaving channels or gain errors may be prevented in advance.

[0107] Further, unlike a conventional method of digital-converting an analog input signal after down-converting the analog input signal using a mixer, it is possible to directly perform a radio frequency (RF) or intermediate frequency conversion, thereby sufficiently utilizing the advantages of digital signal processing which is relatively much easier than analog signal processing.

[0108] As such, the present disclosure provides a band-pass ADC using a bidirectional VCO suitable for sampling high-frequency signals by implementing a VCO structure in the ADC in a bidirectional time-interleaving manner and directly performing an RF or intermediate frequency conversion without performing down-conversion using a mixer.

[0109] Accordingly, the number of VCOs required for band-pass noise shaping is reduced to half so that power efficiency may be improved several times as compared with a conventional VCO-based ADC.

[0110] Further, as compared with a conventional VCO-based ADC, the number of channels is reduced to half so that influence due to interleaving spurs caused by a mismatch between interleaving channels or gain errors may be minimized.

[0111] Further, unlike a conventional VCO-based ADC using a mixer, it is possible to sufficiently utilize the advantages of digital signal processing in which signal processing is relatively easy.

[0112] According to the present disclosure, by employing a structure in which time-interleaving is performed in both directions in the same VCO, the number of VCOs required for band-pass noise shaping is reduced to half so that power efficiency can be improved several times as compared with a conventional VCO-based ADC.

[0113] Further, as compared with a conventional VCO-based ADC, the number of channels can be reduced to half so that influence due to interleaving spurs caused by a mismatch between interleaving channels or gain errors can be minimized.

[0114] Further, unlike a conventional VCO-based ADC using a mixer, it is possible to directly perform an RF or intermediate frequency conversion, thereby sufficiently utilizing the advantages of digital signal processing which is relatively much easier than analog signal processing.

[0115] While the present disclosure has been described with reference to the embodiments illustrated in the figures, the embodiments are merely examples, and it will be understood by those skilled in the art that various changes in form and other embodiments equivalent thereto can be performed. Therefore, the technical scope of the disclosure is defined by the technical idea of the appended claims The drawings and the forgoing description gave examples of the present invention. The scope of the present invention, however, is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the invention is at least as broad as given by the following claims.