RADIO FREQUENCY RECEIVER

Abstract

A radio frequency receiver device comprises: a receiver input arranged to receive signals having one or more frequency components within a frequency spectrum; a filter having a filter output impedance; and an amplifier comprising: an amplifier input (134a, 134b) connected to the filter output; an amplifier output 72a, 72b); at least one radio frequency input transistor (144a, 144b); and a feedback circuit including at least one feedback resistor (146a, 146b). The device is arranged to be selectably operable in: a first mode wherein the amplifier has first feedback resistance and transconductance values respectively such that the amplifier input impedance and the filter output impedance are substantially the same; and a second mode having second feedback resistance and transconductance values such that upon connection of a predetermined external impedance matching circuit (160) between the filter and the amplifier, the amplifier input impedance and the filter output impedance are substantially the same.

Claims

1. A radio frequency receiver device comprising: a receiver input arranged to receive signals having one or more frequency components within a frequency spectrum; a filter having a filter output impedance; and an amplifier comprising: an amplifier input connected to the filter output; an amplifier output; at least one radio frequency input transistor; and a feedback circuit including at least one feedback resistor, said feedback circuit being connected between the amplifier input and the amplifier output; wherein the device is arranged to be selectably operable in: a first mode wherein the amplifier has first feedback resistance and transconductance values respectively such that the amplifier input impedance and the filter output impedance are substantially the same; and a second mode wherein the amplifier has second feedback resistance and transconductance values respectively such that upon connection of a predetermined external impedance matching circuit between the filter and the amplifier, the amplifier input impedance and the filter output impedance are substantially the same.

2. The device as claimed in claim 1, wherein a noise figure associated with the device when it is operated in the first mode is substantially equal to the noise figure when it is operated in the second mode with the predetermined external impedance matching circuit connected.

3. The device as claimed in claim 1, wherein a gain associated with the device when it is operated in the first mode is substantially equal to the gain when it is operated in the second mode with the predetermined external impedance matching circuit connected.

4. The device as claimed in claim 1, wherein the amplifier further comprises: a mirror transistor arranged to form a current mirror arrangement with the at least one radio frequency input transistor; and a variable current source operable to set the current flowing through the current mirror arrangement to either a first current in the first mode or a second current in the second mode.

5. The device as claimed in claim 1, wherein the amplifier comprises first and second radio frequency input transistors in parallel, wherein the first radio frequency input transistor has a first aspect ratio and is in series with a first selection transistor, and the second radio frequency input transistor has a second aspect ratio and is in series with a second selection transistor, and wherein the first and second aspect ratios are different.

6. The device as claimed in claim 1, wherein the feedback circuit comprises first and second feedback resistors in parallel, wherein the first feedback resistor is in series with a first switch and wherein the second feedback resistor is in series with a second switch, the first and second switches being arranged such that while one switch is closed, the other is open.

7. The device as claimed in claim 1, wherein the amplifier is a low noise amplifier.

8. The device as claimed in claim 1, wherein the feedback circuit further includes at least one feedback capacitor.

9. The device as claimed in claim 1, wherein the radio frequency receiver device further comprises a downconversion mixer connected to the output of the amplifier.

10. The device as claimed in claim 9, comprising an analogue baseband filter connected to an output of the downconversion mixer.

11. The device as claimed in claim 10, wherein said analogue baseband filter comprises a low pass filter.

12. The device as claimed in claim 10, comprising an analogue-to-digital converter connected to an output of the analogue baseband filter.

13. The device as claimed in claim 1, wherein the amplifier input is single-ended.

14. The device as claimed in claim 1, wherein the amplifier input is differential.

15. The device as claimed in claim 1, wherein the amplifier output is single-ended.

16. The device as claimed in claim 1, wherein the amplifier output is differential.

17. The device as claimed in claim 1, further comprising a plurality of amplifiers and a plurality of filters, wherein the input of each amplifier is connected to the output of a corresponding filter such that in the first mode each amplifier has first feedback resistance and transconductance values respectively such that the input impedance of each amplifier and the output impedance of the filter to which said amplifier is connected are substantially the same; and in the second mode each amplifier has second feedback resistance and transconductance values respectively such that upon connection of predetermined external impedance matching circuits between each amplifier and its corresponding filter, the input impedance of each amplifier and the output impedance of the filter to which said amplifier is connected are substantially the same.

18. The device as claimed in claim 1, wherein the filter is a bandpass filter.

19. The device as claimed in claim 1, comprising a radio frequency integrated circuit.

20. A radio frequency receiver device comprising: a receiver input arranged to receive signals having one or more frequency components within a frequency spectrum; a plurality of filters each having a filter output impedance; and a plurality of amplifiers each comprising: an amplifier input connected to the output of a corresponding one of the plurality of filters; an amplifier output; at least one radio frequency input transistor; and a feedback circuit including at least one feedback resistor, said feedback circuit being connected between the amplifier input and the amplifier output; wherein the device is arranged to be selectably operable in: a first mode wherein each amplifier has first feedback resistance and transconductance values respectively such that each amplifier input impedance is substantially the same as the output impedance of the corresponding filter; and a second mode wherein each amplifier has second feedback resistance and transconductance values respectively such that upon connection of a predetermined external impedance matching circuit between each amplifier and the corresponding filter, each amplifier input impedance is substantially the same as the output impedance of the corresponding filter.

21. The device as claimed in claim 20, wherein a noise figure associated with the device when it is operated in the first mode is substantially equal to the noise figure when it is operated in the second mode with the predetermined external impedance matching circuit connected between each amplifier and the corresponding filter.

22. The device as claimed in claim 20, wherein a gain associated with the device when it is operated in the first mode is substantially equal to the gain when it is operated in the second mode with the predetermined external impedance matching circuit connected between each amplifier and the corresponding filter.

Description

[0035] Certain embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

[0036] FIG. 1 shows a schematic diagram of radio frequency receiver device;

[0037] FIG. 2 shows a multi-band radio frequency receiver device;

[0038] FIG. 3 shows a prior art amplifier arrangement with on-chip impedance matching;

[0039] FIG. 4 shows a prior art amplifier arrangement with off-chip impedance matching;

[0040] FIG. 5 shows an amplifier arrangement for use within a radio frequency receiver device in accordance with an embodiment of the present invention;

[0041] FIG. 6 shows an amplifier arrangement with current source controlled transconductance in accordance with an embodiment of the invention;

[0042] FIG. 7 shows an amplifier arrangement with aspect ratio controlled transconductance in accordance with an embodiment of the invention;

[0043] FIGS. 8A and 8B show amplifier arrangements with configurable feedback resistance in accordance with an embodiment of the invention;

[0044] FIG. 9 shows a differential amplifier arrangement with a variable current source in accordance with an embodiment of the invention;

[0045] FIG. 10 shows the differential amplifier arrangement of FIG. 9 with an external impedance matching circuit connected;

[0046] FIG. 11 shows a differential amplifier arrangement with a fixed current source in accordance with an embodiment of the invention; and

[0047] FIG. 12 shows the differential amplifier arrangement of FIG. 11 with an external impedance matching circuit connected.

[0048] FIG. 1 shows a radio frequency receiver 2 that includes a radio frequency integrated circuit (RFIC) 4. The receiver 2 is arranged such that radio frequency signals can be received by an antenna 6. The received signals are filtered using a bandpass filter 8, external to the RFIC 4, before being input to the RFIC 4.

[0049] The RFIC 4 comprises a fully differential low-noise amplifier (LNA) 10 which takes a differential input from the filter 8 (the filter 8 comprising a balun that converts the unbalanced signal from the antenna 6 to a balanced signal) and produces a differential output which is input to a pair of quadrature mixers 12a, 12b. Each of these mixers 12a, 12b is provided with either an in-phase or quadrature version of a local oscillator signal produced by a local oscillator 20 and shifted either 0 or 90 by phase shifter 18.

[0050] These mixers produce fully differential in-phase (or I) and quadrature (or Q) signals that are filtered by low-pass filters 14a, 14b before being converted to digital signals by analogue-to-digital convertors 16a, 16b respectively. The resulting digital I and Q signals are then further processed using a digital demodulator 22.

[0051] FIG. 2 shows a multi-band version of the radio frequency receiver device 2 that is arranged to receive signals across a number of frequency ranges within the radio frequency spectrum. As with the receiver of FIG. 1, the antenna 6 receives the radio frequency signals, which are then input to three different bandpass filters 8a, 8b, 8c that are each arranged with a different passband so as to select the desired frequency ranges while rejecting signals outside these ranges. Each filter 8a, 8b, 8c is connected to a respective fully differential LNA 10a, 10b, 10c which amplify the respective filtered signals prior to processing by the demodulation circuit as discussed previously with reference to FIG. 1.

[0052] Each of the filters 8, 8a, 8b, 8c must be impedance matched with their respective low-noise amplifiers 10, 10a, 10b, 10c in order to prevent the generation of undesirable ripples in the passbands of the filters and to maximise power transfer (i.e. reducing the amount of signal reflection that occurs at the interface between the filters 8, 8a, 8b, 8c and the LNAs 10, 10a, 10b, 10c). Two methods of achieving the matched impedance will be described with reference to FIGS. 3 and 4 below.

[0053] Aside from matching the LNA input impedance to the filter impedance, a desirable LNA 10, 10a, 10b, 10c should have a low noise figure (NF) and be sufficiently linear across its operating range of frequencies. In addition, the LNAs 10, 10a, 10b, 10c desirably have sufficiently high gain (A.sub.r) in order to maintain a high signal-to-noise ratio (SNR). The noise figure (NF) and third-order input-referred intercept point (IIP3)a good measure of circuit linearityof a typical radio receiver 4 are given below with reference to Equations 1 and 2 respectively:

[00001] $\begin{matrix} NF = {NF}_{LNA} + \frac{{NF}_{2} - 1}{{(\frac{A_{v, LNA}}{2})}^{2}} .Math. .Math. Noise .Math. .Math. figure .Math. .Math. NF .Math. .Math. of .Math. .Math. an .Math. .Math. integrated .Math. .Math. radio .Math. .Math. frequency .Math. .Math. receiver .Math. .Math. device .Math. .Math. including .Math. .Math. an .Math. .Math. LNA & Equation .Math. .Math. 1 \\ \frac{1}{IIP .Math. .Math. 3} = \frac{1}{IIP .Math. .Math. 3_{LNA}} + \frac{A_{v, LNA}^{2}}{IIP .Math. .Math. 3_{2}} .Math. .Math. Third .Math. - .Math. order .Math. .Math. input .Math. - .Math. referred .Math. .Math. intercept .Math. .Math. point .Math. .Math. IIP .Math. .Math. 3 .Math. .Math. of .Math. .Math. an .Math. .Math. integrated .Math. .Math. radio .Math. .Math. frequency .Math. .Math. receiver .Math. .Math. device .Math. .Math. including .Math. .Math. an .Math. .Math. LNA & Equation .Math. .Math. 2 \end{matrix}$

wherein: NF.sub.LNA is the LNA NF, A.sub.v,LNA is the LNA voltage gain, IIP3.sub.LNA is the LNA IIP3, NF.sub.2 is the combined NF of the circuits following the LNA (mixers 12a, 12b; low-pass filters 14a, 14b; and ADCs 16a, 16b), and IIP3.sub.2 is the combined IIP3 of the circuits following the LNA.

[0054] FIG. 3 shows an amplifier arrangement with on-chip impedance matching (biasing details are omitted for clarity), known in the art per se. In this arrangement, the LNA 110 comprises: an input terminal 34; an output terminal 36; an n-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) radio frequency (RF) input transistor 44a; an nMOSFET cascode transistor 48 with a gate terminal 38; a feedback resistor 46a; a feedback capacitor 52; a DC block capacitor 50; and a resistor-inductor-capacitor (RLC) resonance arrangement including a resistor 58, an inductor 56 and a capacitor 54. As can be seen from FIG. 3, all of the components within the amplifier 110 are on the on-chip side 32 of the LNA 110 and no components are present on the off-chip side 30. The amplifier 10 is connected between a power supply rail 40 and ground 42.

[0055] At radio frequencies, it is assumed that the feedback capacitor 52 and the DC block capacitor 50 act as short circuits. It is also assumed that the inductor 56 and capacitor 54 are chosen so as to resonate at the principal frequency of interest f.sub.0 for which the LNA 110 is designed e.g. the central frequency of the frequency range to be received, as per Equation 3 below:

[00002] $\begin{matrix} f_{0} = \frac{1}{2 .Math. .Math. \sqrt{L_{L} .Math. C_{L}}} .Math. .Math. Resonant .Math. .Math. frequency .Math. .Math. f_{0} .Math. .Math. of .Math. .Math. LC .Math. .Math. resonator & Equation .Math. .Math. 3 \end{matrix}$

wherein L.sub.L is the inductance of the inductor 56 and C.sub.L is the capacitance of the capacitor 54.

[0056] Due to the negative feedback arrangement, the LNA input resistance R.sub.in at f.sub.0 is given by Equation 4 below:

[00003] $\begin{matrix} R_{in} = \frac{R_{F .Math. .Math. 1} + R_{L}}{g_{m .Math. .Math. 1} .Math. R_{L}} .Math. .Math. LNA .Math. .Math. input .Math. .Math. resistance .Math. .Math. at .Math. .Math. f_{0} & Equation .Math. .Math. 4 \end{matrix}$

wherein: R.sub.F1 is the resistance of the feedback resistor 46a; g.sub.m1 is the transconductance of the RF input transistor 44a; and R.sub.L is the resistance of the resonance resistor 58.

[0057] In order to match impedances, the LNA input resistance R.sub.in must be equal to the source resistance (R.sub.s, i.e. usually 50) or the resistance at which the filter 8 is designed to be terminated.

[0058] With matched impedances (R.sub.in=R.sub.s), the voltage gain (A.sub.v) and noise figure (NF) of the LNA 110 shown in FIG. 3 can be approximated as per Equations 5 and 6 below (wherein is a noise constant, typically taken to be for long-channel MOSFETs):

[00004] $\begin{matrix} A_{v} = \frac{R_{F .Math. .Math. 1}}{R_{s}} .Math. .Math. Voltage .Math. .Math. gain .Math. .Math. A_{v} .Math. .Math. with .Math. .Math. matched .Math. .Math. impedance & Equation .Math. .Math. 5 \\ NF = 1 + \frac{}{g_{m .Math. .Math. 1} .Math. R_{s}} + \frac{{(1 + g_{m .Math. .Math. 1} .Math. R_{s})}^{2}}{g_{m .Math. .Math. 1}^{2} .Math. R_{F .Math. .Math. 1} .Math. R_{s}} .Math. .Math. Noise .Math. .Math. figure .Math. .Math. NF .Math. .Math. with .Math. .Math. matched .Math. .Math. impedance & Equation .Math. .Math. 6 \end{matrix}$

[0059] Assuming g.sub.m1R.sub.s>>1, NF can be written as per Equation 7:

[00005] $\begin{matrix} NF = 1 + \frac{}{g_{m .Math. .Math. 1} .Math. R_{s}} + \frac{R_{s}}{R_{F .Math. .Math. 1}} .Math. .Math. Approximation .Math. .Math. of .Math. .Math. noise .Math. .Math. figure .Math. .Math. NF .Math. .Math. with .Math. .Math. matched .Math. .Math. impedance & Equation .Math. .Math. 7 \end{matrix}$

[0060] By way of contrast, FIG. 4 shows an amplifier arrangement with off-chip impedance matching, known in the art per se. In this case, the components on the on-chip side 32 of the LNA 210 are largely the same as the on-chip side 32 of the LNA 110 in FIG. 3; however the feedback resistor 46b and the RF input transistor 44b have resistance value R.sub.F2 and transconductance value gm.sub.2 respectively.

[0061] In contrast to FIG. 3, the LNA 210 shown in FIG. 4 has an external impedance matching circuit 60 connected between the on-chip side of the LNA 210 and the filter (not shown) i.e. the filtered signals from the filter pass from the input terminal 34 through the external impedance matching circuit 60 prior to input into the on-chip input of the amplifier 210. The external impedance matching circuit 60 itself comprises a ladder network of an impedance matching capacitor 62 and a impedance matching inductor 64. It will however be appreciated that this is simply one example of an impedance matching circuit and any such impedance matching circuit falls within the scope of the present invention.

[0062] In this case, the impedance 82 looking into the on-chip components of the LNA 210 is designed to be larger than the input impedance 80 looking into the external impedance matching circuit 60. The ratio of these impedances is denoted as N.sup.2 in Equation 8 below:

[00006] $\begin{matrix} N^{2} = \frac{R_{EQ}}{R_{in}} = \frac{R_{EQ}}{R_{s}} .Math. .Math. Ratio .Math. .Math. of .Math. .Math. impedances .Math. .Math. for .Math. .Math. off .Math. - .Math. chip .Math. .Math. impedance .Math. .Math. .Math. .Math. matching & Equation .Math. .Math. 8 \end{matrix}$

wherein: R.sub.EQ is the impedance 82 looking into the on-chip part of the LNA 210, R.sub.in is the input impedance 80 of the entire LNA 210 including the external impedance matching circuit 60, and N>1. It is assumed that the external impedance matching circuit 60 is designed such that its input impedance R.sub.in is equal to the source impedance R.sub.s (i.e. the impedance of the filter 8).

[0063] In addition, at the frequency of interest f.sub.0, the LNA 210 load impedance forms a parallel resonance circuit and the impedance 82 looking into the on-chip part of the LNA 210 at f.sub.0 is given as per Equation 9:

[00007] $\begin{matrix} R_{EQ} = \frac{R_{F .Math. .Math. 2} + R_{L}}{g_{m .Math. .Math. 2} .Math. R_{L}} .Math. .Math. Input .Math. .Math. resistance .Math. .Math. looking .Math. .Math. into .Math. .Math. the .Math. .Math. on .Math. - .Math. chip .Math. .Math. part .Math. .Math. of .Math. .Math. .Math. the .Math. .Math. LNA .Math. .Math. at .Math. .Math. f_{0} & Equation .Math. .Math. 9 \end{matrix}$

[0064] With the impedance of the filter 8 matched to the LNA input resistance 80 (i.e. R.sub.in=R.sub.s), the voltage gain (A.sub.v) and noise figure (NF) of the LNA 210 shown in FIG. 4 can be approximated as per Equations 10 and 11 below:

[00008] $\begin{matrix} A_{v} = N \frac{R_{F .Math. .Math. 2}}{R_{EQ}} = \sqrt{\frac{R_{EQ}}{R_{s}}} .Math. \frac{R_{F .Math. .Math. 2}}{R_{EQ}} .Math. .Math. Voltage .Math. .Math. gain .Math. .Math. of .Math. .Math. LNA .Math. .Math. 210 .Math. .Math. with .Math. .Math. off .Math. - .Math. chip .Math. .Math. .Math. impedance .Math. .Math. matching .Math. .Math. shown .Math. .Math. in .Math. .Math. FIG . .Math. 4 & Equation .Math. .Math. 10 \\ NF = 1 + \frac{R_{LOSS}}{R_{s}} + \frac{}{g_{m .Math. .Math. 2} .Math. R_{EQ}} + \frac{{(1 + g_{m .Math. .Math. 2} .Math. R_{EQ})}^{2}}{g_{m .Math. .Math. 2}^{2} .Math. R_{F .Math. .Math. 2} .Math. R_{EQ}} .Math. .Math. Noise .Math. .Math. figure .Math. .Math. of .Math. .Math. LNA .Math. .Math. 210 .Math. .Math. with .Math. .Math. off .Math. - .Math. chip .Math. .Math. impedance .Math. .Math. .Math. matching .Math. .Math. shown .Math. .Math. in .Math. .Math. FIG . .Math. 4 & Equation .Math. .Math. 11 \end{matrix}$

wherein: N is the voltage gain in the matching circuit;

[00009] $\frac{R_{F .Math. .Math. 2}}{R_{EQ}}$

is the gain from the LNA on-chip input to the LNA output; and R.sub.LOSS represents resistive losses in the external impedance matching circuit 60.

[0065] A comparison of the performance of conventional on-chip and off-chip impedance matching solutions as described with reference to FIGS. 3 and 4 above is discussed below. It is assumed that the LNA resonant load component values (R.sub.L, L.sub.L, and C.sub.L) are equal in both arrangements. It is also assumed that in both arrangements, the LNA input resistance (R.sub.in) is matched to the source resistance (R.sub.s=50). Furthermore, it is assumed that both LNAs are designed for equal voltage gain

[00010] $A_{v} = \frac{v_{out}}{v_{in}} .$

[0066] By equating the voltage gains of the LNAs 110, 210 with on- and off-chip impedance matching (see Equations 5 and 10 respectively) in accordance with the principle behind the present invention, Equations 12 and 13 may be derived as shown below:

[00011] $\begin{matrix} Equating .Math. .Math. the .Math. .Math. voltage .Math. .Math. gains .Math. .Math. of .Math. .Math. LNAs .Math. .Math. with .Math. .Math. on .Math. - .Math. .Math. and .Math. .Math. off .Math. - .Math. chip .Math. .Math. impedance .Math. .Math. matching \\ .Math. \frac{R_{F .Math. .Math. 1}}{R_{s}} = \sqrt{\frac{R_{EQ}}{R_{s}}} .Math. \frac{R_{F .Math. .Math. 2}}{R_{EQ}} & Equation .Math. .Math. 12 \end{matrix}$

from which:

R.sub.F2=NR.sub.F1

Equation 13: Relationship Between Feedback Resistance Values Needed for On- and Off-Chip Impedance Matching

[0067] Similarly, the relation between the transconductances of the RF input transistors 44a, 44b needed for on- and off-chip impedance matching respectively are given as per Equations 14 and 15 below:

[00012] $\begin{matrix} Equating .Math. .Math. the .Math. .Math. voltage .Math. .Math. gains .Math. .Math. of .Math. .Math. LNAs .Math. .Math. with .Math. .Math. on .Math. - .Math. .Math. and .Math. .Math. off .Math. - .Math. chip .Math. .Math. impedance .Math. .Math. matching \\ .Math. g_{m .Math. .Math. 2} = (R_{F .Math. .Math. 1} + \frac{R_{L}}{N}) .Math. \frac{g_{m .Math. .Math. 1}}{N (R_{F .Math. .Math. 1} + R_{L})} & Equation .Math. .Math. 14 \end{matrix}$

from which if R.sub.F1>>R.sub.L:

[00013] $\begin{matrix} Relationship .Math. .Math. between .Math. .Math. transconductance .Math. .Math. values .Math. .Math. needed .Math. .Math. for .Math. .Math. on .Math. - .Math. .Math. and .Math. .Math. off .Math. - .Math. chip .Math. .Math. impedance .Math. .Math. matching \\ .Math. g_{m .Math. .Math. 2} \frac{g_{m .Math. .Math. 1}}{N} & Equation .Math. .Math. 15 \end{matrix}$

[0068] It may be seen that when designed for equal voltage gain, the resistive feedback (RFB) LNA 210 with off-chip impedance matching (wherein the impedance matching circuit 60 has impedance scaling factor of N.sup.2) allows scaling up of the resistance of the feedback resistor 46b by N compared to the feedback resistor 46a in the LNA 110 with on-chip matching. Likewise, the transconductance of the RF input transistor 44b in the LNA 210 with off-chip impedance matching can be scaled down approximately by a factor of N compared to the RF input transistor 44a in the LNA 110 with on-chip matching.

[0069] In saturation mode, the transconductance of an RF input transistors 44a, 44b can be written as per Equation 16:

[00014] $\begin{matrix} Transconductance .Math. .Math. of .Math. .Math. RF .Math. .Math. input .Math. .Math. transistor .Math. .Math. in .Math. .Math. saturation .Math. .Math. mode \\ .Math. g_{m .Math. .Math. 2} = \frac{2 .Math. I_{DS}}{V_{GS} - V_{t}} = \sqrt{2 .Math. .Math. .Math. C_{ox} .Math. \frac{W}{L} .Math. I_{DS}} & Equation .Math. .Math. 16 \end{matrix}$

wherein, with reference to the RF input transistors 44a, 44b: I.sub.DS is the drain-source current; V.sub.GS is the gate-source voltage; V.sub.t is the threshold voltage; C.sub.ox is the oxide capacitance;

[00015] $\frac{W}{L}$

is the aspect ration; and is the charge carrier mobility.

[0070] Thus, for example, when designed for equal effective gate-source voltage (V.sub.GSV.sub.t) so as to guarantee the same IIP3 and voltage gain A.sub.v in both configurations, the drain-source current in the LNA 210 with off-chip impedance matching can be scaled down about by a factor of N compared to the LNA 110 with on-chip matching. Alternatively, when designed for equal aspect ratio

[00016] $(\frac{W}{L} .Math.),$

the grain-source current in the LNA 210 with off-chip impedance matching can be scaled down about by a factor of N.sup.2 compared to the LNA 110 with on-chip matching.

[0071] However, typically the voltage-to-current conversion at the RF input transistor 44a, 44b limits the IIP3 of the LNA 110, 210. This results in lower IIP3 in the LNA 210 with off-chip matching compared to the LNA 110 with on-chip matching. Nevertheless, in practice, employing an LNA 210 with off-chip input impedance matching can result in tens of percentage savings (typically around 40%) in power consumption compared to the LNA 110 with complete on-chip input impedance matching. Of course, this advantage comes with the cost of external matching components as discussed previously. However it will be appreciated that, at least with some portable devices, low power consumption may be more important than the bill of materials, and thus utilising off-chip, external impedance matching circuits may be a preferred option.

[0072] By using Equations 13 and 14 and assuming that gm.sub.1R.sub.s>>1, the NF of the LNA 210 with off-chip impedance matching can be written in terms of the transconductance gm.sub.1 of the RF input transistor 44a and the resistance R.sub.F1 of the feedback resistor 46a of the LNA 110 with on-chip matching as per Equation 17:

[00017] $\begin{matrix} Noise .Math. .Math. figure .Math. .Math. of .Math. .Math. LNA .Math. .Math. 210 .Math. .Math. with .Math. .Math. off .Math. - .Math. chip .Math. .Math. matching .Math. .Math. in .Math. .Math. terms .Math. .Math. of .Math. .Math. the .Math. .Math. transconductance .Math. .Math. and .Math. .Math. feedback .Math. .Math. resistance .Math. .Math. associated .Math. .Math. with .Math. .Math. on .Math. - .Math. chip .Math. .Math. matching \\ .Math. NF = 1 + \frac{R_{LOSS}}{R_{s}} + \frac{}{{Ng}_{m .Math. .Math. 1} .Math. R_{s}} + \frac{{({Ng}_{m .Math. .Math. 1} .Math. R_{s} + 2)}^{2}}{{Ng}_{m .Math. .Math. 1}^{2} .Math. R_{s} .Math. R_{F .Math. .Math. 1}} & Equation .Math. .Math. 17 \end{matrix}$

[0073] By using Equation 17, the NF of the LNA 210 using off-chip matching network can be now easily compared to the NF of the LNA 110 with on-chip matching (see Equation 5). It can be seen that the NF of the LNA 210 with off-chip matching includes a term R.sub.LOSS due to resistive losses in the external impedance matching circuit 60, which is not present in the LNA 110 with on-chip matching. This term is usually relatively small, since the matching network can be implemented using high quality factor (or Q-factor) components (i.e. the inductors 64 and capacitors 62) which have relatively low losses associated therewith. It can also be seen that that the second term representing the noise contribution due to the RF input transistor 44b is lower by a factor of N than in the LNA 110 with on-chip matching. However, it can be seen that the last term relating to the noise in feedback resistor 46b is larger compared to the LNA 110 using on-chip matching.

[0074] FIG. 5 shows an amplifier arrangement 510 for use within a radio frequency receiver device in accordance with an embodiment of the present invention. The Applicant has appreciated that a device that could be designed with the ability to have both on- or off-chip impedance matching, while exhibiting the same voltage gain A.sub.v, noise figure NF and linearity characteristics for the entire radio receiver in both configurations would be very advantageous. In practice, this means that an LNA 510 with configurable input impedance matching should exhibit approximate the same voltage gain A.sub.v, noise figure NF and linearity (measured using the IIP3) in both configurations, i.e. both with on- and off-chip matching.

[0075] Similarly to the LNAs 110, 210 described with reference to FIGS. 3 and 4, the LNA 510 illustrated conceptually in FIG. 5 comprises: an input terminal 34; an output terminal 36; an nMOSFET cascode transistor 48 with a gate terminal 38; a feedback capacitor 52; a DC block capacitor 50; and a resistor-inductor-capacitor (RLC) resonance arrangement including a resistor 58, an inductor 56 and a capacitor 54. As can be seen from FIG. 5, all of the components of the amplifier 510 are on the on-chip side 32 and no components are present on the off-chip side 30. Of course, in the case of an external matching network being used, there will be additional external components connected on the off-chip side 30 that are not shown in this particular example). The amplifier 510 is connected between a power supply rail 40 and ground 42.

[0076] However, in contrast to the LNAs 110, 210 described previously, the LNA 510 embodying the present invention comprises an nMOSFET RF input transistor 44 with configurable transconductance as indicated by the arrow through the transistor symbol. The feedback resistor 46 arranged in the feedback path of the LNA 510 is also configurable. In this particular instance, configurable means that the transconductance of the RF input transistor 44 and the resistance of the feedback resistor 46 can be set to either a first pair of values gm.sub.1 and R.sub.F1 or to a second pair of values gm.sub.2 and R.sub.F2 depending on whether it is to be used with on-chip or off-chip impedance matching respectively. As discussed earlier, in practice, R.sub.F1<R.sub.F2 and gm.sub.1>gm.sub.2.

[0077] Of course, the LNA 510 in FIG. 5 is a simplified conceptual illustration as transistors with configurable transconductance are not a component typically available per se. However, the Applicant has devised methods for altering the transconductance of the RF input transistor 44 as will be described below with reference to FIGS. 7 and 8. The Applicant has also devised methods for altering the resistance of the feedback resistor 46 as will be described with reference to FIGS. 8A and 8B.

[0078] FIG. 6 shows an amplifier arrangement with current source controlled transconductance in accordance with an embodiment of the invention. Here, a current source 66 is used to bias the RF input transistor 44. A mirror transistor 62 forms a simple current mirror with the RF input transistor 44, which sets the bias current for the RF input transistor 44. The bias resistor 64 isolates the bias circuit (i.e. the current source 66 and mirror transistor 62) from the LNA input terminal 34 at RF frequencies. As discussed previously, the transconductance of RF input transistor 44 needs to be configured or switched to the correct value for on- or off-chip impedance matching as required.

[0079] In this arrangement, the current source 66 is variable, such that it can provide a desired current from the power supply rail 40 through the mirror transistor 62 to ground 42. While variable current sources are typically able to take any value between lower and upper limits, in this embodiment the current source 66 can be set to one of two discrete current values.

[0080] The amount of current that flows through the mirror transistor 62 directly determines the amount of current that flows through the RF input transistor 44, i.e. it controls the current density through the RF input transistor 44, in turn altering its transconductance. Since the current source 66 is able to provide two discrete current values, this causes the RF input transistor 44 to have either a first transconductance value gm.sub.1 for use with on-chip impedance matching; or a second transconductance value gm.sub.2 for use with off-chip impedance matching.

[0081] FIG. 7 shows an amplifier arrangement with aspect ratio controlled transconductance in accordance with an embodiment of the invention. In this arrangement, there are two RF input transistors 44a, 44b arranged in parallel having first and second aspect ratios

[00018] $\frac{W_{1}}{L_{1}} .Math. .Math. and .Math. .Math. \frac{W_{2}}{L_{2}}$

respectively such that the first transistor 44a has a first transconductance value gm.sub.1 for use with on-chip impedance matching and the second transistor 44b has a second transconductance value gm.sub.2 for use with off-chip impedance matching.

[0082] Each of the RF input transistors 44a, 44b has its drain terminal connected to the source terminal of an nMOSFET selection transistor 68a, 68b. The gate terminals of each of the selection transistors 68a, 68b are connected to selection terminals 70a, 70b; while the drain terminals of the selection transistors 68a, 68b are connected to the RLC resonance circuit and back to the input terminal 34 via the feedback network as before.

[0083] Different voltages (e.g. +5 V and 0 V) can then be applied to selection terminals 70a and 70b in order to selectively enable one of the selection transistors 68a, 68b while disabling the other. This ensures that current can only flow through one of the RF input transistors 44a, 44b at any given time, while the other is essentially disconnected from the circuit. The enabled selection transistor 68a, 68b then simply acts as a cascode transistor during operation.

[0084] In this arrangement, the current source 66 provides a constant bias current through the mirror transistor 62, which allows for constant biasing of the RF input transistor 44a, 44b in use. Meanwhile it is the difference in aspect ratios

[00019] $\frac{W_{1}}{L_{1}} .Math., \frac{W_{2}}{L_{2}}$

that provide the variable transconductance.

[0085] FIGS. 8A and 8B show amplifier arrangements with configurable feedback resistance in accordance with an embodiment of the invention. In FIG. 8a, the variable feedback resistance is achieved by simply using a variable resistor 46 (e.g. a rheostat). However, this is impractical for use in integrated circuits.

[0086] Instead, the arrangement in FIG. 8B uses two different feedback resistors 46a, 46b with resistance values of R.sub.F1 and R.sub.F2 respectively. Each of these feedback resistors 46a, 46b is in parallel with one another, and in series with a switch 68a, 68b respectively. These switches may each be physical switches or may be implemented in silicon using e.g. a MOSFET wherein applying a sufficient gate-source voltage thereto completes the feedback path including the appropriate resistor 46a, 46b while leaving the other disconnected. This allows for the appropriate resistance value of R.sub.F1 or R.sub.F2 to be used for on- or off-chip impedance matching as appropriate.

[0087] FIG. 9 shows a differential amplifier arrangement 1010 with a variable current source 66 for use in a radio frequency receiver device that utilises on-chip impedance matching. Here, two identical RF input transistors 144a, 144b form a grounded-source pair arrangement that amplify a differential signal input across input terminals 134a, 134b. The arrangement shown in FIG. 9 (and similarly in FIG. 10) shows a bias terminal 70 to which a bias voltage (e.g. the supply voltage 42) is applied.

[0088] The variable current source 66 can be set to either a first bias current I.sub.b1 or a second bias current I.sub.b2, which sets the transconductance values of the RF input transistors 144a, 144b to either gm.sub.1 or gm.sub.2 respectively.

[0089] The feedback resistance on each side of the amplifier may be switched between first and second feedback resistance values R.sub.F1 and R.sub.F2 using switches 152a, 152b, 153a, 153b. If the RF input transistors 144a, 144b are set to their first transconductance value of gm.sub.1 and the feedback is set to the first feedback resistance value of R.sub.F1 by closing switches 152a, 152b and opening switches 153a, 153b, the LNA 1010 is ready for use with on-chip impedance matching.

[0090] By way of contrast, FIG. 10 shows the differential amplifier arrangement 1010 of FIG. 9 utilising an external impedance matching circuit 160 for off-chip impedance matching. In order to achieve this, the RF input transistors 144a, 144b are set to their second conductance value of gm.sub.2 and the feedback is set to the second feedback resistance value of R.sub.F2 by opening switches 152a, 152b and closing switches 153a, 153b, setting the LNA 1010 to its off-chip mode.

[0091] FIG. 11 shows a differential amplifier arrangement 1110 with a fixed current source 66 in accordance with an embodiment of the invention. Similarly to the LNA 1010 described with reference to FIGS. 9 and 10, two identical RF input transistors 144a, 144b form a grounded-source pair arrangement.

[0092] Similarly to the LNA 1010 of FIGS. 9 and 10, the feedback resistance may be switched between first and second feedback resistance values R.sub.F1 and R.sub.F2 using switches 152a, 152b, 153a, 153b. If the RF input transistors 144a, 144b are set to their first transconductance value of gm.sub.1 and the feedback is set to the first feedback resistance value of R.sub.F1 by closing switches 152a, 152b and opening switches 153a, 153b, the LNA 1110 is ready for use with on-chip impedance matching.

[0093] However, by way of contrast to the LNA 1010 of FIGS. 9 and 10, the effective transconductance is controlled by applying high or low voltages to control terminals 70a, 70b as described previously with reference to FIG. 7. In this arrangement, there are two pairs of parallel RF input transistorsa first pair 144a, 145a being one parallel arrangement and a second pair 144b, 145b being a further parallel arrangement. One transistor 144a, 144b in each pair has a first aspect ratio

[00020] $\frac{W_{1}}{L_{1}}$

while the other transistor 145a, 145b has a second aspect ratio

[00021] $\frac{W_{2}}{L_{2}}$

This means that for a given, fixed current from the current source 66, one transistor 144a, 144b in each pair has a first transconductance value gm.sub.1 for use with on-chip impedance matching while the other transistor 145a, 145b in the pair has a second transconductance value gm.sub.2 for use with off-chip impedance matching.

[0094] Each of the RF input transistors 144a, 144b, 145a, 145b have their respective drain terminal connected to the source terminal of an nMOSFET selection transistor 168a, 168b, 169a, 169b respectively. The gate terminals of one pair of selection transistors 168a, 168b are connected to one of the selection terminals 70a (for on-chip mode) while the gate terminals of the other pair of selection transistors 169a, 169b are connected to the other selection terminal 70b (for off-chip mode). The drain terminals of each of the selection transistors 168a, 168b, 169a, 169b are connected to the RLC resonance circuit and back to the input terminal 134 via the feedback network as before.

[0095] Different voltages (e.g. +5 V and 0 V) can be applied to the selection terminals 70a and 70b in order to selectively enable one of one of the selection transistor pairs 168a, 168b or 169a, 169b while disabling the other. This ensures that current can only flow through one pair of the RF input transistors 144a, 144b or 145a, 145b at any given time, while the other pair is essentially taken out of the circuit. The enabled selection transistor pair 168a, 168b or 169a, 169b simply act as a cascode transistor during operation.

[0096] Thus by opening switches 152a, 152b, closing switches 153a, 153b and applying a high voltage to the on-chip selection terminal 70a and a low voltage to the off-chip selection terminal 70b, the feedback resistance is set to R.sub.f1 and the effective transconductance is gm.sub.1.

[0097] FIG. 12 shows the differential amplifier arrangement 1110 of FIG. 11 utilising an external impedance matching circuit 160 for off-chip impedance matching. In this arrangement, switches 152a, 152b are closed, switches 153a, 153b are open, a low voltage is applied to the on-chip selection terminal 70a and a high voltage is applied to the off-chip selection terminal 70b. This sets the feedback resistance to R.sub.f2 and the effective transconductance is gm.sub.2, and thus the amplifier arrangement 1110 is ready for use in its off-chip impedance matching mode.

[0098] As described previously, the Applicant has appreciated that it is advantageous for the amplifier, and by extension the entire radio receiver, to exhibit the same gain and noise characteristics, regardless of whether on-chip or off-chip impedance matching is used, such that a customer need only choose between cost and power consumption.

[0099] If, from Equations 7 and 11, it is assumed that the noise in a resistive feedback LNA is dominated by the noise in the RF input transistor(s) 44, 144a, 144b, and the noise figure NF is designed to be equal in both configurations, i.e. in both on- and off-chip impedance matching modes, Equations 18 and 19 below are obtained:

[00022] $\begin{matrix} Approximation .Math. .Math. of .Math. .Math. noise .Math. .Math. figure .Math. .Math. in .Math. .Math. a .Math. .Math. resistive .Math. .Math. feedback .Math. .Math. in .Math. .Math. on .Math. - .Math. .Math. and .Math. .Math. off .Math. - .Math. chip .Math. .Math. impedance .Math. .Math. matching .Math. .Math. modes \\ .Math. N .Math. .Math. F 1 + \frac{}{g_{m .Math. .Math. 1} .Math. R_{s}} 1 + \frac{}{g_{m .Math. .Math. 2} .Math. R_{EQ}} & Equation .Math. .Math. 18 \end{matrix}$
g.sub.m1R.sub.s=g.sub.m2R.sub.EQ

Equation 19: Relationship Between First and Transconductance Values, Source Impedance and Impedance Looking into the On-Chip Input of the LNA in the Off-Chip Matching Configuration

[0100] By using the relation of Equation 19 in Equation 9, Equation 20 below is obtained:

R.sub.F2=(g.sub.m2R.sub.EQ1)R.sub.L=(g.sub.m1R.sub.s1)R.sub.L

Equation 20: Second Feedback Resistance Value for Off-Chip Matching in Terms of On-Chip Matching Variables Only

[0101] Thus, once the component values for gm.sub.1 and R.sub.L are known from initially designing the LNA 510, 1010, 1110 for on-chip impedance matching, an initial value for the feedback resistor (R.sub.F2) needed for off-chip impedance matching while retaining the same LNA noise figure in both configurations can be obtained using Equation 20. Also, by requiring the LNA voltage gain A, be the same in both configurations and using Equation 13, the impedance transformation ratio in the external impedance matching circuit 60, 160 must fulfil the condition given below in Equation 21:

[00023] $\begin{matrix} Impedance .Math. .Math. transformation .Math. .Math. ratio .Math. .Math. for .Math. .Math. external .Math. .Math. matching .Math. .Math. circuit .Math. .Math. 60, 160 \\ .Math. N - \frac{R_{F .Math. .Math. 2}}{R_{F .Math. .Math. 1}} = \frac{(g_{m .Math. .Math. 1} .Math. R_{s} - 1) .Math. R_{L}}{R_{F .Math. .Math. 1}} & Equation .Math. .Math. 21 \end{matrix}$

[0102] Thus once gm.sub.1, R.sub.F1 and R.sub.L are available from the design of LNA 510, 1010, 1110 with on-chip input impedance matching and the value of N is determined, the external matching circuit 60, 160 for off-chip impedance matching can be designed as appropriate.

[0103] Simulations have been performed using 55 nm CMOS technology at LTE Band I (2170 MHz). The LNA performance is presented below in Table 1 for both on-chip and off-chip impedance matching configurations. In both configurations, the differential LNA input impedance is designed to be approximately 100. This is confirmed by the input reflection coefficient s.sub.11, which is well below 10 dB (which is a typical requirement used in the art to measure the quality of input matching).

TABLE-US-00001 TABLE 1 Simulated performance of exemplary differential resistive-feedback LNA with configurable input impedance matching. Simulations with 55 nm CMOS technology at Band I (2170 MHz). Parameter s.sub.11 Gain NF I.sub.DD (dB) (dB) (dB) (mA) LNA configuration 17 20.8 1.6 13.3 LNA with on-chip impedance matching 22 21.1 1.6 7.9 LNA with external impedance matching network

[0104] From Table 1 it can be seen that in both LNA configurations, the LNA has about 21 dB voltage gain and 1.6 dB NF. When configured for on-chip input impedance matching, the LNA consumes about 13.3 mA whereas when configured to be used with an external impedance matching circuit, the LNA draws about 7.9 mA. Thus, when used in the off-chip impedance matching configuration, a saving of approximately 40% in LNA power consumption can be achieved.

[0105] Thus it will be appreciated that the described embodiments of the present invention provide a radio frequency receiver device comprising one or more amplifiers that can be arranged for either on- or off-chip impedance matching without incurring a penalty to the LNA or radio receiver noise figure or linearity thereof. Although particular embodiments have been described in detail, it will be appreciated by those skilled in the art that many variations and modifications are possible using the principles of the invention set out herein.

RADIO FREQUENCY RECEIVER

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Abstract

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