An Embedded High Voltage LDMOS-SCR Device with a Strong Voltage Clamp and ESD Robustness

Abstract

The present invention provides an embedded high voltage LDMOS-SCR device with strong voltage clamp and ESD robustness, which can be used as the on-chip ESD protection for high voltage IC. Wherein said the device comprises a P substrate, a P well, a N well, a first field oxide isolation region, a first P+ injection region, a second field oxide isolation region, a first N+ injection region, a first fin polysilicon gate, a second N+ injection region, a second fin polysilicon gate, a third N+ injection region, a third fin polysilicon gate, a polysilicon gate, a fourth fin polysilicon gate, a second P+ injection region, a fifth fin polysilicon gate, a third P+ injection region, a sixth fin polysilicon gate, a fourth P+ injection region, a third oxygen isolation region, a fourth N+ injection region and a fourth field oxygen isolation region. Under the influence of ESD pulse, the ESD discharge current path with LDMOS-SCR structure and the RC coupling current path with embedded PMOS interdigital structure in the drain terminal and embedded NMOS interdigital structure in the source terminal are formed,in order to enhance the ESD robustness of the device and improve the voltage clamp capability.

Claims

1. An embedded high voltage LDMOS-SCR device with a strong voltage clamp and ESD robustness, comprising a RC coupling current path of interdigital structure which combines an embedded NMOS in a source terminal and an embedded PMOS in a drain terminal, and a ESD discharge current path of LDMOS-SCR structure, in order to enhance a ESD robustness of the device and voltage clamp capability; wherein the device further comprises a P substrate(101), a P well(102), a N well(103), a first field oxygen isolation region(104), a first P+ injection region(105), a second field oxygen isolation region(106), a first N+ injection region(107), a first fin polysilicon gate(108), a second N+ injection region(109), a second fin polysilicon gate(110), a third N+ injection region(111), a third fin polysilicon gate(112), a polysilicon gate(113), a fourth fin polysilicon gate(114), a second P+ injection region(115), a fifth fin polysilicon gate(116), a third P+ injection region(117), a sixth fin polysilicon gate(118), a fourth P+ injection region(119), a third field oxygen isolation region(120), a fourth N+ injection region(121) and a fourth field oxygen isolation region(122); wherein the P well(102) and the N well(103) are successively arranged from left to right on a surface of the P substrate(101), a left edge of the P substrate(101) is connected to a left edge of the P well(102), a right side of the P well(102) is connected to a left of the N well(103), and a right side of the N well(103) is connected to a right edge of the P substrate(101); wherein the first field oxygen isolation region(104), the first P+ injection region(105), the second field oxygen isolation region(106) and an embedded NMOS interdigital structure are successively arranged from left to right on a surface of the P well(102); wherein the embedded NMOS interdigital structure comprises the first N+ injection region(107), the first fin polysilicon gate(108), the second N+ injection region(109), the second fin polysilicon gate(110), the third N+ injection region(111) and the third fin polysilicon gate(112); wherein within a width range, the device is capable to be alternately extended from a N+ injection region and a fin polysilicon gate along the width direction according to an actual requirements; wherein a left side of the first field oxygen isolation region(104) is connected to a left edge of the P well(102), a right side of the first field oxygen isolation region(104) is connected to a left side of the first P+ injection region(105), a right side of the first P+ injection region(105) is connected to a left side of the second field oxygen isolation region(106), and a right side of the second field oxygen isolation region(106) is connected to a left side of the embedded NMOS interdigital structure; wherein the third field oxygen isolation region(120), the fourth N+ injection region(121), the fourth field oxygen isolation region(122) and an embedded PMOS interdigital structure are successively arranged from left to right on a surface of the N well(103); wherein the embedded PMOS interdigital structure comprises the fourth fin polysilicon gate(114), the second P+ injection region(115), the fifth fin polysilicon gate(116), the third P+ injection region(117), the sixth fin polysilicon gate(118) and the fourth P+ injection region(119); wherein within a width range, the device is capable to be alternately extended from a P+ injection region and a fin polysilicon gate along the width direction according to an actual requirements; wherein a right side of the embedded PMOS interdigital structure is connected to the left side of a third field oxygen isolation region(120), a right side of the third field oxygen isolation region(120) is connected to a left side of the fourth N+ injection region(121), a right side of the fourth N+ injection region(121) is connected to a left side of the fourth field oxygen isolation region(122), and a right side of the fourth field oxygen isolation region(122) is connected to a right edge of the N well(103); wherein the polysilicon gate(113) is configured to stretch across a partial surface of the P well(102) and the N well(103), a left side of the polysilicon gate(113) is connected to a right side of the embedded NMOS interdigital structure, and a right side of the polysilicon gate(113) is connected to the a side of the embedded PMOS interdigital structure; wherein the first P+ injection region(105) is connected to a first metal 1 (201), the first N+ injection region(107) is connected to a second metal 1 (202), the first fin polysilicon gate(108) is connected to a third metal 1 (203), the second N+ injection region(109) is connected to a fourth metal 1 (204), the second fin polysilicon gate(110) is connected to a fifth metal 1 (205), the third N+ injection region(111) is connected to a sixth metal 1 (206), the third fin polysilicon gate(112) is connected to a seventh metal 1 (207), the polysilicon gate(113) is connected to an eighth metal 1 (208), the fourth fin polysilicon gate(114) is connected to a ninth metal 1 (209), the second P+ injection region(115) is connected to a tenth metal 1 (210), the fifth fin polysilicon gate(116) is connected to an eleventh metal 1 (211), the third P+ injection region(117) is connected to a twelfth metal 1 (212), the sixth fin polysilicon gate(118) is connected to a thirteenth metal 1 (213), the fourth P+ injection region(119) is connected to a fourteenth metal 1 (214), and the fourth N+ injection region(121) is connected to a fifteenth metal 1 (215); wherein the first metal 1 (201), the second metal 1 (202), the third metal 1 (203), the fifth metal 1 (205), the sixth metal 1 (206), the seventh metal 1 (207) are all connected to a first metal 2 (301), and an electrode(304) extracted from the first metal 2 (301) is configured to be used as the metal cathode of the device; wherein the eighth metal 1 (208), the ninth metal 1 (209), the tenth metal 1 (210), the eleventh metal 1 (211), the thirteenth metal 1 (213), the fourteenth metal 1 (214) and the fifteenth metal (215) are all connected to a second metal 2 (302), and an electrode(305) extracted from the second metal 2 (302) is configured to be used as the metal anode of the device; wherein the fourth metal 1 (204) is connected to a third metal 2 (303), and the twelfth metal 1 (212) is connected to the third metal 2 (303).

2. The device of claim 1, wherein in the drain terminal, the embedded PMOS interdigital structure which comprises the fourth fin polysilicon gate(114), the second P+ injection region(115), the fifth fin polysilicon gate(116), the third P+ injection region(117), the sixth fin polysilicon gate(118) and the fourth P+ injection region(119) is capable to increase the holding voltage and enhance the voltage clamp capability of the device.

3. The device of claim 1, wherein in the source terminal, the embedded NMOS interdigital structure which comprises the first N+ injection region(107), the first fin polysilicon gate(108), the second N+ injection region(109), the second fin polysilicon gate(110), the third N+ injection region(111) and the third fin polysilicon gate(112) is capable to reduce the trigger voltage of the device, and increase the ESD robustness and voltage clamp capability of the device.

4. The device of claim 1, wherein the embedded PMOS interdigital structure and the embedded NMOS interdigital structure is capable to increase the parasitic capacitance of the device, and under the influence of transient ESD pulse, a trigger current of parasitic resistance in P well(102) and N well(103) is capable to be increased due to a RC coupling effect, and a trigger voltage of the device is capable to be reduced, and a voltage clamp capability of the device is enhanced and the current conduction uniformity of the device is improved.

Description

BRIEF DESCRIPTION OF FIGURES

[0019] FIG. 1 is a three dimensional diagram illustrating the device structure in a preferred embodiment.

[0020] FIG. 2 is a diagram illustrating the metal connection of the device in a preferred embodiment.

[0021] FIG. 3 is a diagram illustrating the ESD discharge current path CP1 and CP2 under the action of ESD pulse in a preferred embodiment.

[0022] FIG. 4 is a diagram illustrating the section structure of discharge current path CP1 and its internal equivalent circuit under the action of the ESD pulse.

DETAILED DESCRIPTION

[0023] With the drawings and a specific embodiment, the present invention is further described in detail.

[0024] The present invention provides an embedded high voltage LDMOS-SCR device with strong voltage clamp and ESD robustness. By combining the strong ESD robustness of the LDMOS-SCR structure and the advantages of large parasitic capacitance of embedded PMOS and NMOS interdigital structure, the capability of voltage clamp and the latch-up free under the high voltage ESD pulse stress is enhanced.

[0025] FIG. 1 is the three dimensional diagram illustrating the device structure, in particular to an embedded high voltage LDMOS-SCR device with strong voltage clamp and ESD robustness. This device includes the ESD discharge current path with LDMOS-SCR structure, the RC coupling current path with embedded PMOS interdigital structure in the drain terminal and embedded NMOS interdigital structure in the source terminal. Wherein said the device can enhance the ESD robustness of the device and improve the voltage clamp capability and the turn-on speed of the device. Wherein said the device comprises a P substrate 101, a P well 102, a N well 103, a first field oxide isolation region 104, a first P+ injection region 105, a second field oxide isolation region 106, a first N+ injection region 107, a first fin polysilicon gate 108, a second N+ injection region 109, a second fin polysilicon gate 110, a third N+ injection region 111, a third fin polysilicon gate 112, a polysilicon gate 113, a fourth fin polysilicon gate 114, a second P+injection region 115, a fifth fin polysilicon gate 116, a third P+ injection region 117, a sixth fin polysilicon gate 118, a fourth P+ injection region 119, a third oxygen isolation region 120, a fourth N+ injection region 121 and a fourth field oxygen isolation region 122.

[0026] Wherein said the P well 102 and the N 103 well are successively arranged from left to right on the surface of the P substrate 101. The left edge of the P substrate 101 is connected to the left edge of the P well 102. The right side of the P well 102 is connected to the left of the N well 103. The right side of the N well 103 is connected to the right edge of the P substrate 101.

[0027] Wherein said the first field oxygen isolation region 104, the first P+ injection region 105, the second field field oxygen isolation region 106 and the embedded NMOS interdigital structure are successively arranged from left to right on the surface of the P well 102. Wherein said the embedded NMOS interdigital structure comprises the first N+ injection region 107, the first fin polysilicon gate 108, the second N+ injection region 109, the second fin polysilicon gate 110, the third N+ injection region 111 and the third fin polysilicon gate 112. Within the width range, the device can be alternately extended from a N+ injection region and a fin polysilicon gate along the width direction according to the actual requirements. The left side of the first field oxygen isolation region 104 is connected to the left edge of the P well 102. The right side of the first field oxygen isolation region 104 is connected to the left side of the first P+ injection region 105. The right side of the first P+ injection region 105 is connected to the left side of the second field oxygen isolation region 106. The right side of the second field oxygen isolation region 106 is connected to the left side of the embedded NMOS interdigital structure.

[0028] Wherein said the third field oxygen isolation region 120, the fourth N+ injection region 121, the fourth field oxygen isolation region 122 and the embedded PMOS interdigital structure are successively arranged from left to right on the surface of the N well 103. Wherein said the embedded PMOS interdigital structure comprises the fourth fin polysilicon gate 114, the second P+ injection region 115, the fifth fin polysilicon gate 116, the third P+ injection region 117, the sixth fin polysilicon gate 118 and the fourth P+ injection region 119. Within the width range, the device can be alternately extended from a P+ injection region and a fin polysilicon gate along the width direction according to the actual requirements. The right side of the embedded PMOS interdigital structure is connected to the left side of the third field oxygen isolation region 120. The right side of the third field oxygen isolation region 120 is connected to the left side of the fourth N+ injection region 121. The right side of the fourth N+ injection region 121 is connected to the left side of the fourth field oxygen isolation region 122. The right side of the fourth field oxygen isolation region 122 is connected to the right edge of the N well 103.

[0029] Wherein said the polysilicon gate 113 stretches across the partial surface of the P well 102 and the N well 103. The left side of the polysilicon gate 113 is connected to the right side of the embedded NMOS interdigital structure. The right side of the polysilicon gate 113 is connected to the left side of the embedded PMOS interdigital structure.

[0030] As shown in FIG. 2, the first P+ injection region 105 is connected to a first metal 1 201. The first N+ injection region 107 is connected to a second metal 1 202. The first fin polysilicon gate 108 is connected to a third metal 1 203. The second N+ injection region 109 is connected to a fourth metal 1 204. The second fin polysilicon gate 110 is connected to a fifth metal 1 205. The third N+ injection region 111 is connected to a sixth metal 1206. The third fin polysilicon gate 112 is connected to a seventh metal 1 207. The polysilicon gate 113 is connected to an eighth metal 1 208. The fourth fin polysilicon gate 114 is connected to a ninth metal 1 209. The second P+ injection region 115 is connected to a tenth metal 1 210. The fifth fin polysilicon gate 116 is connected to an eleventh metal 1 211. The third P+ injection region 117 is connected to a twelfth metal 1 212. The sixth fin polysilicon gate 118 is connected to a thirteenth metal 1 213. The fourth P+ injection region 119 is connected to a fourteenth metal 1 214. The fourth N+ injection region 121 is connected to a fifteenth metal 1 215.

[0031] Wherein said the first metal 1 201, the second metal 1 202, the third metal 1 203, the fifth metal 1 205, the sixth metal 1206, the seventh metal 1 207 are all connected to a first metal 2 301, an electrode 304 extracted from the first metal 2 301 is used as the metal cathode of the device.

[0032] Wherein said the eighth metal 1 208, the ninth metal 1 209, the tenth metal 1 210, the eleventh metal 1 211, the thirteenth metal 1 213, the fourteenth metal 1 214 and the fifteenth metal 215 are all connected to a second metal 2 302, an electrode 305 extracted from the second metal 2 302 is used as the metal anode of the device.

[0033] Wherein said the fourth metal 1 204 is connected to a third metal 2 303, and the twelfth metal 1 212 is connected to the third metal 2 303.

[0034] As shown in FIG. 3, the ESD discharge current path CP1 with LDMOS-SCR structure comprising the metal anode, the N well 103, the fourth N+ injection region 121, the second P+ injection region 115, the fourth fin polysilicon gate 114, the polysilicon gate 113, the P well 102, the first N+ injection region 107, the first P+ injection region 105 and the metal cathode, can enhance the secondary failure current and voltage clamp capability of the device.

[0035] The RC coupling current path CP2 with embedded PMOS interdigital structure in the drain terminal and embedded NMOS interdigital structure in the source terminal comprises the metal anode, the N well 103, the fourth N+ injection region 121, the fourth P+ injection region 119, the sixth fin polysilicon gate 118, the third P+ injection region 117, the P well 102, the second N+ injection region 109, the second fin polysilicon gate 110, the third N+ injection region 111, the first P+ injection region 105 and the metal cathode. Because of the fin-type embedded NMOS interdigital structure and the embedded PMOS interdigital structure, parasitic capacitance on the surface of device can be increased, thereby the trigger current and the turn-on speed of the device can also be improved.

[0036] As shown in FIG. 4, when the ESD pulse acts on the device, the equivalent parasitic capacitance Cp with embedded PMOS interdigital structure is formed by comprising the N well 103, the fourth P+ injection region 119, the sixth fin polysilicon gate 118 and the third P+ injection region 117. The equivalent parasitic capacitance Cn with embedded NMOS interdigital structure is formed by comprising the P well 102, the second N+ injection region 109, the second fin polysilicon gate 110 and the third N+ injection region 111. Wherein said the equivalent parasitic capacitance Cp and the well resistance R.sub.NW of the N well 103 can form as the first RC coupling effect. Wherein said the equivalent parasitic capacitance Cn and the well resistance R.sub.PW of the P well 102 can form as the second RC coupling effect. Under the combined influence of the first RC coupling effect and the second RC coupling effect, the current on parasitic resistance of the P well 102 and the N well 103 can be increased. When the voltage of the R.sub.NW or the R.sub.PW rapidly increase to 0.7 V, the parasitic transistor Q1 or Q2 inside the structure of LDMOS-SCR turn on, thus forming the ESD discharge current path CP1, so as to improve the holding voltage and current of the device.

[0037] While the present invention has been described in some detail for purposes of clarity and understanding, one skilled in the art will appreciate that various changes in form and detail can be made without departing from the true scope of the invention. All figures, tables, appendices, patents, patent applications and publications, referred to above, are hereby incorporated by reference.