SOLID-STATE IMAGING DEVICE

Abstract

A solid-state imaging device comprises a photodetecting section, an unnecessary carrier capture section, and a vertical shift register. The unnecessary carrier capture section has carrier capture regions arranged in a region between the photodetecting section and the vertical shift register for respective rows. Each of the carrier capture regions includes a transistor and a photodiode. The transistor has one terminal connected to the photodiode and the other terminal connected to a charge elimination line. The charge elimination line is short-circuited to a reference potential line.

Claims

1-4. (canceled)

5: A solid-state imaging device comprising: a photodetecting section having M?N pixels (each of M and N being an integer of 2 or more), each including a first photodiode and a first switch circuit having one terminal connected to the first photodiode, two-dimensionally arrayed in M rows and N columns; N readout lines provided for the respective columns and connected to the other terminals of the first switch circuits included in the pixels of the corresponding columns; a readout circuit section connected to the N readout lines; and a shift register, juxtaposed with the photodetecting section in a row direction, for controlling an open/closed state of the first switch circuits for each row, wherein a line passing through a region of the first photodiode is set as a boundary of joint exposure.

6: The solid-state imaging device according to claim 5, wherein the shift register and the photodetecting section are formed on a common substrate.

7: The solid-state imaging device according to claim 5, wherein the boundary is a boundary in the column direction, and the boundary is shifted from the center of the first photodiode in the row direction.

8: The solid-state imaging device according to claim 5, wherein the boundary is a boundary in the column direction, the first switch circuit is disposed on one side of the center of the first photodiode in the row direction, and the boundary is disposed on the other side of the center of the first photodiode in the row direction.

9: The solid-state imaging device according to claim 5, wherein a dummy photodiode is arranged in a region between the photodetecting section and the readout circuit section.

10: The solid-state imaging device according to claim 9, wherein the dummy photodiode has a width in the column direction shorter than that of the first photodiode in the column direction.

11: The solid-state imaging device according to claim 9, wherein the N readout lines include a readout line disposed on the first photodiode and the dummy photodiode.

12: A method of manufacturing a solid-state imaging device including: a photodetecting section having M?N pixels (each of M and N being an integer of 2 or more), each including a first photodiode and a first switch circuit having one terminal connected to the first photodiode, two-dimensionally arrayed in M rows and N columns; N readout lines provided for the respective columns and connected to the other terminals of the first switch circuits included in the pixels of the corresponding columns; a readout circuit section connected to the N readout lines; and a shift register, juxtaposed with the photodetecting section in a row direction, for controlling an open/closed state of the first switch circuits for each row, the method comprising: when manufacturing at least the photodetecting section by a photolithography technique, performing joint exposure, wherein in performing the joint exposure, a line passing through a region of the first photodiode is set as a boundary of the joint exposure.

13: The solid-state imaging device manufacturing method according to claim 12, wherein, in the solid-state imaging device, the shift register and the photodetecting section are formed on a common substrate.

14: The solid-state imaging device manufacturing method according to claim 12, wherein the boundary is a boundary in the column direction, and the boundary is shifted from the center of the first photodiode in the row direction.

15: The solid-state imaging device manufacturing method according to claim 12, wherein the boundary is a boundary in the column direction, the first switch circuit is disposed on one side of the center of the first photodiode in the row direction, and the boundary is disposed on the other side of the center of the first photodiode in the row direction.

16: The solid-state imaging device manufacturing method according to claim 12, wherein, in the solid-state imaging device, a dummy photodiode is arranged in a region between the photodetecting section and the readout circuit section.

17: The solid-state imaging device manufacturing method according to claim 16, wherein the dummy photodiode has a width in the column direction shorter than that of the first photodiode in the column direction.

18: The solid-state imaging device manufacturing method according to claim 16, wherein the N readout lines include a readout line disposed on the first photodiode and the dummy photodiode.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0013] FIG. 1 is a plan view illustrating a solid-state imaging device.

[0014] FIG. 2 is a plan view enlarging a part of the solid-state imaging device.

[0015] FIG. 3 is a diagram illustrating an inner configuration of the solid-state imaging device.

[0016] FIG. 4 is a diagram illustrating a detailed circuit configuration example of a pixel, an integration circuit, a holding circuit, and a carrier capture region.

[0017] FIG. 5 is a timing chart of respective signals.

[0018] FIG. 6 is a plan view illustrating an example in which a dummy photodiode for absorbing unnecessary carriers is arranged in a region between a shift register and a photodetecting section.

[0019] FIG. 7 includes (a) a plan view of the photodetecting section illustrating an example of boundaries of joint exposure, and (b) a diagram illustrating an example of boundaries of joint exposure in the vicinity of a carrier capture section.

[0020] FIG. 8 includes (a) a plan view of the photodetecting section illustrating another example of boundaries of joint exposure, and (b) a diagram illustrating another example of boundaries of joint exposure in the vicinity of the carrier capture section.

[0021] FIG. 9 is a plan view schematically illustrating an example in which two glass substrates are juxtaposed with each other.

DESCRIPTION OF EMBODIMENTS

[0022] An embodiment of the solid-state imaging device in accordance with the present invention will be described below in detail with reference to the accompanying drawings. In the explanation of the drawings, the same elements will be denoted by the same reference signs, while omitting their overlapping descriptions.

[0023] The solid-state imaging device in accordance with an embodiment is used for a medical X-ray imaging system, for example. FIG. 1 and FIG. 2 are diagrams illustrating a configuration of a solid-state imaging device 1A in this embodiment. FIG. 1 is a plan view illustrating the solid-state imaging device 1A, while FIG. 2 is a plan view enlarging a part of the solid-state imaging device 1A. FIG. 1 and FIG. 2 also depict an XYZ orthogonal coordinate system for easier understanding.

[0024] As illustrated in FIG. 1, the solid-state imaging device 1A comprises a photodetecting section 20, an unnecessary carrier capture section 30, a readout circuit section 40, and a vertical shift register 60. The photodetecting section 20, unnecessary carrier capture section 30, readout circuit section 40, and vertical shift register 60 are formed on a principal surface of a substrate 12. The vertical shift register 60 is juxtaposed with the photodetecting section 20 in the X-axis direction. A part of the unnecessary carrier capture section 30 is arranged in a region between the photodetecting section 20 and the vertical shift register 60, while the remaining part of the unnecessary carrier capture section 30 is juxtaposed with the photodetecting section 20 in the Y-axis direction and located in a region between the photodetecting section 20 and readout circuit section 40.

[0025] The readout circuit section 40 includes a plurality of integration circuits provided so as to correspond to respective columns of the photodetecting section 20, while the integration circuits respectively generate voltage values corresponding to amounts of charges output from the pixels in the corresponding columns. The readout circuit section 40 holds the voltage values output from the respective integration circuits and successively outputs the held voltage values.

[0026] The photodetecting section 20 is constructed by two-dimensionally arranging a plurality of pixels P.sub.1,1 to P.sub.M,N over M rows and N columns (where each of M and N is an integer of 2 or more). FIG. 2 depicts four pixels P.sub.m,N?1, P.sub.m,N, P.sub.m+1, N?1, P.sub.m+1,N as representative of the plurality of pixels P.sub.1,1 to P.sub.M,N For example, the pixel P.sub.m,N is the one located on the m-th row and the N-th column (where m is an integer of 1 or more and M or less). In FIG. 1 and FIG. 2, the column direction coincides with the Y-axis direction, and the row direction coincides with the X-axis direction.

[0027] Each of the pixels P.sub.1,1 to P.sub.M,N included in the photodetecting section 20 comprises a transistor 21 and a photodiode 22. Each of the transistors 21 in the pixels P.sub.1,1 to P.sub.M,N is a first switch circuit in this embodiment. The transistor 21 is preferably constituted by a field-effect transistor (FET) but may also be constituted by a bipolar transistor. The following explanation will assume the transistor 21 to be an FET. In this case, by control terminal is meant a gate. When the transistor 21 is a bipolar transistor, by control terminal is meant a base.

[0028] Each of the photodiodes 22 in the pixels P.sub.1,1 to P.sub.M,N is a first photodiode in this embodiment. The photodiode 22, which is constituted by a semiconductor region including a p-n junction or p-i-n junction, generates charges by an amount corresponding to the intensity of light incident thereon and accumulates thus generated charges in a junction capacitance part. The transistor 21 has one terminal (e.g., a source region) electrically connected to the photodiode 22. An undepicted scintillator is disposed on the photodetecting section 20. The scintillator generates scintillation light according to X-rays incident thereon, converts an X-ray image into a light image, and outputs the light image to the photodiodes 22.

[0029] The solid-state imaging device 1A further comprises a plurality of row selection lines Q.sub.1 to Q.sub.M (represented by Q.sub.m and Q.sub.m+1 in FIG. 2) provided for the respective rows and a plurality of readout lines R.sub.1 to R.sub.N (represented by R.sub.N and R.sub.N?1 in FIG. 2) provided for the respective columns.

[0030] The row selection line Q.sub.m of the m-th row electrically connects the control terminals (e.g., gate terminals) for controlling the open/closed state of the transistors 21 included in the pixels P.sub.m,1 to P.sub.m,N of the corresponding row and the vertical shift register 60 for controlling the open/closed state of the transistors 21 for each row to each other. The readout line R.sub.n of the n-th column (where n is an integer of 1 or more and N or less) is electrically connected to the other terminals (e.g., drain regions) of the transistors 21 included in the pixels P.sub.1,n to P.sub.M,n of the corresponding column. The plurality of row selection lines Q.sub.1 to Q.sub.M and plurality of readout lines R.sub.1 to R.sub.N are made of a metal, for example.

[0031] The unnecessary carrier capture section 30 has M carrier capture regions DA.sub.1 to DA.sub.M. The carrier capture regions DA.sub.1 to DA.sub.M are arranged in a region between the photodetecting section 20 and vertical shift register 60 for the respective rows. FIG. 2 illustrates two carrier capture regions DA.sub.m, DA.sub.m+1 as representative of the carrier capture regions DA.sub.1 to DA.sub.M. For example, the carrier capture region DA.sub.m is the carrier capture region located at the m-th row. As with the above-described pixels P.sub.1,1 to P.sub.M,N, each of the M carrier capture regions DA.sub.1 to DA.sub.M comprises a transistor 21 and a photodiode 22.

[0032] Each of the M transistors 21 in the carrier capture regions DA.sub.1 to DA.sub.M is a second switch circuit in this embodiment. The M photodiodes 22 in the carrier capture regions DA.sub.1 to DA.sub.M, each of which is a dummy photodiode in this embodiment and constituted by a semiconductor region including a p-n junction or p-i-n junction, are arranged in a region between the photodetecting section 20 and vertical shift register 60 for the respective rows. The transistor 21 has one terminal (e.g., a source region) electrically connected to the photodiode 22.

[0033] A control terminal (e.g., gate terminal) for controlling the open/closed state of the transistor 21 included in the carrier capture region DA.sub.m is electrically connected to the row selection line Q.sub.m of the corresponding row. The solid-state imaging device 1A further comprises a charge elimination line R.sub.d. The charge elimination line R.sub.d is electrically connected to the other terminals (e.g., drain regions) of the transistors 21 included in the carrier capture regions DA.sub.1 to DA.sub.M. The charge elimination line R.sub.d is made of a metal. Light is incident on the carrier capture regions DA.sub.1 to DA.sub.M, which are not light-shielded, as on the normal pixels P.sub.1,1 to P.sub.M,N. However, the carrier capture regions DA.sub.1 to DA.sub.M may partly or wholly be light-shielded.

[0034] The unnecessary carrier capture section 30 further has (N+1) carrier capture regions DB.sub.1 to DB.sub.N+1 arranged for the respective columns. The carrier capture regions DB.sub.1 to DB.sub.N+1 are constructed as with the above-described pixels P.sub.1,1 to P.sub.M,N. That is, each of the carrier capture regions DB.sub.1 to DB.sub.N+1 comprises a transistor 21 and a photodiode 22.

[0035] The transistor 21 has one terminal (e.g., source region) electrically connected to the photodiode 22. Control terminals of the transistors 21 included in the carrier capture regions DB.sub.1 to DB.sub.N+1 are electrically connected to a row selection line Q.sub.d which will be explained later. The other terminals (e.g., drain regions) of the transistors 21 included in the carrier capture regions DB.sub.1 to DB.sub.N are electrically connected to the readout lines R.sub.1 to R.sub.N of the respective columns. The other terminal of the transistor 21 included in the carrier capture region DB.sub.N+1 of the (N+1)-th column is electrically connected to the charge elimination line R.sub.d.

[0036] A circuit configuration of the solid-state imaging device 1A will now be explained in detail. FIG. 3 is a diagram illustrating an inner configuration of the solid-state imaging device 1A. As described above, the photodetecting section 20 is constructed by two-dimensionally arraying M?N pixels P.sub.1,1 to P.sub.M,N in M rows and N columns. The unnecessary carrier capture section 30 includes the M carrier capture regions DA.sub.1 to DA.sub.M and (N+1) carrier capture regions DB.sub.1 to DB.sub.N+1. The m-th row selection line Q.sub.m connected to the N pixels P.sub.m,1 to P.sub.m,N and carrier capture region DA.sub.m of the m-th row is connected to the vertical shift register 60. The row selection line Q.sub.d connected to the carrier capture regions DB.sub.1 to DB.sub.N+1 is also connected to the vertical shift register 60.

[0037] The readout circuit section 40 is a circuit for successively outputting electric signals corresponding to amounts of charges output for the respective columns through the readout lines R.sub.1 to R.sub.N. The readout circuit section 40 has N integration circuits 42 provided for the respective columns and N holding circuits 44. The integration circuit 42 and holding circuit 44 are connected in series to each other for each column. The N integration circuits 42 have a configuration in common. The N holding circuits 44 have a configuration in common.

[0038] The N integration circuits 42 have respective input terminals connected to the readout lines R.sub.1 to R.sub.N, accumulate charges input from the readout lines R.sub.1 to R.sub.N, and output respective voltage values corresponding to the amounts of accumulated charges from output terminals to the N holding circuits 44. Here, the charge elimination line R.sub.d is provided with no integration circuit, but is short-circuited to a reference potential line (a potential line connected to the ground potential in this embodiment) GND. Therefore, the charges having passed through the charge elimination line R.sub.d is discharged to the reference potential line GND. Thus, unlike the signals output from the photodiodes 22 of the pixels P.sub.1,1 to P.sub.m,N and input to the readout circuit section 40, the signals output from the respective dummy photodiodes 22 of the carrier capture regions DA.sub.1 to DA.sub.M are not output from the solid-state imaging device LA.

[0039] The N integration circuits 42 are respectively connected to a reset line 46 provided in common for the N integration circuits 42. The N holding circuits 44 have respective input terminals connected to the output terminals of the integration circuits 42, hold the voltage values input to the input terminals, and output the held voltage values from the output terminals to a voltage output line 48. The N holding circuits 44 are respectively connected to a hold line 45 provided in common for the N holding circuits 44. The N holding circuits 44 are also respectively connected to a horizontal shift register 61 through a first column selection line U.sub.1 to an N-th column selection line U.sub.N.

[0040] The vertical shift register 60 provides the N pixels P.sub.m,1 to P.sub.m,N at the m-th row with an m-th row selection control signal VS.sub.m through the m-th row selection line Q.sub.m. In addition, the vertical shift register 60 provides the (N+1) carrier capture regions DB.sub.1 to DB.sub.N+1 with a row selection control signal VS.sub.d through the row selection line Q.sub.d. In the vertical shift register 60, the row selection control signals VS.sub.d, VS.sub.1 to VS.sub.M sequentially become significant values.

[0041] The horizontal shift register 61 provides the N holding circuits 44 with column selection control signals HS.sub.1 to HS.sub.N through the column selection lines U.sub.1 to U.sub.N, respectively. The column selection control signals HS.sub.1 to HS.sub.N sequentially become significant values. Each of the N integration circuits 42 is provided with a reset control signal RE through the reset line 46. Each of the N holding circuits 44 is provided with a hold control signal Hd through the hold line 45.

[0042] FIG. 4 is a diagram illustrating a detailed circuit configuration example of the pixel P.sub.m,n, integration circuit 42, holding circuit 44, and carrier capture region DA.sub.m. Here, a circuit diagram of the pixel P.sub.m,n on the m-th row and the n-th column is illustrated as a representative of the M?N pixels P.sub.1,1 to P.sub.M,N, and a circuit diagram of the carrier capture region DA.sub.m at the m-th row is illustrated as a representative of the M carrier capture regions DA.sub.1 to DA.sub.M.

[0043] As illustrated in FIG. 4, the photodiode 22 of the pixel P.sub.m,n has a grounded anode terminal and a cathode terminal connected to the readout line R.sub.n through the transistor 21. Similarly, the photodiode 22 of the carrier capture region DA.sub.m has a grounded anode terminal and a cathode terminal connected to the charge elimination line R.sub.d through the transistor 21. The transistors 21 of the pixel P.sub.m,n and carrier capture region DA.sub.m are provided with the m-th row selection control signal VS.sub.m from the vertical shift register 60 through the m-th row selection line Q.sub.m. The m-th row selection control signal VS.sub.m instructs the transistors 21 included in the N pixels P.sub.m,1 to P.sub.m,N and carrier capture region DA.sub.m at the m-th row to open/close.

[0044] When the m-th row selection control signal VS.sub.m is a non-significant value (off-voltage of the control terminal of the transistor 21), for example, the transistor 21 is turned off. At this time, the charges generated in the photodiode 22 are accumulated in the junction capacitance part of the photodiode 22 without being output to the readout line R (or the charge elimination line R.sub.d). When the m-th row selection control signal VS.sub.m is a significant value (on-voltage of the control terminal of the transistor 21), on the other hand, the transistor 21 is turned on. At this time, the charges accumulated in the junction capacitance part of the photodiode 22 are output to the readout line R.sub.n (or charge elimination line R.sub.d) through the transistor 21. The charges output from the photodiode 22 of the pixel P.sub.m,n are sent to the integration circuit 42 through the readout line R.sub.n. On the other hand, the charges output from the photodiode 22 of the carrier capture region DA.sub.m are sent to the reference potential line GND through the charge elimination line R.sub.d.

[0045] The integration circuit 42 has a so-called charge integration type configuration including an amplifier 42a, a capacitive element 42b, and a discharge switch 42c. The capacitive element 42b and discharge switch 42c are connected in parallel with each other between the input terminal and output terminal of the amplifier 42a. The amplifier 42a has an input terminal connected to the readout line R.sub.n. The discharge switch 42c is provided with the reset control signal RE through the reset line 46.

[0046] The reset control signal RE instructs the respective discharge switches 42c of the N integration circuits 42 to open/close. For example, when the reset control signal RE is a non-significant value (e.g., high level), the discharge switch 42c closes, so as to discharge the capacitive element 42b, thereby initializing the output voltage value of the integration circuit 42. When the reset control signal RE is a significant value (e.g., low level), the discharge switch 42c opens, so that the charges input to the integration circuit 42 are accumulated in the capacitive element 42b, whereby a voltage value corresponding to the amount of accumulated charges is output from the integration circuit 42.

[0047] The holding circuit 44 includes an input switch 44a, an output switch 44b, and a capacitive element 44c. One end of the capacitive element 44c is grounded. The other end of the capacitive element 44c is connected to the output terminal of the integration circuit 42 through the input switch 44a and also connected to the voltage output line 48 through the output switch 44b. The input switch 44a is provided with the hold control signal Hd through the hold line 45. The hold control signal Hd instructs the respective input switches 44a of the N holding circuits 44 to open/close. The output switch 44b of the holding circuit 44 is provided with the n-th column selection control signal HS.sub.n through the n-th column selection line U.sub.n. The selection control signal HS.sub.n instructs the output switch 44b of the holding circuit 44 to open/close.

[0048] When the hold control signal Hd changes from the high level to the low level, for example, the input switch 44a changes from the closed state to the open state, whereupon the voltage value input to the holding circuit 44 is held by the capacitive element 44c. When the n-th column selection control signal HS.sub.n changes from the low level to the high level, the output switch 44b is closed, whereupon the voltage value held by the capacitive element 44c is output to the voltage output line 48.

[0049] FIG. 5 is a timing chart of respective signals. FIG. 5 illustrates, successively from the upper side, (a) reset control signal RE, (b) row selection control signal VS.sub.d, (c) first row selection control signal VS.sub.1, (d) second row selection control signal VS.sub.2, (e) third row selection control signal VS.sub.3, (f) fourth row selection control signal VS.sub.4, (g) M-th row selection control signal VS.sub.M, (h) hold control signal Hd, and (i) first column selection control signal HS.sub.1 to N-th column selection control signal HS.sub.N.

[0050] First, during a period from time t.sub.10 to time t.sub.11, the reset control signal RE is set to the high level. This closes the discharge switch 42c in each of the N integration circuits 42, so as to discharge the capacitive element 42b.

[0051] During a period from time t.sub.12 after time t.sub.1l to time t.sub.13, the vertical shift register 60 sets the row selection control signal VS.sub.d to the high level. This turns the transistors 21 in the carrier capture regions DB.sub.1 to DB.sub.N+1 into connected states, whereby the charges accumulated in the respective photodiodes 22 of the carrier capture regions DB.sub.1 to DB.sub.N+1 are output through the readout lines R.sub.1 to R.sub.N to the integration circuits 42 and accumulated in the capacitive elements 42b. Thereafter, during a period from time t.sub.14 after time t.sub.13 to time t.sub.15, the reset control signal RE is set to the high level. This closes the discharge switch 42c in each of the N integration circuits 42, so as to release the charges accumulated in the capacitive element 42b.

[0052] Subsequently, during a period from time t.sub.16 after time t.sub.15 to time t.sub.17, the first row selection control signal VS.sub.1 is set to the high level. This turns the transistors 21 in the pixels P.sub.1,1 to P.sub.1,N at the first row and the carrier capture region DA.sub.1 into connected states. The charges accumulated in the photodiodes 22 of the pixels P.sub.1,1 to P.sub.1,N are output through the readout lines R.sub.1 to R.sub.N to the respective integration circuits 42, so as to be accumulated in their capacitive elements 42b. The integration circuits 42 output respective voltage values having magnitudes corresponding to the amounts of charges accumulated in the capacitive elements 42b. On the other hand, the charges accumulated in the photodiode 22 of the carrier capture region DA.sub.1 are released to the reference potential line GND through the charge elimination line R.sub.d.

[0053] Then, during a period from time t.sub.18 after time t.sub.17 to time t.sub.19, the hold control signal Hd is set to the high level, whereby the input switch 44a in each of the N holding circuits 44 is turned into the connected state, whereby the voltage value output from the integration circuit 42 is held by the capacitive element 44c.

[0054] Thereafter, during a period from time t.sub.20 after time t.sub.19 to time t.sub.21, the horizontal shift register 61 turns the first column selection control signal HS.sub.1 to N-th column selection control signal HS.sub.N into the high levels in sequence. This successively closes the output switches 44b of the N holding circuits 44, whereby the voltage values held by the capacitive elements 44c are sequentially output to the voltage output line 48. During this period, the reset control signal RE is set to the high level, whereby the capacitive element 42b of each integration circuit 42 is discharged.

[0055] Next, during a period from time t22 after time t.sub.21 to time t.sub.23, the vertical shift register 60 sets the second row selection control signal VS.sub.2 to the high level. This turns the transistors 21 in the pixels P.sub.2,1 to P.sub.2,N at the second row and the carrier capture region DA.sub.2 into connected states. The charges accumulated in the respective photodiodes 22 in the pixels P.sub.2,1 to P.sub.2,N are output through the readout lines R.sub.1 to R.sub.N to the integration circuits 42 and accumulated in the capacitive elements 42b. On the other hand, the charges accumulated in the photodiode 22 of the carrier capture region DA.sub.2 are released to the reference potential line GND through the charge elimination line R.sub.d.

[0056] Subsequently, an operation similar to that at the first row successively outputs the voltage values having magnitudes corresponding to the amounts of charges accumulated in the capacitive elements 42b from the N holding circuits 44 to the voltage output line 48. Then, operations similar to that at the first row also convert the charges accumulated in the pixels at the third to M-th rows into voltage values and output them successively to the voltage output line 48. This completes the readout of image data by one image frame from the photodetecting section 20.

[0057] Effects exhibited by the solid-state imaging device 1A of this embodiment explained in the foregoing will now be explained. In the solid-state imaging device 1A of this embodiment, light is incident on not only the photodetecting section 20 but its surrounding regions as well. While the solid-state imaging device 1A is used as an X-ray imaging device, even when the regions surrounding the photodetecting section 20 are covered with a scintillator, X-rays transmitted through the scintillator and scintillation light from the scintillator are incident on the regions surrounding the photodetecting section 20. This generates unnecessary charges (unnecessary carriers) in the regions surrounding the photodetecting section 20. Since the vertical shift register 60 juxtaposed with the photodetecting section 20 has a substantial area, a large number of unnecessary carriers occur in the region formed with the vertical shift register 60 in particular.

[0058] When unnecessary carriers generated in the vertical shift register 60 flow into the photodetecting section 20, noise is superimposed on outputs from pixels P.sub.1,N to P.sub.M,N adjacent to the vertical shift register 60. FIG. 6 is a plan view illustrating an example in which a photodiode (dummy photodiode) 81 for absorbing unnecessary carriers is arranged in a region between the vertical shift register 60 and photodetecting section 20 in order to avoid the phenomenon described above. The dummy photodiode 81 is formed over a plurality of rows continuously from the first row to M-th row (i.e., continuous in the column direction). Short-circuiting the dummy photodiode 81 to the reference potential line (grounding line) GND can release the unnecessary carriers generated in the vertical shift register 60 to the reference potential line GND, so as to prevent them from flowing into the photodetecting section 20.

[0059] However, the following problem exists in this scheme. Typically, between pixels adjacent to each other in the photodetecting section 20, crosstalk exists because of coupling capacitance occurring between their photodiodes 22 and the like. In each pixel, parasitic capacitance also exists between the photodiode 22 and row selection line Q.sub.m connected to each other through the transistor 21 and this parasitic capacitance also affects the crosstalk. However, the above-described dummy photodiode 81 is provided with no transistor and thus does not generate such parasitic capacitance. Therefore, the pixels P.sub.1,N to P.sub.M,N adjacent to the dummy photodiode 81 have different degrees of crosstalk as compared with the other pixels, whereby output characteristics and magnitudes of noise from the pixels P.sub.1,N to P.sub.M,N adjacent to the dummy photodiode 81 differ from those of the other pixels.

[0060] In view of such problems, the solid-state imaging device 1A of this embodiment arranges the M photodiodes (dummy photodiodes) 22 for the respective rows in the carrier capture regions DA.sub.1 to DA.sub.M between the vertical shift register 60 and photodetecting section 20. The unnecessary carriers generated in the vertical shift register 60 are absorbed by these photodiodes 22. This can effectively prevent noise caused by unnecessary carriers generated in the vertical shift register 60 from being superimposed on outputs from pixels in the photodetecting section 20.

[0061] In this solid-state imaging device 1A, the photodiodes 22 of the carrier capture regions DA.sub.1 to DA.sub.M and the charge elimination line R.sub.d are connected to each other through the transistors 21, and when the transistors 21 are turned on, unnecessary carriers are eliminated from the photodiodes 22 to the reference potential line GND through the charge elimination line R.sub.d. Thus, in the solid-state imaging device 1A, the photodiodes 22 of the carrier capture regions DA.sub.1 to DA.sub.M are provided with the transistors 21 as in the pixels P.sub.1,1 to P.sub.M,N in the photodetecting section 20. Since the photodiodes 22 are provided for the carrier capture regions DA.sub.1 to DA.sub.M of the respective rows, the photodiodes 22 of the carrier capture regions DA.sub.t to DA.sub.M adjacent to each other in the column direction are separated from each other.

[0062] Therefore, the solid-state imaging device 1A of this embodiment enables the pixels P.sub.1,N to P.sub.M,N adjacent to the carrier capture regions DA.sub.1 to DA.sub.M to have crosstalk with a magnitude close to that of crosstalk in other pixels, thereby making it possible for the pixels P.sub.1,N to P.sub.M,N to have output characteristics and magnitudes of noise closer to those of the other pixels. When the carrier capture regions DA.sub.1 to DA.sub.M are light-shielded only partly or not at all, light is incident on the photodiodes 22 of the carrier capture regions DA.sub.1 to DA.sub.M as in the other pixels P.sub.1,1 to P.sub.M,N, so as to generate carriers, whereby they can accumulate carriers by amounts closer to those in the other pixels.

[0063] As in this embodiment, the vertical shift register 60 and photodetecting section 20 may be formed on the common substrate 12. While unnecessary carriers generated in the vertical shift register 60 are likely to flow into the photodetecting section 20 in such a case, the solid-state imaging device 1A of this embodiment can effectively prevent the unnecessary carriers from flowing into the photodetecting section 20.

[0064] Preferably, as in this embodiment, the control terminals of the transistors 21 of the carrier capture regions DA.sub.1 to DA.sub.M are connected to the row selection lines Q.sub.1 to Q.sub.M in common with the control terminals of the transistors 21 of the pixels P.sub.1,1 to P.sub.M,N. As a consequence, the parasitic capacitance values between the photodiodes 22 of the carrier capture regions DA.sub.1 to DA.sub.M and the row selection lines Q.sub.1 to Q.sub.M can be made closer to the parasitic capacitance values between the photodiodes 22 of the pixels P.sub.1,1 to P.sub.M,N and the row selection lines Q.sub.1 to Q.sub.M. Therefore, the magnitude of crosstalk in the pixels P.sub.1,N to P.sub.M,N adjacent to the carrier capture regions DA.sub.1 to DA.sub.M can be made further closer to the magnitude of crosstalk in the other pixels.

[0065] An exposure method in a process of manufacturing the solid-state imaging device 1A in accordance with this embodiment will now be explained. When manufacturing the solid-state imaging device 1A, a number of pixels P.sub.1,1 to P.sub.M,N and carrier capture regions DA.sub.1 to DA.sub.M, DB.sub.1 to DB.sub.N+1 are made by a photolithography technique while using a reticle including a predetermined pattern. At this time, since the pixels P.sub.1,1 to P.sub.M,N have a configuration in common, so-called joint exposure is performed, in which the reticle including the predetermined pattern is exposed to light a plurality of times while moving its position.

[0066] (a) in FIG. 7 is a plan view of the photodetecting section 20 and illustrates an example of boundaries (joints) LA of joint exposure. In the example illustrated in (a) in FIG. 7, lines passing the center of a rectangular photodiode 22 are referred to as boundaries LA, LB. In this case, as illustrated in (b) in FIG. 7, the photodiodes 22 in the carrier capture regions DA.sub.1 to DA.sub.M, DB.sub.1 to DB.sub.N+1 have a size substantially equivalent to that of the photodiodes 22 in the pixels P.sub.1,1 to P.sub.M.

[0067] (a) in FIG. 8 is a plan view of the photodetecting section 20 and illustrates another example of boundaries LA of joint exposure. In the example illustrated in (a) in FIG. 8, the boundary LA in the column direction is shifted to the left side (i.e., away from the carrier capture regions DA.sub.1 to DA.sub.M) from the center of the rectangular photodiode 22, and the boundary LB in the row direction is shifted to the upper side (i.e., away from the carrier capture regions DB.sub.1 to DB.sub.N) from the center of the rectangular photodiode 22. In this case, as illustrated in (b) in FIG. 8, the size of the photodiodes 22 in the carrier capture regions DA.sub.1 to DA.sub.M, DB.sub.1 to DB.sub.N+1 can be made smaller than the size of the photodiodes 22 in the pixels P.sub.1,1 to P.sub.M,N.

[0068] Specifically, the width of the photodiodes 22 of the carrier capture regions DA.sub.1 to DA.sub.M in the row direction can be made shorter than the width of the photodiodes 22 of the pixels P.sub.1,1 to P.sub.M,N in this direction. The width of the photodiodes 22 of the carrier capture regions DB.sub.1 to DB.sub.N in the column direction can also be made shorter than the width of the photodiodes 22 of the pixels P.sub.1,1 to P.sub.M,N in this direction. Therefore, the region required for surrounding the photodetecting section 20 can be made narrower.

[0069] The following advantages are obtained by making the photodiodes 22 of the carrier capture regions DA.sub.1 to DA.sub.M, DB.sub.1 to DB.sub.N+1 smaller as described above. FIG. 9 is a plan view schematically illustrating an example in which two glass substrates 12 are juxtaposed with each other. Formed on the glass substrates 12 are the pixels P.sub.1,1 to P.sub.M,N of the photodetecting section 20 and the carrier capture regions DA.sub.1 to DA.sub.M, DB.sub.1 to DB.sub.N+1. Thus juxtaposing a plurality of glass substrates 12 with each other is effective in further increasing the area of the photodetecting section in the solid-state imaging device as a whole.

[0070] At this time, arranging the pixels P.sub.1,1 to P.sub.M,N and carrier capture regions DA.sub.1 to DA.sub.M and DB.sub.1 to DB.sub.N identically on the two glass substrates 12 enables parts to be used in common, thereby suppressing the manufacturing cost. In this case, however, the carrier capture regions DA.sub.1 to DA.sub.M are located between the two photodetecting sections 20, thus yielding an insensitive region (dead area) in which the image is not obtained. In such a case, the above-described insensitive region can be narrowed by making the width of the photodiodes 22 of the carrier capture regions DA.sub.1 to DA.sub.M in the row direction smaller than the width of the photodiodes 22 in the pixels P.sub.1,1 to P.sub.M,N in this direction.

[0071] Referring to (a) in FIG. 8, in a normal pixel P.sub.m+1,n, a transistor is formed on the side closer to P.sub.m+1,n+1. The joint (boundary LA) of the pixel P.sub.m+1,n is located on the side closer to the pixel P.sub.m+1,n?1. That is, with respect to the center of the pixel P.sub.m+1,n, the transistor and joint (boundary LA) exist on one side and the other side of the pixel, respectively, thereby increasing the distance between the joint and transistor in the row direction. Thus, the joint and transistor can physically be separated from each other, whereby manufacturing defects can be reduced.

[0072] The solid-state imaging device in accordance with the present invention is not limited to the above-described embodiment, but can be modified in various ways. For example, the photodetecting section illustrated in the above-described embodiment may comprise a configuration in which a film of amorphous silicon or polycrystalline silicon is formed on a glass substrate. In this case, the transistor 21 is favorably realized by a thin-film transistor. The photodetecting section may also be produced on a monocrystalline silicon substrate.

[0073] Though the above-described embodiment employs the present invention in a so-called passive pixel sensor (PPS) in which each pixel has no amplifier circuit while integration circuits are provided for respective readout lines of columns, the present invention is also applicable to a so-called active pixel sensor (APS) in which each pixel has an amplifier circuit.

[0074] While the above-described embodiment illustrates an example in which the carrier capture regions DB.sub.1 to DB.sub.N+1 are juxtaposed with the photodetecting section in the column direction, the carrier capture regions DB.sub.1 to DB.sub.N+1 may be omitted.

[0075] The solid-state imaging device in accordance with the above-described embodiment uses a configuration comprising a photodetecting section having M?N pixels (each of M and N being an integer of 2 or more), each including a first photodiode and a first switch circuit having one terminal connected to the first photodiode, two-dimensionally arrayed in M rows and N columns; N readout lines provided for the respective columns and connected to the other terminals of the first switch circuits included in the pixels of the corresponding columns; N integration circuits for outputting respective voltage values corresponding to amounts of charges input through the N readout lines; a shift register, juxtaposed with the photodetecting section in a row direction, for controlling an open/closed state of the first switch circuits for each row; M dummy photodiodes arranged in a region between the shift register and the photodetecting section for the respective rows; M second switch circuits having respective one terminals connected to the M dummy photodiodes; and a charge discharge line connected to the other terminals of the M second switch circuits and short-circuited to a reference potential line.

[0076] The solid-state imaging device may have a configuration in which the dummy photodiode has a width in the row direction shorter than that of the first photodiode in the row direction. In the above solid-state imaging device, the size of the dummy photodiode is not always required to be equal to that of the first photodiode. Therefore, thus making the width of the dummy photodiode shorter than that of the first photodiode can narrow regions surrounding the photodetecting section, whereby an insensitive region occurring between solid-state imaging devices when a plurality of solid-state imaging devices are juxtaposed with each other, for example, can be made narrower.

[0077] The solid-state imaging device may also have a configuration in which the shift register and the photodetecting section are formed on a common substrate. While unnecessary carriers generated in the shift register are likely to flow into the photodetecting section in such a case, the above-described solid-state imaging device can effectively prevent the unnecessary carriers from flowing into the photodetecting section.

[0078] The solid-state imaging device may have a configuration further comprising M row selection lines, provided for the respective rows, for electrically connecting control terminals of the first and second switch circuits for controlling the open/closed state and the shift register to each other. Thus providing the row selection lines in common for the first and second switch circuits enables pixels adjacent to the dummy photodiode to have crosstalk with a magnitude further closer to that of crosstalk in the other pixels.

INDUSTRIAL APPLICABILITY

[0079] The present invention can be utilized as a solid-state imaging device which enables pixels adjacent to a dummy photodiode to have output characteristics and magnitudes of noise closer to those of the other pixels.

REFERENCE SIGNS LIST

[0080] 1Asolid-state imaging device, 12substrate, 20photodetecting section, 21transistor, 22photodiode, 30unnecessary carrier capture section, 40readout circuit section, 42integration circuit, 44holding circuit, 45hold line, 46reset line, 48voltage output line, 60vertical shift register, 61horizontal shift register, DA.sub.1 to DA.sub.M, DB.sub.1 to DB.sub.N+1carrier capture region, GNDreference potential line, LA, LBboundary (joint), P.sub.1,1 to P.sub.M,Npixel, Q.sub.1 to Q.sub.M, Q.sub.drow selection line, R.sub.1 to R.sub.Nreadout line, R.sub.dcharge elimination line.