SOLID-STATE IMAGING ELEMENT, DRIVING METHOD, AND ELECTRONIC DEVICE

Abstract

The present disclosure relates to a solid-state imaging element, a driving method, and an electronic device that can generate an arbitrary intermediate voltage level between a high voltage level and a low voltage level. A solid-state imaging element according to a first aspect of the present disclosure includes: a first driving line configured to supply selectively to a posterior stage, a first voltage level that is output from a first power source and a second voltage level that is output from a second power source and lower than the first voltage level; a second driving line that is different from the first driving line; a capacitance that is formed between the first driving line and the second driving line; and a floating setting unit configured to set the first driving line to a floating state. The present disclosure is applicable to, for example, a CMOS image sensor.

Claims

1. A solid-state imaging element comprising: a first driving line configured to supply selectively to a posterior stage, a first voltage level that is output from a first power source and a second voltage level that is output from a second power source and lower than the first voltage level; a second driving line that is different from the first driving line; a capacitance that is formed between the first driving line and the second driving line; and a floating setting unit configured to set the first driving line to a floating state.

2. The solid-state imaging element according to claim 1, wherein the first driving line set to the floating state is configured to supply to the posterior stage, a third voltage level between the first voltage level and the second voltage level in accordance with a change in voltage that is supplied to the second driving line by capacitive coupling.

3. The solid-state imaging element according to claim 1, wherein the floating setting unit comprises a first switch configured to connect between the first power source and the first driving line, and a second switch configured to connect between the second power source and the first driving line.

4. The solid-state imaging element according to claim 2, wherein the capacitance formed between the first driving line and the second driving line is a parasitic capacitance.

5. The solid-state imaging element according to claim 2, wherein the capacitance formed between the first driving line and the second driving line is an actual capacitance that is formed intentionally.

6. The solid-state imaging element according to claim 2, wherein the first driving line and the second driving line are pixel driving lines that are disposed adjacent to each other in a longitudinal direction.

7. The solid-state imaging element according to claim 2, wherein the second driving line is a line dedicated to the capacitive cup link.

8. The solid-state imaging element according to claim 2, wherein each of the first driving line and the second driving line comprises a plurality of driving lines.

9. The solid-state imaging element according to claim 2, wherein the first driving line is configured to supply any of the first voltage level, the secondvoltage level, and the third voltage level to a transfer gate electrode in the posterior stage.

10. A driving method for a solid-stage imaging element including a first driving line configured to supply selectively to a posterior stage, a first voltage level that is output from a first power source and a second voltage level that is output from a second power source and lower than the first voltage level, a second driving line that is different from the first driving line, a capacitance that is formed between the first driving line and the second driving line, and a floating setting unit configured to set the first driving line to a floating state, the method comprising the steps of: setting the first driving line configured to supply the first voltage level to the posterior stage, to the floating state; and lowering the voltage level to be supplied to the second driving line and supplying a third voltage level between the first voltage level and the second voltage level to the posterior stage from the first driving line by capacitive coupling.

11. An electronic device including a solid-stage imaging element, the solid-stage imaging element comprising: a first driving line configured to supply selectively to a posterior stage, a first voltage level that is output from a first power source and a second voltage level that is output from a second power source and lower than the first voltage level; a second driving line that is different from the first driving line; a capacitance that is formed between the first driving line and the second driving line; and a floating setting unit configured to set the first driving line to a floating state.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0021] FIG. 1 is a circuit diagram for describing a basic principle of the present disclosure.

[0022] FIG. 2 is a timing chart in accordance with FIG. 1.

[0023] FIG. 3 is a diagram for describing a transition time in a circuit illustrated in FIG. 1.

[0024] FIG. 4 is a timing chart in accordance with FIG. 3.

[0025] FIG. 5 is a diagram for describing a method for causing an intermediate voltage level to transit smoothly.

[0026] FIG. 6 is a timing chart in accordance with FIG. 5.

[0027] FIG. 7 is a circuit diagram illustrating a first embodiment of the present disclosure.

[0028] FIG. 8 is a timing chart in accordance with FIG. 7.

[0029] FIG. 9 is a circuit diagram illustrating a configuration to set driving lines in FIG. 7 to a floating state.

[0030] FIG. 10 is a diagram illustrating a specific arrangement of two driving lines illustrated in FIG. 9 in a solid-state imaging element.

[0031] FIG. 11 is a plan view illustrating an arrangement of driving lines and transfer gate electrodes.

[0032] FIG. 12 is a stereoscopic perspective view in accordance with FIG. 7.

[0033] FIG. 13 is a timing chart in accordance with FIG. 9.

[0034] FIG. 14 is a circuit diagram illustrating a second embodiment of the present disclosure.

[0035] FIG. 15 is a stereoscopic perspective view in accordance with FIG. 14.

[0036] FIG. 16 is a circuit diagram illustrating a third embodiment of the present disclosure.

[0037] FIG. 17 is a circuit diagram illustrating a specific example of FIG. 16.

[0038] FIG. 18 is a timing chart in accordance with FIG. 16.

[0039] FIG. 19 is a diagram for describing a case in which an intermediate voltage level is used for charge transfer in a solid-state imaging element.

[0040] FIG. 20 is a diagram illustrating examples of using an electronic device to which the present disclosure has been applied.

MODE FOR CARRYING OUT THE INVENTION

[0041] A best mode for carrying out the present disclosure (hereinafter referred to as embodiment) will hereinafter be described in detail with reference to the drawings. First, a basic principle of the present disclosure is described.

<Basic Principle>

[0042] FIG. 1 is a circuit diagram for describing a basic principle of the present disclosure.

[0043] The circuit illustrated in FIG. 1 includes a capacitance C.sub.1 and a capacitance C.sub.2 that are connected in series. The capacitance C.sub.1 has one end connected to a pulse power source A through a line V.sub.1 and the other end connected to the capacitance C.sub.2 through a line V.sub.2. On the other hand, one end of the capacitance C.sub.2 that is not connected to the capacitance C.sub.1 is grounded. To the line V.sub.2, a pulse power source B is connected through a switch SW.

[0044] Note that the capacitance C.sub.1 and the capacitance C.sub.2 are not formed actually, and the capacitance C.sub.1 corresponds to a parasitic capacitance generated between the line V.sub.1 and the line V.sub.2. The capacitance C.sub.2 corresponds to the synthetic capacitance of all the capacitances connected to the line V.sub.2.

[0045] The pulse power sources A and B are ideal power sources that can change voltages in a pulsed manner.

[0046] FIG. 2 shows voltage changes of the pulse power sources A and B, timings when the switch SW is turned on or off, and changes of a voltage generated in the line V.sub.1 (referred to as voltage V.sub.1) and a voltage generated in the line V.sub.2 (referred to as voltage V.sub.2) that occur accordingly.

[0047] As shown in FIG. 2, the voltage V.sub.1 generated in the line V.sub.1 varies in synchronization with the pulse power source A without depending on whether the switch SW is on or off.

[0048] On the other hand, the voltage V.sub.2 generated in the line V.sub.2 varies in synchronization with the pulse power source B when the switch SW is on. However, when the switch SW is off, the line V.sub.2 is in a floating state (also referred to as a high impedance (high-Z) state) so that the capacitance C.sub.1 and the capacitance C.sub.2 are coupled. Here, due to an influence of the voltage V.sub.1 that drives the capacitance C.sub.1, the voltage V.sub.2 decreases by a voltage ?V.sub.2 following the decrease of the voltage V.sub.1. Here, the voltage ?V.sub.2 and the voltage V.sub.1 are in a relation as expressed by the following expression (1) , where ?V.sub.1 represents a variation width of the voltage V.sub.1:

[00001]$\left[\mathrm{Expression}.Math..Math.1\right].Math.$$\begin{array}{cc}?.Math..Math.V_2=\frac{C_1}{C_1+C_2}.Math.?.Math..Math.V_1& \left(1\right)\end{array}$

[0049] In other words, if the line V.sub.2 is set to the floating state, the voltage V.sub.2 generated in the line V.sub.2 can be controlled by using the pulse power source A.

[0050] However, the changes of the voltage V.sub.1 generated in the line V.sub.1 and the voltage V.sub.2 generated in the line V.sub.2 do not end instantly as shown in FIG. 2 but take a certain length of time (transition time).

[0051] Next, FIG. 3 is a circuit diagram for describing the time (transition time) necessary to change the voltage V.sub.1 generated in the line V.sub.1 and the voltage V.sub.2 generated in the line V.sub.2.

[0052] FIG. 3 additionally includes a capacitance C.sub.3 to the line V.sub.1 in the circuit diagram illustrated in FIG. 1. The capacitance C.sub.3 has one end grounded. Moreover, FIG. 3 shows a relation between the voltage change of the pulse power source B, and the timing when the switch SW is turned on or off, that is, the timing when the line V.sub.2 is set to the floating state. That is to say, the pulse power source B changes from a high voltage level V.sub.high to a low voltage level V.sub.Low while the line V.sub.2 is in the flowchart state.

[0053] FIG. 4 shows changes of the voltage V.sub.1 generated in the line V.sub.1 and the voltage V.sub.2 generated in the line V.sub.2 in accordance with FIG. 3.

[0054] As shown in A of FIG. 4, the voltage V.sub.1 generated in the line Vi starts to decrease from the V.sub.high state at the same time as the pulse power source A decreases, and decreases to V.sub.Low in accordance with the following expression (2):

[00002]$\left[\mathrm{Expression}.Math..Math.2\right].Math.$$\begin{array}{cc}{V}_1=\left(V_{\mathrm{High}}-V_{\mathrm{Low}}\right)?e^{\frac{-t}{\left(C_{12}+C_3\right).Math.R}}+V_{\mathrm{Low}}& \left(2\right)\end{array}$

[0055] In the expression (2) , a capacitance C.sub.12 is a synthetic capacitance of the capacitance C.sub.1 and the capacitance C.sub.2, and is expressed by the following expression (3):

[00003]$\left[\mathrm{Expression}.Math..Math.3\right].Math.$$\begin{array}{cc}{C}_{12}=\frac{C_1.Math.C_2}{C_1+C_2}=\frac{C_1}{\frac{C_1}{C_2}+1}& \left(3\right)\end{array}$

[0056] On the other hand, when the switch SW is turned off at a timing 0 to make the line V.sub.2 in a floating state as shown in B of FIG. 4, the voltage V.sub.2 generated in the line V.sub.2 starts to decrease from V.sub.high following the decrease of the voltage V.sub.1 in accordance with the expression (4) below:

[00004]$\left[\mathrm{Expression}.Math..Math.4\right].Math.$$\begin{array}{cc}{V}_2=\frac{C_1}{C_1+C_2}?\left\{\left(V_{\mathrm{High}}-V_{\mathrm{Low}}\right)?e^{\frac{-t}{\left(C_{12}+C_3\right).Math.R}}+V_{\mathrm{Low}}\right\}& \left(4\right)\end{array}$

[0057] When the switch SW is turned on at a timing t.sub.1 to release the line V.sub.2 from the floating state, the voltage V.sub.2=V.sub.mid at that time is obtained in accordance with the following expression (5):

[00005]$\left[\mathrm{Expression}.Math..Math.5\right].Math.$$\begin{array}{cc}{V}_2=0.99?\frac{C_1}{C_1+C_2}.Math.\left(V_{\mathrm{High}}-V_{\mathrm{Low}}\right)& \left(5\right)\end{array}$

[0058] When the line V.sub.2 is released from the floating state, the pulse power source B has already decreased to V.sub.Low; therefore, the voltage V.sub.2 generated in the line V.sub.2 decreases from V.sub.Mid to V.sub.Low in accordance with the following expression (6):

[00006]$\left[\mathrm{Expression}.Math..Math.6\right].Math.$$\begin{array}{cc}{V}_2=\left(V_{\mathrm{Mid}}-V_{\mathrm{Low}}\right)?e^{\frac{-\left(t-t_1\right)}{\left(C_1+C_2\right).Math.R}}+V_{\mathrm{Low}}& \left(6\right)\end{array}$

[0059] As described above, in a case of the floating state, the voltage V.sub.2 generated in the line V.sub.2 changes following the change of the voltage V.sub.1. Therefore, the change of the voltage V.sub.2 does not occur before the change of the voltage V.sub.1, and the transition of the voltage V.sub.2 can be performed at the same time as that of the voltage V.sub.1. Moreover, if the line V.sub.2 is released from the floating state before the voltage V.sub.2 becomes V.sub.Low, the voltage V.sub.2 can be set to an arbitrary intermediate voltage level V.sub.Mid between the high voltage level V.sub.High and the low voltage level V.sub.Low.

[0060] Next, FIG. 5 shows a change in voltage of the pulse power source B and a timing when the switch SW is turned on or off (that is, timing of floating state) in a case where the transition of the voltage V.sub.2 generated in the line V.sub.2 is performed more smoothly than the transition shown in B of FIG. 4.

[0061] That is to say, while the line V.sub.2 is in the floating state, the voltage of the pulse power source B is changed into an intermediate voltage level V.sub.Mid2 between the high voltage level V.sub.High and the low voltage level V.sub.Low. Next, after the release from the floating state, the voltage of the pulse power source B may be changed from the intermediate voltage level V.sub.Mid2 to the low voltage level V.sub.Low.

[0062] FIG. 6 shows a change of the voltage V.sub.1 generated in the line V.sub.1 and a change of the voltage V.sub.2 generated in the line V.sub.2 in accordance with FIG. 5.

[0063] The voltage V.sub.1 generated in the line V.sub.1 starts to decrease at the same time as the pulse power source A decreases as shown in A of FIG. 6 and this is similar to A of FIG. 4. The voltage V.sub.1 decreases from V.sub.high to V.sub.Low in accordance with the expression (2).

[0064] On the other hand, as shown in B of FIG. 6, when the switch SW is turned off at a timing 0 to make the line V.sub.2 in a floating state, the voltage V.sub.2 generated in the line V.sub.2 decreases from V.sub.high following the decrease of the voltage V1 in accordance with the expression (4).

[0065] After that, assuming that the voltage when the switch SW is turned on at the timing t.sub.1 to release the line V.sub.2 from the floating state is V.sub.Mid1, the voltage of the pulse power source B when the line V.sub.2 is released from the floating state has already decreased to V.sub.Mid2; therefore, the voltage V.sub.2 decreases from V.sub.Mid1 to V.sub.Mid2 in accordance with the following expression (7):

[00007]$\left[\mathrm{Expression}.Math..Math.7\right].Math.$$\begin{array}{cc}{V}_2=\left(V_{\mathrm{Mid}.Math..Math.1}-V_{\mathrm{Mid}.Math..Math.2}\right)?e^{\frac{-\left(t-t_1\right)}{\left(C_1+C_2\right).Math.R}}+V_{\mathrm{Mid}.Math..Math.2}& \left(7\right)\end{array}$

[0066] In addition, when the voltage of the pulse power source B decreases from V.sub.Mid2 to V.sub.Low at a timing t.sub.2, the voltage V.sub.2 decreases from V.sub.Mid2 to V.sub.Low in accordance with the following expression (8):

[00008]$\left[\mathrm{Expression}.Math..Math.8\right].Math.$$\begin{array}{cc}{V}_2=\left(V_{\mathrm{Mid}.Math..Math.2}-V_{\mathrm{Low}}\right)?e^{\frac{-\left(t-t_1\right)}{\left(C_1+C_2\right).Math.R}}+V_{\mathrm{Low}}& \left(8\right)\end{array}$

[0067] As described above, if the voltage of the pulse power source B can be set to the intermediate voltage level V.sub.Mid2 between the high voltage level V.sub.High and the low voltage level V.sub.Low the transition of the voltage V.sub.2 generated in the line V.sub.2 can be performed more smoothly than the transition in the case of B in FIG. 4. In this case, since the voltage V.sub.2 can be set to two kinds of intermediate voltage levels V.sub.Mid1 and V.sub.Mid2 using this for charge transfer in a solid-state imaging element can improve the transfer efficiency further.

First Embodiment

[0068] Next, FIG. 7 is a circuit diagram of a first embodiment according to the present disclosure, in which the aforementioned basic principle is applied to a solid-state imaging element.

[0069] FIG. 7 illustrates three transfer gate electrodes TG11 to TG13 and driving lines 14 to 16 connected respectively to the three transfer gate electrodes TG11 to TG13 in the solid-state imaging element. That is to say, a driving pulse TG11 is applied to the transfer gate electrode TG11 through the driving line 14. Similarly, a driving pulse TG12 is applied to the transfer gate electrode TG12 through the driving line 15, and a driving pulse TG13 is applied to the transfer gate electrode TG13 through the driving line 16.

[0070] The driving lines 14 to 16 can be set to a floating state at an arbitrary timing. The driving lines 14 to 16 are disposed adjacent to each other. Therefore, a parasitic capacitance is generated between the driving lines 14 to 16. Similarly, a parasitic capacitance is generated between the transfer gate electrodes TG11 to TG13 that are disposed adjacent to each other. By using the parasitic capacitance as the capacitances C.sub.1 and C.sub.2 in the basic principle described above, the operation similar to that of the basic principle can be obtained.

[0071] Note that a capacitance that is designed intentionally in the circuit may be formed in addition to the parasitic capacitance generated between the driving lines 14 to 16 or between the transfer gate electrodes TG11 to TG13.

[0072] FIG. 8 shows the driving pulses TG11 to TG13 that are supplied to the driving lines 14 to 16 in FIG. 7, and voltage changes of the driving lines 14 to 16.

[0073] As shown in FIG. 8, when the driving pulse TG11 is applied to the transfer gate electrode TG11 through the driving line 14, setting the driving lines 15 and 16 to the floating state makes it possible to apply the intermediate voltage to the transfer gate electrodes TG12 and TG13 . Next, when the driving pulse TG12 is applied to the transfer gate electrode TG12 throughthe driving line 15, maintainingthe driving line 16 in the floating state makes it possible to apply an intermediate voltage that is different in level from the previous voltage to the transfer gate electrode TG13.

[0074] Next, FIG. 9 to FIG. 12 more specifically express the first embodiment shown in FIG. 7. That is to say, FIG. 9 expresses a circuit configuration to set two of the three driving lines 14 to 16 in FIG. 7 to the floating state.

[0075] FIG. 10 illustrates a specific arrangement of the two driving lines shown in FIG. 9 in the solid-state imaging element, and a vertical driver in the drawing includes the circuit configuration shown in FIG. 9. FIG. 11 illustrates an arrangement of the transfer gate electrodes that are disposed in a layer below the driving lines along line AA in FIG. 10. FIG. 12 stereoscopically illustrates an arrangement of the driving lines and the transfer gate electrodes.

[0076] A driving line V.sub.OUT1 shown in FIG. 9 corresponds to the driving line 14 in FIG. 7. To the driving line V.sub.OUT1, a driving pulse at the high voltage level V.sub.High is supplied through a PMOS switch ?1 and a driving pulse at the low voltage level V.sub.Low is supplied through an NMOS switch ?2. The PMOS switch ?1 is turned on when an input ?1 to a gate of the PMOS switch ?1 is Low, so that the voltage at the high voltage level V.sub.High is output to the driving line V.sub.OUT1. The PMOS switch ?1 is turned off when the input ?1 to the gate is High. The NMOS switch ?2 is turned on when an input ?2 to a gate of the NMOS switch ?2 is Low, so that the voltage at the low voltage level V.sub.Low is output to the driving line V.sub.OUT1. The NMOS switch ?2 is turned off when the input ?2 to the gate is Low.

[0077] A driving line V.sub.OUT2 corresponds to the driving line 15 in FIG. 7. To the driving line V.sub.OUT2, a driving pulse at the high voltage level V.sub.High is supplied through a PMOS switch ?3 and a driving pulse at the low voltage level V.sub.Low is supplied through an NMOS switch ?4. The PMOS switch ?3 is turned on when an input ?3 to a gate of the PMOS switch ?3 is Low, so that the voltage at the high voltage level V.sub.High is output to the driving line V.sub.OUT2. The PMOS switch ?3 is turned off when the input ?3 to the gate is High. The NMOS switch ?4 is turned on when an input ?4 to a gate of the NMOS switch ?4 is High, so that the voltage at the low voltage level V.sub.Low is output to the driving line V.sub.OUT2. The NMOS switch ?4 is turned off when the input ?4 to the gate is Low.

[0078] A capacitance C.sub.para corresponds to a parasitic capacitance generated between the driving line V.sub.OUT1 and the driving line V.sub.OUT2.

[0079] FIG. 13 is a timing chart expressing a voltage change in the driving lines V.sub.OUT1 and V.sub.OUT2 in FIG. 9.

[0080] The driving line V.sub.OUT2 can be set to the floating state when the input ?3 to the gate of the PMOS switch ?3 is set to High and the input ?4 to the gate of the NMOS switch ?4 is set to Low. Here, the voltage V.sub.OUT2 of the driving line V.sub.OUT2 follows the voltage V.sub.OUT1 of the driving line V.sub.OUT1 by the capacitive coupling driving through the parasitic capacitance C.sub.para; therefore, the intermediate voltage level can be generated in the voltage V.sub.OUT2 of the driving line V.sub.OUT2.

Second Embodiment

[0081] Next, FIG. 14 is a circuit diagram of a second embodiment according to the present disclosure. In the second embodiment, a capacitance C.sub.design that is designed intentionally is added to the configuration shown in FIG. 9 between the driving line V.sub.OUT1 and the driving line V.sub.OUT2.

[0082] FIG. 15 stereoscopically illustrates an arrangement of the driving lines and the transfer gate electrodes in a case where the capacitance C.sub.design is added between the driving lines .

[0083] In regard to the type of capacitance C.sub.design, an arbitrary capacitance such as a MEM capacitance or a MOS capacitance can be used. The size of the capacitance C.sub.design is determined by calculating a change in potential by a capacitance division ratio.

Third Embodiment

[0084] Next, FIG. 16 is a circuit diagram of a vertical driver of a third embodiment according to the present disclosure.

[0085] The vertical driver of the third embodiment includes a pixel driving line 21 that can output an intermediate voltage level in addition to the high voltage level V.sub.High and the low voltage level V.sub.Low. To the pixel driving line 21, a switch 22A that turns on or off the supply of voltage at the high voltage level V.sub.High and a switch 23B that turns on or off the supply of voltage at the low voltage level V.sub.Low are connected. In addition, to the pixel driving line 21, a coupling driving line 24C is connected through a coupling capacitance 25 and a switch 26D that are connected in series. By turning off the switches 22A and 23B, the pixel driving line 21 can be set to the floating state.

[0086] FIG. 17 illustrates a circuit configuration in a case where the switch 22A, the switch 23B, and the switch 26D in FIG. 16 are achieved by a PMOS gate electrode, an NMOS gate electrode, and an NMOS gate electrode formed on a diffusion layer, respectively.

[0087] FIG. 18 is a timing chart in a case where the pixel driving line 21 in FIG. 16 outputs the intermediate voltage level.

[0088] By turning off the switches 22A and 23B after turning on the switch 26D, the pixel driving line 21 can be set to the floating state. Here, if the voltage of the coupling driving line 24C is changed from V.sub.High to V.sub.Low, the intermediate voltage level can be generated in the pixel driving line 21 by using the capacitive coupling.

[0089] After that, if the voltage of the coupling driving line 24C is returned to V.sub.High after the switch 26D is turned off and then the voltage of the coupling driving line 24C is changed from V.sub.High to V.sub.Low by turning on the switch 26D again, an intermediate voltage level that is different from the previous one can be generated in the pixel driving line 21.

[0090] As described above, the intermediate voltage level can be generated in the pixel driving line 21 by turning on or off the switch 26D that connects between the pixel driving line 21 and the coupling capacitance 25 and changing the voltage of the coupling driving line 24C at least once or more.

[0091] Note that it is also possible to change the capacitance value for coupling and adjust the potential variation amount by connecting a plurality of combinations of switches and capacitances to connect between the pixel driving line 21 and the coupling driving line 24C in parallel and adjusting the number of switches to be turned on or off.

[0092] The coupling driving line 24C may be shared among a plurality of pixel driving lines 21.

<Example of Using Intermediate Voltage Level>

[0093] FIG. 19 shows an effect in a case where the intermediate voltage level obtained by the first to third embodiments is used for charge transfer in the solid-state imaging element.

[0094] In a case where the intermediate voltage level is used for charge transfer, the transition of the pixel driving line that is driven previously in time by the capacitive coupling generates the intermediate potential in the pixel driving line that is driven next in time; therefore, the transition in the posterior stage does not occur before the transition and the potential state in the anterior stage. As a result, even if the transition to the intermediate potential in the next line has started at the same time as the line that is driven previously, the charges can be transferred to the posterior stage for sure and the pulse intervals can be reduced. Accordingly, it is expected that the charge transfer efficiency and the transfer speed can be improved and moreover, the operation speed of the entire solid-state imaging element can be improved.

<Example of Using Image Sensor>

[0095] FIG. 20 shows examples of using an image sensor to which the present disclosure has been applied.

[0096] The image sensor described above is applicable to various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray, which will be described below. [0097] Devices for photographing an image for appreciation, such as a digital camera and a portable device with a camera function; [0098] Devices to be used for traffic to enable safe driving, for example automatic stop, recognition of a state of a driver, and so on; for example, an on-vehicle sensor that photographs an image in front of, behind, around, or inside the vehicle, a monitor camera that monitors a traveling vehicle and a road, and a range sensor that measures the distance between vehicles; [0099] Devices to be used for home appliances such as a TV, a refrigerator, and an air conditioner to photograph a user's gesture and perform an operation indicated by the gesture; [0100] Devices to be used for medical or healthcare purposes, such as an endoscope and an angiography device using an infrared ray; [0101] Devices to be used for security, such as a surveillance camera to prevent crimes, and a camera for person authentication; [0102] Devices to be used for cosmetics, such as a skin checker to photograph skin, and a microscope to photograph scalp; [0103] Devices to be used for sports, such as an action camera and a wearable camera for sport applications; and [0104] Devices to be used for agriculture, such as a camera to monitor a condition of a farm or crops.

[0105] The embodiment of the present disclosure is not limited to the above-described embodiment, and various changes can be made without departing from the concept of the present disclosure.

[0106] The present disclosure can employ configurations as described below.

[0107] (1) A solid-state imaging element including:

[0108] a first driving line configured to supply selectively to a posterior stage, a first voltage level that is output from a first power source and a second voltage level that is output from a second power source and lower than the first voltage level;

[0109] a second driving line that is different from the first driving line;

[0110] a capacitance that is formed between the first driving line and the second driving line; and

[0111] a floating setting unit configured to set the first driving line to a floating state.

[0112] (2) The solid-state imaging element according to (1), in which the first driving line set to the floating state is configured to supply to the posterior stage, a third voltage level between the first voltage level and the second voltage level in accordance with a change in voltage that is supplied to the second driving line by capacitive coupling.

[0113] (3) The solid-state imaging element according to (1) or (2), in which the floating setting unit comprises a first switch configured to connect between the first power source and the first driving line, and a second switch configured to connect between the second power source and the first driving line.

[0114] (4) The solid-state imaging element according to anyone of (1) to (3), in which the capacitance formed between the first driving line and the second driving line is a parasitic capacitance.

[0115] (5) The solid-state imaging element according to anyone of (1) to (4), in which the capacitance formed between the first driving line and the second driving line is an actual capacitance that is formed intentionally.

[0116] (6) The solid-state imaging element according to anyone of (1) to (5), in which the first driving line and the second driving line are pixel driving lines that are disposed adjacent to each other in a longitudinal direction.

[0117] (7) The solid-state imaging element according to any one of (1) to (5), in which the second driving line is a line dedicated to the capacitive cup link.

[0118] (8) The solid-state imaging element according to any one of (1) to (7), in which each of the first driving line and the second driving line comprises a plurality of driving lines.

[0119] (9) The solid-state imaging element according to any one of (2) to (8), in which the first driving line is configured to supply any of the first voltage level, the second voltage level, and the third voltage level to a transfer gate electrode in the posterior stage.

[0120] (10) A driving method fora solid-stage imaging element including a first driving line configured to supply selectively to a posterior stage, a first voltage level that is output from a first power source and a second voltage level that is output from a second power source and lower than the first voltage level, a second driving line that is different from the first driving line, a capacitance that is formed between the first driving line and the second driving line, and a floating setting unit configured to set the first driving line to a floating state, the method including the steps of:

[0121] setting the first driving line configured to supply the first voltage level to the posterior stage, to the floating state; and

[0122] lowering the voltage level to be supplied to the second driving line and supplying a third voltage level between the first voltage level and the second voltage level to the posterior stage from the first driving line by capacitive coupling.

[0123] (11) An electronic device including a solid-stage imaging element, the solid-stage imaging element including:

[0124] a first driving line configured to supply selectively to a posterior stage, a first voltage level that is output from a first power source and a second voltage level that is output from a second power source and lower than the first voltage level;

[0125] a second driving line that is different from the first driving line;

[0126] a capacitance that is formed between the first driving line and the second driving line; and

[0127] a floating setting unit configured to set the first driving line to a floating state.

REFERENCE SIGNS LIST

[0128] 11 to 13 Transfer gate electrode [0129] 14 to 16 Driving line [0130] 22A Switch [0131] 23B Switch [0132] 24C Coupling driving line [0133] 25 Coupling capacitance [0134] 26D Switch