Method and device for damping voltage harmonics in a multilevel power converter

Abstract

A method for reducing lower order harmonics of a power converter includes, for each phase leg of the converter: obtaining a voltage reference for the phase leg; for a present sample, obtaining a flux error of the output voltage of the leg; dividing the first sample flux error by a time period to obtain an average voltage error over said time period; subtracting an obtained processed average voltage error, based on the average voltage error, from the voltage reference to obtain a modified voltage reference for the phase leg; and providing the modified voltage reference to a modulation unit of the converter for controlling the phase leg.

Claims

1. A method for reducing lower order harmonics of a power converter, the method comprising, for each phase leg of the converter, the steps of: obtaining a voltage reference for the phase leg, wherein the phase leg has a plurality of cells; for a present sample, obtaining a flux error of the output voltage of the phase leg, wherein the obtaining of the flux error comprises: calculating a voltage error of the present sample by subtracting an obtained voltage reference for the phase leg for a preceding sample from an estimated voltage output of the phase leg for said preceding sample; and integrating the calculated voltage error over a sampling time period to obtain the flux error of the present sample; dividing the present sample flux error by a cycle time period to obtain an average voltage error over said time period; subtracting an obtained processed average voltage error, based on the average voltage error, from the voltage reference to obtain a modified voltage reference for the phase leg; and providing the modified voltage reference to a modulation unit of the converter for controlling the phase leg in a present cycle time period, generating, by the modulation unit, switching state signals to switch on or off of all of the cells in the phase leg using the modified voltage reference, thereby compensating for the average voltage error that is not compensated in the preceding sample to control the phase leg in the present cycle time period, and reducing the lower order harmonics of the phase leg.

2. The method of claim 1, wherein obtaining the processed average voltage error comprises multiplying the average voltage error by a gain.

3. The method of claim 2, wherein obtaining the processed average voltage error comprises applying a filter to the average voltage error.

4. The method of claim 2, wherein the cycle time period is the half switching cycle duration.

5. The method of claim 2, wherein sampling is performed every 10 s or less.

6. The method of claim 1, wherein obtaining the processed average voltage error comprises applying a filter to the average voltage error.

7. The method of claim 6, wherein the cycle time period is the half switching cycle duration.

8. The method of claim 6, wherein sampling is performed every 10 s or less.

9. The method of claim 1, wherein the cycle time period is the half switching cycle duration.

10. The method of claim 9, wherein sampling is performed every 10 is or less.

11. The method of claim 1, wherein sampling is performed every 10 s or less.

12. The method of claim 1, wherein the method is performed by a respective control unit of each phase leg.

13. The method of claim 1, wherein the modulation unit is for pulse-width modulation, PWM.

14. The method of claim 13, wherein the modulation unit is for phase shifted carrier based PWM.

15. A non-transitory computer program product comprising computer-executable components for causing a control unit for a phase leg of a power converter to perform the method of claim 1 when the computer-executable components are run on processor circuitry comprised in the control unit.

16. A control unit for a phase leg of a power converter, the control unit comprising: processor circuitry; and a storage unit storing instructions executable by said processor circuitry whereby said control unit is operative to: obtain a voltage reference for the phase leg, wherein the phase leg has a plurality of cells; for a present sample, obtain a flux error of the output voltage of the phase leg by: calculating a voltage error of the present sample by subtracting an obtained voltage reference for the phase leg for a preceding sample from an estimated voltage output of the phase leg for said preceding sample; and integrating the calculated voltage error over a sampling time period to obtain the flux error of the present sample; divide the present sample flux error by a time period to obtain an average voltage error over said time period; subtract an obtained processed average voltage error, based on the average voltage error, from the voltage reference to obtain a modified voltage reference for the phase leg; and provide the modified voltage reference to a modulation unit of the converter for controlling the phase leg in a present cycle time period, such that the modulation unit generates switching state signals to switch on or off of all of the cells in the phase leg using the modified voltage reference, thereby compensating for the average voltage error that is not compensated in the preceding sample to control the phase leg in the present cycle time period, and reducing the lower order harmonics of the phase leg.

17. A power converter comprising a plurality of phase legs, each of which comprising a control unit of claim 16.

18. The converter of claim 17, wherein the converter is a three-phase converter in delta configuration or Y configuration.

19. A non-transitory computer program product for reducing lower order harmonics of a power converter, the computer program product comprising computer program code which is able to, when run on processor circuitry of a control unit for a phase leg of the power converter, cause the control unit to: obtain a voltage reference for the phase leg, wherein the phase leg has a plurality of cells; for a present sample, obtain a flux error of the output voltage of the phase leg by: calculating a voltage error of the present sample by subtracting an obtained voltage reference for the phase leg for a preceding sample from an estimated voltage output of the phase leg for said preceding sample; and integrating the calculated voltage error over a sampling time period to obtain the flux error of the present sample; divide the present sample flux error by a time period to obtain an average voltage error over said time period; subtract an obtained processed average voltage error, based on the average voltage error, from the voltage reference to obtain a modified voltage reference for the phase leg; and provide the modified voltage reference to a modulation unit of the converter for controlling the phase leg in a present cycle time period, such that the modulation unit generates switching state signals to switch on or off of all of the cells in the phase leg using the modified voltage reference, thereby compensating for the average voltage error that is not compensated in the preceding sample to control the phase leg in the present cycle time period, and reducing the lower order harmonics of the phase leg.

20. The non-transitory computer program product according to claim 19, wherein the non-transitory computer program product is embodied on a non-transitory computer readable medium.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments will be described, by way of example, with reference to the accompanying drawings, in which:

(2) FIG. 1 is a schematic circuit diagram of an embodiment of an AC-AC converter in delta configuration, in accordance with the present invention.

(3) FIG. 2 is a schematic diagram illustrating flux error under ideal conditions, for an embodiment of a converter.

(4) FIG. 3 is a schematic diagram illustrating flux error under non-ideal conditions, for an embodiment of a converter.

(5) FIG. 4 is a schematic functional block diagram illustrating an embodiment of how to estimate phase leg voltage from individual cell capacitor voltages and switching function (or switching state) of the cells of a phase leg of an embodiment of a converter.

(6) FIG. 5 is a schematic functional flow chart of an embodiment of a method for controlling the flux error in a converter phase leg, in accordance with the present invention.

DETAILED DESCRIPTION

(7) Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown. However, other embodiments in many different forms are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout the description.

(8) The present disclosure provides a method which reduces the magnitude of lower order harmonics of a -connected chain-link converter (or any converter in general e.g. Y-connected) operated with phase shifted carrier based PWM (or any carrier based modulation). According to this method, the voltage reference is modified in each sampling to reduce the flux error. Herein, the time integral of voltage is defined as flux. The time integral of a difference between actual voltage generated by the converter and the reference voltage is defined as the flux error.

(9) A delta connected chain-link based STATCOM, as shown in FIG. 1 as an example of a power converter in accordance with the present invention, is a voltage source converter (VSC) which can behave like an inductor or capacitor, storing the reactive power in its cell capacitors. This causes lower order harmonics on the AC side of the converter. Also, in addition to this when a lesser pulse number per cell (less than 3.5) is used, then the triangle comparison based modulation scheme may generate lower order harmonics irrespective of the number of cells used (i.e., could be more than 20 cells). As an alternative to a STATCOM, the multilevel converter of the present invention may be a static VAR compensator (SVC).

(10) FIG. 1 schematically illustrates an embodiment of a chain-link converter 1 of the present invention. In the embodiment of FIG. 1, the chain-link converter 1 is in a delta configuration and in a full-bridge configuration. The converter 1 is configured to control and be connected to a three-phase AC system having the phases A, B and C. The converter 1 comprises three phase legs 2, each connected between two of the phases A, B and C. Each of the phase legs 2 comprises a plurality of series-connected converter cells 3. Each cell 3 comprises a capacitor 4. A current control 11 is comprised in the converter 1 in order to control the operation of each of the phase legs 2 of the converter 1, e.g. by setting reference voltages for the phase legs 2. In accordance with the present invention, the converter 1 also comprises a control unit 10 for each phase, here called 10a, 10b and 10c depending on the phase leg 2 it is configured to control. The control units 10 thus perform control on a lower (per phase) level in the converter than the current control 11. Each control unit 10 comprises a processor and a data storage unit, as well as other circuitry which may be appropriate. In accordance with the present invention, the control unit 10 implements a plurality of control functions on its phase leg 2 of the converter 1 for improving the operation of the converter 1 in accordance with the present invention. One or more of the control units 10 may be co-located with each other and/or with the current control 11, and may thus share components e.g. processor circuitry and/or data storage with each other.

(11) FIG. 2 is a schematic diagram illustrating flux error under ideal conditions, for an embodiment of a converter. The carrier signal (carrier) per cell 3, reference voltage signal (U.sub.ref) and the output voltage (U.sub.dc) of one cell 3 are shown. In any carrier based PWM, the time T1 is calculated according to the volt-second balance in every half cycle of the switching period (i.e. Tsw/2). The volt-second balance during Tsw/2 is expressed in Equation 2.
U.sub.dcT.sub.1U.sub.refT=0Equation 2

(12) Here, it is assumed that U.sub.ref is constant within the time Tsw/2 and the cell capacitor 4 voltage does not contain any voltage ripple. The flux error can be expressed as:
e.sub.=.sub.act.sub.refEquation 3
or:

(13) $\begin{array}{cc}{e}_{}={}_0^{T_1}{U}_{\mathrm{dc}}\mathrm{dt}-{}_0^{\frac{T_{\mathrm{sw}}}{2}}{U}_{\mathrm{ref}}\mathrm{dt}& \mathrm{Equation}4\end{array}$

(14) The flux error e.sub. is plotted in the bottom half of FIG. 2. It is observed that flux error reaches to zero at the end of each Tsw/2 (at the dashed help lines). But, in a real scenario, the cell capacitor voltage contains ripple or other non-idealities, whereby the reference voltage U.sub.ref within the period Tsw/2 may not be constant, as shown in FIG. 3. It is observed that the flux error is not zero at the end of each Tsw/2 period (again, at the dashed help lines). This eventually corresponds to the lower order harmonics in the converter generated voltage.

(15) FIG. 4 is a schematic logical block diagram of an embodiment of a mathematical model performed by a phase leg voltage estimator function 14 of the converter 1 for calculating the voltage of a phase leg 2 based on the voltages measured over the capacitors 4 of the cells 3 in the phase leg.

(16) The model depends on at least one switching state of each of the cells, Si(k1), which is +1, 0 or 1 depending on whether the cell 3 needs to be inserted in positive mode, bypass mode or negative mode respectively. It also depends on sensing the cell capacitor voltages or the sum of cell capacitor voltages in the phase leg. The voltage output of the converter phase leg, U.sub.o(k1) is calculated by the expression,

(17) $\begin{array}{cc}{U}_o\left(k-1\right)=\underset{i=1}{\overset{N}{.Math.}}\frac{S_i\left(k-1\right)*U_{\mathrm{dc},i}\left(k-1\right)}{N}& \mathrm{Equation}5\end{array}$
or by the expression,

(18) $\begin{array}{cc}{U}_o\left(K-1\right)=\underset{i=1}{\overset{N}{.Math.}}\frac{S_i\left(K-1\right)*U_{\mathrm{dc},\mathrm{avg}}\left(k-1\right)}{N}& \mathrm{Equation}6\end{array}$
where, U.sub.dc,i(k1) refers to the previous sample sensed cell capacitor voltages in the phase leg, and U.sub.dc,avg(k1) is the previous sample average of sensed cell capacitor voltages in the phase leg.

(19) The error in voltage estimation using the latter method may be high. Hence, the former expression is preferred over the latter one. The estimated converter voltage output U.sub.o(k1) is used as an input in FIG. 5.

(20) FIG. 5 is a schematic functional flow chart of an embodiment of a method for controlling the flux error in a converter phase leg. The current control 11 provides the reference voltage U.sub.ref for a sampling k of the control unit 10, which is thus obtained S1 by the control unit 10 of each phase leg 2. The current control 11 may e.g. update the voltage reference every 10 s to 1 s, e.g. every 100 s as indicated in the figure. The voltage reference may thus be the same for several consecutive samplings k of the control unit if the current control 11 has a longer sampling time than the sampling time of the control unit 10 which may typically have a sampling frequency of l 10 s or less.

(21) In an optional step, the control unit 10 may calculate S6 a voltage error U.sub.error of the present sample k by subtracting the obtained S1 voltage reference U.sub.ref for the phase leg for a preceding sample k1 from an estimated voltage output U.sub.o(k1) of the phase leg 2 for said preceding sample (k1) as discussed above. Then, in another optional step, the control unit 10 may integrate S7 the calculated S6 voltage error U.sub.error over the sampling time period used by the control unit 10 (which is typically in the order of 10 s or less) to obtain the flux error (.sub.error) of the present sample k. This is an example of how the flux error may be obtained S2 by the control unit 10. Other examples include that the flux error is calculated elsewhere and sent to the control unit 10.

(22) Then, the control unit 10 divides S3 the present sample flux error .sub.error(k) by a time period, e.g. T.sub.SW/2 as discussed herein, to obtain an average voltage error U.sup.avg.sub.error over said time period. In optional step(s) the average voltage error U.sup.avg.sub.error may be further processed to obtain a processed average voltage error Up.sup.proc.avg.sub.error. This may e.g. be done by multiplying S8 the average voltage error U.sup.avg.sub.error by a gain G, and/or by applying a filter 13 to the average voltage error U.sup.avg.sub.error (possibly as already multiplied by the gain G). The filter 13 may be used to suppress noise generated due to the switching frequency components in the feedback signal. The filter may be a low pass filter or band pass or resonant filter tuned to specific frequency components that needs to be damped. Although U.sup.avg.sub.error is called average voltage error, the waveform typically has DC+Low frequency AC+Switching/High frequency AC quantities. By means of the filter, it may be possible to compensate for the DC and preferable at least some of the low frequency AC quantities. Thus, the filter may be used to either remove the high frequency AC (low pass or band pass filter)termed as noise due to switching frequency components, or to allow only specific frequency components to pass through the filter, blocking (preferably all) other components (resonant filters).

(23) Then, the control unit 10 subtracts S4 the obtained processed average voltage error U.sup.proc.avg.sub.error, based on (and possibly the same as (depending on whether processing has been applied or not)) the average voltage error U.sup.avg.sub.error, from the voltage reference (U.sub.ref) to obtain a modified voltage reference U.sup.mod.sub.ref for the phase leg 2. The modified voltage reference U.sup.mod.sub.ref for the phase leg 2 is then provided S5 to the modulation unit 12 of the converter 1 for controlling the phase leg 2. The modulation unit, e.g. PWM module 12 may generate the switching state, Si(k) of all the cells in the converter phase leg 2. By means of the modulation, e.g. PWM, module, the converter 1 may output a voltage U.sub.o(k). By using the information of previous sample sensed cell capacitor voltages, U.sub.dc,i(k1) and the switching state of the cells Si(k1), U.sub.o(k1) for calculating the flux error of the present sample k may be computed in the phase leg voltage estimator block 14.

(24) The control unit may be caused to perform the method by means of running a computer program, as presented above. This computer program may be stored in the storage unit of the control unit 10, or be stored on an external medium, to form a computer program product. The computer program product comprises a computer readable (non-volatile) medium comprising a computer program in the form of computer-executable components. The computer program/computer-executable components may be configured to cause a control unit 10, e.g. as discussed herein, to perform an embodiment of the method of the present disclosure. The computer program/computer-executable components may be run on the processor circuitry of the control unit 10 for causing it to perform the method. The computer program product may e.g. be comprised in a storage unit or memory comprised in the control unit 10 and associated with the processor circuitry. Alternatively, the computer program product may be, or be part of, a separate, e.g. mobile, storage means, such as a computer readable disc, e.g. CD or DVD or hard disc/drive, or a solid state storage medium, e.g. a RAM or Flash memory.

EXAMPLE

(25) The logic to compensate flux error may in one embodiment be described as follows. The flux error (e.sub.) is calculated S2 at the end of every half switching sample (i.e. T.sub.sw/2). The flux error should go to zero, but it may not happen due to some practical considerations (e.g. ripple in the cell capacitor voltage, variation of reference voltage within T.sub.sw/2). Divide S3 the flux error (e.sub.) at the end of the half switching sample by the half switching sample duration

(26) $\left(\frac{T_{\mathrm{sw}}}{2}\right).$
This will give the average voltage error (U.sup.avg.sub.error) that was not compensated in the previous half switching sample. Subtract S4 this voltage error (U.sub.error.sup.avg) from the voltage reference (U.sub.ref) of the next sample k. The idea is to compensate for the average voltage error created in the previous sample k1 due to non-idealities in the coming sample. To improve the performance of compensation the update can be performed at every simulation sample (e.g. 10 s, i.e. the sampling rate of the control unit 10) rather than at the beginning of every half switching sample

(27) $\left(\frac{T_{\mathrm{sw}}}{2}\right).$
Hence, the voltage error (U.sup.avg.sub.error) is calculated and subtracted from the voltage reference every simulation step. This involves the calculation of flux error at every simulation step and dividing it by the half switching sample duration

(28) $\left(\frac{T_{\mathrm{sw}}}{2}\right).$
This is similar to using a moving window of

(29) $\frac{T_{\mathrm{sw}}}{2}$
to calculate the average voltage error and updating it in the voltage reference every simulation step. By this method, all the lower order harmonics other than the carrier harmonics can be damped effectively.

(30) With reference again to FIG. 5, the current controller 11 generates a reference voltage signal which is sampled (u.sub.ref.sup.s(k)) e.g. every 100 s. The actual converter voltage (U.sub.0(k)) is calculated every simulation step from the measured cell capacitor voltages and the switching state of the cell inside the valve control unit (VCU) which may be comprised in the control unit 10. The voltage error (U.sub.error(k)) is computed S6 between actual converter voltage and the sampled reference voltage. The integration S7 of voltage error produces flux error (.sub.error). The corresponding average voltage error over a period of T.sub.sw/2 is calculated S3 through the expression of Error! Reference source not found.7.

(31) $\begin{array}{cc}{U}_{\mathrm{error}}^{\mathrm{avg}}=\frac{{}_{\mathrm{error}}}{\left(\frac{T_{\mathrm{sw}}}{2}\right)}& \mathrm{Equation}7\end{array}$

(32) The reference voltage is updated S4 according to Equation 8.
U.sub.ref.sup.mod=U.sub.ref.sup.sU.sub.error.sup.avgEquation 8

(33) This modified reference voltage is sent to the PWM module 12 which performs the PSC for generating the PWM pulses.

(34) The present disclosure has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims.