Methods of forming semiconductor structures

Abstract

The present disclosure relates to a process for the manufacture of a high resistivity semiconductor substrate, comprising the following stages: providing a first substrate with an in-depth weakened layer; providing a second substrate with a layer of an oxide at the surface; attaching the first substrate to the second substrate so as to form a compound substrate comprising a layer of buried oxide; and cleaving the compound substrate at the level of the weakened layer. The process additionally comprises at least one stage of stabilization, in particular, a stabilization heat treatment, of the second substrate with the layer of oxide before the stage of cleaving at the level of the weakened layer.

Claims

1. A method of forming a semiconductor structure, the method comprising: providing a first substrate with an in-depth weakened layer; providing a second substrate with an oxide layer at a surface thereof; attaching the first substrate to the second substrate to form a compound substrate comprising a buried oxide layer, the first substrate comprising the in-depth weakened layer, the second substrate comprising the oxide layer; stabilizing at least the second substrate with the oxide layer at the surface; and after stabilizing at least the second substrate, cleaving the compound substrate at the weakened layer to form a semiconductor structure.

2. The method of claim 1, wherein stabilizing at least the second substrate comprises stabilizing at least the second substrate before attaching the first substrate to the second substrate.

3. The method of claim 1, wherein stabilizing at least the second substrate comprises nucleation, precipitation of precipitates, and growth of the precipitates.

4. The method of claim 1, wherein stabilizing at least the second substrate comprises heat treating at least the second substrate at each of a plurality of temperatures within a range from approximately 650 C. to approximately 1,200 C.

5. The method of claim 4, wherein each of the plurality of temperatures is maintained for a duration with a range extending from approximately 30 minutes to approximately 10 hours.

6. The method of claim 4, wherein heat treating at least the second substrate comprises exposing at least the second substrate to a nonoxidizing atmosphere.

7. The method of claim 4, wherein heat treating at least the second substrate comprises exposing at least the second substrate to an oxidizing atmosphere.

8. The method of claim 7, wherein exposing at least the second substrate to an oxidizing atmosphere comprises exposing at least the second substrate to an atmosphere comprising water and oxygen.

9. The method of claim 1, further comprising forming the weakened layer by ion implantation in the first substrate.

10. The method of claim 1, further comprising annealing the semiconductor substrate after cleaving the compound substrate at the weakened layer.

11. The method of claim 10, wherein annealing the semiconductor structure comprises exposing the semiconductor structure to a temperature within a range from approximately 1,075 C. to approximately 1,250 C.

12. The method of claim 11, wherein annealing the semiconductor structure comprises exposing the semiconductor structure to a temperature within a range from approximately 1,175 C. to approximately 1,230 C.

13. The method of claim 10, wherein annealing the semiconductor structure comprises exposing the semiconductor structure to an annealing condition for a period of time within a range from approximately 15 seconds to approximately 120 seconds.

14. The method of claim 13, wherein annealing the semiconductor structure comprises exposing the semiconductor structure to an annealing condition for a period of time within a range from approximately 20 seconds to approximately 90 seconds.

15. The method of claim 10, wherein annealing the semiconductor structure comprises exposing the semiconductor structure to a nonoxidizing atmosphere.

16. The method of claim 15, wherein exposing the semiconductor structure to a nonoxidizing atmosphere comprises exposing the semiconductor structure to an atmosphere comprising at least one gas selected from the group consisting of hydrogen and argon.

17. The method of claim 16, wherein exposing the semiconductor structure to a nonoxidizing atmosphere comprises exposing the semiconductor structure to an atmosphere comprising approximately 50% hydrogen or less.

18. The method of claim 1, further comprising attaching a residue of the first substrate to a third substrate after cleaving the compound substrate at the weakened layer, the third substrate comprising a layer of an oxide.

19. The method of claim 1, wherein the first substrate comprises a semiconductor material.

20. The method of claim 1, wherein the second substrate comprises silicon.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The disclosure will be explained in more detail in the following by means of advantageous embodiments and with the support of the following accompanying figures, in which:

(2) FIG. 1 diagrammatically illustrates stages of a process for the manufacture of a high resistivity semiconductor substrate according to a first example embodiment of the present disclosure; and

(3) FIG. 2 diagrammatically illustrates stages of a process for the manufacture of a high resistivity semiconductor substrate according to a second example embodiment of the present disclosure.

DETAILED DESCRIPTION

(4) In the following description of examples of embodiments of a process for the manufacture of a high resistivity semiconductor substrate, analogous reference signs can be used to denote the same elements repeated in the different embodiments. Furthermore, the description of elements already described may be omitted for the sake of conciseness.

(5) A first example embodiment of a process for the manufacture of a high resistivity semiconductor substrate will now be described with reference to FIG. 1. In this embodiment, the transfer of a layer of a semiconductor material will be carried out from a donor substrate toward a receiver substrate.

(6) As illustrated in Stage (I) of FIG. 1, a donor substrate 101 having an in-depth weakened layer 102 is provided for the purpose of carrying out a layer transfer toward a receiver substrate. The substrate 101 can be a semiconductor material, for example, silicon, germanium or a compound of silicon and germanium. Generally, the donor substrate 101 may include one or more alloys of semiconductors Groups III-V and/or one or more alloys of semiconductors of Group IV.

(7) As illustrated in Stage (II) of FIG. 1, a substrate 103 having an oxide layer 104 at the surface is provided for the purpose of receiving a transferred semiconductor layer. The substrate 103 may include silicon and, in particular, interstitial oxygen with a concentration of at least approximately 1210.sup.17 atoms.Math.cm.sup.3. The oxide layer 104 may be a layer of a natural oxide or a layer of SiO.sub.2 obtained by growth or otherwise deposited. The layer 104 may also be, for example, an insulator used in a semiconductor of an alumina (Al.sub.2O.sub.3) type or of a nitride type (e.g., Si.sub.3N.sub.4).

(8) As illustrated in Stage (III) of FIG. 1, before the transfer of a layer from the donor substrate 101 and, in particular, before being attached to the donor substrate 101, the substrate 103 including the oxide layer 104 at the surface may be subjected to at least one stage of stabilization treatment of the interstitial oxygen. This stage can be a stage of nucleation, precipitation, and growth of the precipitates. The stabilization can be a heat treatment comprising several stationary temperature phases. This treatment, in particular, a stationary temperature phase, can be carried out under an atmosphere of an oxidizing type, in particular, based on water and on oxygen, or else under an atmosphere of a nonoxidizing type, in particular, of a neutral type, with a gas based on argon. The substrate 103 comprising the oxide layer 104 can thus be subjected to a temperature, in particular, to stationary temperature phases, within a range from approximately 650 C. to approximately 1,200 C. Furthermore, this treatment, in particular, each stationary temperature phase, can last for approximately 30 minutes to approximately 10 hours, such as from approximately 1 hour to approximately 8 hours.

(9) Subsequently, after the stabilization treatment, as illustrated in Stage (IV) of FIG. 1, the donor substrate 101 may be attached, such as by adhesively bonding, (e.g., by molecular adhesion or any other method of adhesively bonding semiconductors) to the receiver substrate 103 via the oxide layer 104, so as to form a compound substrate 105 of the SOI type with a buried oxide layer 104.

(10) Subsequently, after the adhesive bonding stage, as illustrated in Stage (V) of FIG. 1, a portion 1012 of the donor substrate 101 may be detached from the compound substrate 105 by cleaving at the level of the in-depth weakened layer 102 so as to leave a transferred layer 1011 of the donor substrate 101 attached to the receiver substrate 103 via the oxide layer 104, thus forming a new compound substrate 106 comprising the transferred layer 1011. It is then possible to improve the surface roughness of the transferred layer 1011 by subjecting the compound substrate 106 to one or more smoothing heat treatments, in particular, of the rapid annealing, i.e., RTA-type. Furthermore, the residue 1012 of the donor substrate 101 can be recycled to form a new donor substrate in another layer transfer process.

(11) The compound substrates 105 and 106 may both be structures of HiOi HR SOI type, namely, of the type of high resistivity silicon-on-insulator having a high concentration of interstitial oxygen. Given that stabilization of the interstitial oxygen has been carried out before the layer transfer, in other words, before the cleaving stage, and thus before any smoothing annealing, it is possible to obtain HiOi HR SOI substrates with interface state densities of less than 510.sup.11 cm.sup.2.Math.eV.sup.1 and mobilities of the carriers in the SOI of greater than 700 cm.sup.2.Math.V.sup.1.Math.s.sup.1 for the electrons. After removal of the SOI film and aluminium on a buried oxide contact, the fixed charge values in the buried oxide can then be less than 310.sup.10 cm.sup.2 and the crest interface state densities can be less than 510.sup.10 cm.sup.2.Math.ev.sup.1.

(12) In other words, the electrical (in particular, interfacial) properties of the compound substrates 105 and 106 are markedly improved in comparison with HiOi HR SOI substrates obtained by conventional methods, that is to say, for which the stabilization stage would have been carried out after the smoothing annealing(s).

(13) A second example embodiment of a process for the manufacture of a high resistivity semiconductor substrate will now be described with reference to FIG. 2. The second embodiment repeats all the characteristics of the first embodiment and, in addition, gives details of optional process stages.

(14) As illustrated in Stage (I) of FIG. 2, a donor substrate 201 is provided, which can be the same as the donor substrate 101 of the first embodiment, as depicted in FIG. 1. The substrate 201 can thus also be a semiconductor material, such as silicon, germanium or a compound of silicon and germanium. Generally, the donor substrate 201 may include one or more alloys of semiconductors of Groups III-V and/or one or more alloys of semiconductors of Group IV.

(15) Stage (II) of FIG. 2 illustrates that the donor substrate 201 can subsequently be subjected to a stage of in-depth weakening in order to provide an in-depth weakened layer 202 for the purpose of carrying out a layer transfer toward a receiver substrate, as in the first embodiment. This stage can be carried out, in particular, by ion implantation, especially by implantation of ionic entities, such as H.sup.+ and/or He.sup.+.

(16) As illustrated in Stage (III) of FIG. 2, a substrate 203 having a layer of oxide 204 at the surface is also provided for the purpose of receiving a transferred semiconductor layer. Like the substrate 103 of the first embodiment (FIG. 1), the substrate 203 of the second embodiment can include silicon and, in particular, interstitial oxygen with a concentration of at least approximately 1210.sup.17 atoms.Math.cm.sup.3. Still analogous to the first embodiment, the layer of oxide 204 may be a layer of a natural oxide, a layer of SiO.sub.2, obtained by growth or else deposited, or also an insulator used in semiconductors of an alumina (Al.sub.2O.sub.3) type or of a nitride type (e.g., Si.sub.3N.sub.4).

(17) As illustrated in Stage (IV) of FIG. 2, before the transfer of a layer from the donor substrate 201 and, in particular, before being attached to the donor substrate 201, the substrate 203 having the layer of oxide 204 at the surface may be subjected to at least one stage of a stabilization treatment of the interstitial oxygen. Analogous to the first embodiment, the stabilization treatment can be a stage of nucleation, precipitation, and growth of the precipitates. It can thus be a heat treatment comprising several stationary temperature phases. This treatment, in particular, a stationary temperature phase, can be carried out under an atmosphere of an oxidizing type, in particular, based on water and on oxygen, or else under an atmosphere of a nonoxidizing type, in particular, of a neutral type, with a gas based on argon. The substrate 203 having the layer of oxide 204 can thus also be subjected to a temperature, in particular, to stationary temperature phases, within a range from approximately 650 C. to approximately 1,200 C. Furthermore, this treatment, in particular, each stationary temperature phase, can last from approximately 30 minutes to approximately 10 hours, such as from approximately 1 hour to approximately 8 hours.

(18) After stabilization, as illustrated in Stage (V) of FIG. 2, analogous to the adhesive bonding stage of the first embodiment, the donor substrate 201 and the receiver substrate 203 may be adhesively bonded at the level of the layer of oxide 204 to form a compound substrate 205 of the SOI type with the layer of buried oxide 204. In this instance also, the adhesive bonding can be carried out by molecular adhesion or any other method for the adhesive bonding of semiconductor layers.

(19) Subsequently, as illustrated in Stage (VI) of FIG. 2, adhesive bonding may be followed by cleaving, in which a portion 2012 of the donor substrate 201 is detached from the compound substrate 205 by cleaving at the level of the in-depth weakened layer 202. This cleaving may leave a transferred layer 2011 of the donor substrate 201 attached to the receiver substrate 203 by the layer of oxide 204, thus forming a new compound substrate 206 that includes the transferred layer 2011. Such cleaving can be carried out by subjecting the compound substrate 205 to a temperature in a range from approximately 300 C. to approximately 600 C. for a period of time of approximately 30 minutes to approximately 5 hours, under a neutral atmosphere of N.sub.2 or of Ar.

(20) Subsequently, after the cleaving stage, Stage (VII) of FIG. 2 illustrates an optional subsequent smoothing stage which makes it possible to improve the roughness of the exposed surface 207 of the transferred layer 2011. This stage can be carried out by heat treatment including one or more annealings, such as rapid annealings, i.e., RTAs. The compound substrate 206 can then be exposed to a temperature within a range from approximately 1,075 C. to approximately 1,250 C., such as from approximately 1,175 C. to approximately 1,230 C., such as a temperature of approximately 1,200 C. The temperature may be maintained for a period of time from approximately 15 seconds to approximately 120 seconds, such as from approximately 20 seconds to approximately 90 seconds, such as for a period of time of approximately 30 seconds. The compound substrate 206 may be maintained under an atmosphere of the nonoxidizing type, such as an atmosphere of argon and/or hydrogen in a composition that can range from 0% to approximately 50% of hydrogen.

(21) Finally, as mentioned above, the residue 2012 of the donor substrate 201 may be recycled in order to form a new donor substrate in another layer transfer process.

(22) Thus, analogously to the first embodiment, it is possible in the second embodiment to obtain compound substrates 205 and 206 of HiOi HR SOI type, namely, of the type of high resistivity silicon-on-insulator having a high concentration of interstitial oxygen. In particular, given that stabilization of the interstitial oxygen was performed before the layer transfer, in other words, before the cleaving stage, and thus before any smoothing annealing, just as in the first embodiment, it is possible in the second embodiment to obtain HiOi HR SOI substrates with interface state densities of less than 510.sup.11 cm.sup.2.Math.eV.sup.1 and mobilities of the carriers in the SOI of greater than 700 cm.sup.2.Math.V.sup.1.Math.s.sup.1 for the electrons. After removal of the SOI film and aluminium on a buried oxide contact, the fixed charge values in the buried oxide can then be less than 310.sup.10 cm.sup.2 and the crest interface state densities can be less than 510.sup.10 cm.sup.2.Math.eV.sup.1.

(23) In other words, just like those of the compound substrates 105 and 106, the electrical properties (in particular, interfacial properties) of the compound substrates 205 and 206 are also markedly improved in comparison with HiOi HR SOI substrates obtained by conventional methods, that is to say, for which the stabilization stage would have been carried out after the smoothing annealing(s).

(24) Additional non limiting example embodiments of the disclosure are described below.

Embodiment 1

(25) A method of forming a semiconductor structure, the method comprising attaching a first substrate to a second substrate to form a compound substrate comprising a buried oxide layer stabilizing at least the second substrate; and after stabilizing at least the second substrate, cleaving the compound substrate at the weakened layer to form a semiconductor structure. The first substrate comprises a weakened layer, and the second substrate comprises a layer of an oxide.

Embodiment 2

(26) The method of Embodiment 1, wherein stabilizing at least the second substrate comprises stabilizing at least the second substrate before attaching the first substrate to the second substrate.

Embodiment 3

(27) The method of Embodiment 1 or Embodiment 2, wherein stabilizing at least the second substrate comprises nucleation, precipitation of precipitates, and growth of the precipitates.

Embodiment 4

(28) The method of any one of Embodiments 1 through 3, wherein stabilizing at least the second substrate comprises heat treating the second substrate.

Embodiment 5

(29) The method of Embodiment 4, wherein stabilizing at least the second substrate comprises heat treating at least the second substrate at each of a plurality of temperatures within a range from approximately 650 C. to approximately 1,200 C.

Embodiment 6

(30) The method of Embodiment 5, wherein each of the plurality of temperatures is maintained for a duration with a range extending from approximately 30 minutes to approximately 10 hours.

Embodiment 7

(31) The method of Embodiment 6, wherein each of the plurality of temperatures is maintained for a duration with a range extending from approximately 1 hour to approximately 8 hours.

Embodiment 8

(32) The method of any one of Embodiments 4 through 7, wherein heat treating at least the second substrate comprises exposing at least the second substrate to a nonoxidizing atmosphere.

Embodiment 9

(33) The method of Embodiment 8, wherein exposing at least the second substrate to a nonoxidizing atmosphere comprises exposing at least the second substrate to an atmosphere comprising water and oxygen.

Embodiment 10

(34) The method of any one of Embodiments 4 through 7, wherein heat treating at least the second substrate comprises exposing at least the second substrate to an oxidizing atmosphere.

Embodiment 11

(35) The method of Embodiment 10, wherein exposing at least the second substrate to an oxidizing atmosphere comprises exposing at least the second substrate to an atmosphere comprising argon.

Embodiment 12

(36) The method of any one of Embodiments 1 through 11, further comprising forming the weakened layer by ion implantation in the first substrate.

Embodiment 13

(37) The method of any one of Embodiments 1 through 12, further comprising annealing the semiconductor substrate after cleaving the compound substrate at the weakened layer.

Embodiment 14

(38) The method of Embodiment 13, wherein annealing comprises rapid thermal annealing.

Embodiment 15

(39) The method of Embodiment 13 or Embodiment 14, wherein annealing the semiconductor structure comprises exposing the semiconductor structure to a temperature within a range from approximately 1,075 C. to approximately 1,250 C.

Embodiment 16

(40) The method of Embodiment 15, wherein annealing the semiconductor structure comprises exposing the semiconductor structure to a temperature within a range from approximately 1,175 C. to approximately 1,230 C.

Embodiment 17

(41) The method of Embodiment 16, wherein annealing semiconductor structure comprises exposing the semiconductor structure to a temperature of approximately 1,200 C.

Embodiment 18

(42) The method of any one of Embodiments 13 through 17, wherein annealing the semiconductor structure comprises exposing the semiconductor structure to an annealing condition for a period of time within a range from approximately 15 seconds to approximately 120 seconds.

Embodiment 19

(43) The method of Embodiment 18, wherein annealing the semiconductor structure comprises exposing the semiconductor structure to an annealing condition for a period of time within a range from approximately 20 seconds to approximately 90 seconds.

Embodiment 20

(44) The method of Embodiment 19, wherein annealing the semiconductor structure comprises exposing the semiconductor structure to an annealing condition for approximately 30 seconds.

Embodiment 21

(45) The method of any one of Embodiments 13 through 20, wherein annealing the semiconductor structure comprises exposing the semiconductor structure to a nonoxidizing atmosphere.

Embodiment 22

(46) The method of Embodiment 21, wherein exposing the semiconductor structure to a nonoxidizing atmosphere comprises exposing the semiconductor structure to an atmosphere comprising at least one gas selected from the group consisting of hydrogen and argon.

Embodiment 23

(47) The method of Embodiment 22, wherein exposing the semiconductor structure to a nonoxidizing atmosphere comprises exposing the semiconductor structure to an atmosphere comprising approximately 50% hydrogen or less.

Embodiment 24

(48) The method of any one of Embodiments 1 through 23, further comprising attaching a residue of the first substrate to a third substrate after cleaving the compound substrate at the weakened layer, the third substrate comprising a layer of an oxide.

Embodiment 25

(49) The method of Embodiment any one of Embodiments 1 through 24, wherein the first substrate comprises a semiconductor material.

Embodiment 26

(50) The method of Embodiment 25, wherein the semiconductor material comprises at least one element selected from the group consisting of the elements of Groups III-V of the Periodic Table.

Embodiment 27

(51) The method of Embodiment 26, wherein the semiconductor material comprises at least one alloy comprising at least one element of Group IV of the Periodic Table.

Embodiment 28

(52) The method of Embodiment 27, wherein the semiconductor material comprises at least one material selected from the group consisting of silicon, germanium, and compounds comprising silicon and germanium.

Embodiment 29

(53) The method of Embodiment 26, wherein the semiconductor material comprises at least one alloy comprising at least one element of Group III of the Periodic Table and at least one element of Group V of the Periodic Table.

Embodiment 30

(54) The method of any one of Embodiments 1 through 29, wherein the second substrate comprises silicon.

Embodiment 31

(55) The method of Embodiment 30, wherein the second substrate comprises silicon exhibiting a concentration of interstitial oxygen of at least approximately 1210.sup.17 atoms.Math.cm.sup.3.

(56) While the present invention has been described herein with respect to certain illustrated embodiments, those of ordinary skill in the art will recognize and appreciate that it is not so limited. Rather, many additions, deletions, and modifications to the illustrated embodiments may be made without departing from the scope of the invention as hereinafter claimed, including legal equivalents thereof. In addition, features from one embodiment may be combined with features of another embodiment while still being encompassed within the scope of the invention as contemplated by the inventors. Further, embodiments of the disclosure have utility with different and various semiconductor structure types and configurations.