Semiconductor stack for converter with snubber capacitors

Abstract

A semiconductor stack for a converter comprises two series-connected semiconductor switches; two terminals for connecting a cell capacitor, which are connected to one another by the two semiconductor switches; at least one cooling element arranged between the semiconductor switches; a frame, by which the semiconductor switches and the cooling element are fixed to one another and which provides the terminals; and at least two snubber capacitors which are mechanically fixed to the frame and which are connected in parallel, are connected to the terminals and which in each case form a commutation loop with the semiconductor switches.

Claims

1. A semiconductor stack for a converter, the semiconductor stack comprising: two series-connected semiconductor switches; two terminals for connecting a cell capacitor, which are connected to one another by the two semiconductor switches; at least one cooling element arranged between the semiconductor switches; a frame, by which the semiconductor switches and the cooling element are fixed to one another and which provides the terminals; two snubber capacitors which are mechanically fixed to the frame and which are connected in parallel, which are connected to the terminals and which are arranged on opposite sides of the semiconductor stack spatially near the semiconductor switches to form two parallel commutation loops with the semiconductor switches; a snubber diode, wherein the parallel-connected snubber capacitors are connected to one end of the two series-connected semiconductor switches via the snubber diode; a snubber resistor connected in parallel with the snubber diode; and a choke coil which is inserted between the cell capacitor and one of the semiconductor switches and which is used for controlling a change of a turn-off current over time between the snubber diode and the semiconductor switches, wherein the two series-connected semiconductor switches, the at least one cooling element, the at least two snubber capacitors, the snubber diode and the snubber resistor are coupled to each other, using the frame, to form a stack.

2. The semiconductor stack as claimed in claim 1, further comprising: at least four snubber capacitors which are mechanically fixed to the frame.

3. The semiconductor stack as claimed in claim 2, wherein two snubber capacitors are arranged on opposite sides of the semiconductor stack.

4. The semiconductor stack as claimed in claim 2, wherein two snubber capacitors are arranged spatially alongside one another on one side of the semiconductor stack.

5. The semiconductor stack as claimed in claim 2, wherein the snubber capacitors are embodied such that they are similar with respect to capacitance.

6. The semiconductor stack as claimed in claim 2, further comprising: another two series-connected semiconductor switches, the two series-connected semiconductor switches forming a first pair of series-connected semiconductor switches and the another two series-connected semiconductor switches forming a second pair of series-connected semiconductor switches, the first and second pairs of series-connected semiconductor switches for connecting in pairs to two cell capacitors; the at least two snubber capacitors forming first snubber capacitors which are mechanically fixed to the frame and which are connected in parallel and which in each case form a commutation loop with the first pair of semiconductor switches; and at least two second snubber capacitors which are mechanically fixed to the frame and which are connected in parallel and which in each case form a commutation loop with the second pair of semiconductor switches.

7. The semiconductor stack as claimed in claim 2, wherein the semiconductor switches are selected from: transistors, thyristors, IGBTs, integrated gate-commuted thyristors, reverse-conducting insulated gate bipolar transistors and reverse-conducting insulated gate-commuted thyristors.

8. The semiconductor stack as claimed in claim 1, wherein two snubber capacitors are arranged spatially alongside one another on one side of the semiconductor stack.

9. The semiconductor stack as claimed in claim 8, wherein the snubber capacitors are embodied such that they are similar with respect to capacitance.

10. The semiconductor stack as claimed in claim 1, wherein the snubber capacitors are embodied such that they are similar with respect to capacitance.

11. The semiconductor stack as claimed in claim 1, further comprising: another two series-connected semiconductor switches, the two series-connected semiconductor switches forming a first pair of series-connected semiconductor switches and the another two series-connected semiconductor switches forming a second pair of series-connected semiconductor switches, the first and second pairs of series-connected semiconductor switches for connecting in pairs to two cell capacitors; the at least two snubber capacitors forming first snubber capacitors which are mechanically fixed to the frame and which are connected in parallel and which in each case form a commutation loop with the first pair of semiconductor switches; and at least two second snubber capacitors which are mechanically fixed to the frame and which are connected in parallel and which in each case form a commutation loop with the second pair of semiconductor switches.

12. The semiconductor stack as claimed in claim 11, wherein the first snubber capacitors are connected to one another via a first busbar, the second snubber capacitors are connected to one another via a second busbar, and the first snubber capacitors are connected to the second snubber capacitors via another busbar, wherein the at least one cooling element comprises a heat sink, the another busbar being fixed to the heat sink between the pairs of semiconductor switches.

13. The semiconductor stack as claimed in claim 1, wherein the semiconductor switches are selected from: transistors, thyristors, IGBTs, integrated gate-commuted thyristors, reverse-conducting insulated gate bipolar transistors and reverse-conducting insulated gate-commuted thyristors.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) Exemplary embodiments of the invention are described in detail below with reference to the accompanying figures.

(2) FIG. 1 shows a circuit diagram of a two-level converter.

(3) FIG. 2 shows circuit symbols for possible semiconductor switches.

(4) FIG. 3 shows a circuit diagram for a semiconductor stack in accordance with one embodiment of the invention.

(5) FIG. 4 schematically shows a semiconductor stack in accordance with one embodiment of the invention.

(6) FIG. 5 schematically shows a semiconductor stack in accordance with a further embodiment of the invention.

(7) FIG. 6 shows a circuit diagram for a semiconductor stack in accordance with a further embodiment of the invention.

(8) FIG. 7 shows a three-dimensional view of a semiconductor stack in accordance with one embodiment of the invention.

(9) The reference signs used in the figures and their meanings are summarized in the List of reference signs. In principle, identical or similar parts are provided with the same reference signs.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

(10) FIG. 1 schematically illustrates a two-level voltage source converter 10 comprising a commutation loop 12 between two semiconductor switches S.sub.1, S.sub.2, a capacitor C.sub.dc being arranged in said commutation loop. Said loop 12 has a leakage inductance or commutation impedance L.sub.com.

(11) If a commutation of the current occurs between the two switches, the current i does not fall abruptly owing to the leakage inductance, but rather is temporally dependent, which leads to voltage spikes that load the semiconductor switches. The overvoltage v that occurs is calculated here by v=L.sub.com*di/dt.

(12) As is illustrated in FIG. 2, the semiconductor switches S.sub.1, S.sub.2 can comprise for example a transistor, thyristor, IGBT, IGCT, RC-IGBT, RC-IGCT, etc.

(13) FIG. 3 shows a two-level converter 10 comprising further switching components in order to prevent or at least to reduce voltage spikes generated by the leakage inductance L.sub.com. The circuit shown in FIG. 3 is a so-called RCLD damping circuit. By way of example, the components of the converter apart from the cell capacitor C.sub.dc are combined in a common module/stack, wherein the cell capacitor C.sub.dc can be connected to the module/stack via terminals 14 and 16.

(14) Firstly, a snubber capacitor C.sub.cl1 can be connected in parallel with the cell capacitor C.sub.dc and in parallel with the series-connected semiconductor switches S.sub.1, S.sub.2, which is situated in spatial proximity to the two semiconductor switches S.sub.1, S.sub.2. In this way, the commutation loop 12 is reduced in size and the inductance of the lines is reduced or the inductance L.sub.s is coupled out of the commutation loop 12.

(15) In the case of undamped oscillations (resonances) between the snubber capacitor and the cell or main capacitor C.sub.dc, a snubber diode (damping diode) D.sub.cl and a snubber resistor (damping resistor) R.sub.s can be inserted into the commutation loop 12.

(16) If the turn-off current or its change over time di/dt is intended to be controlled (for example between the diode D.sub.cl and the semiconductor switches S.sub.1, S.sub.2) and/or if at least a portion of the switching losses of the semiconductor switches S.sub.1, S.sub.2 is intended to be passed into the snubber resistor R.sub.s (for example for IGBTs as semiconductor switches S.sub.1, S.sub.2), a di/dt inductor inductance (i.e., a choke coil) L.sub.i can be introduced. In this case, the inductance L.sub.i can be inserted between the cell capacitor C.sub.dc and one of the semiconductor switches S.sub.1, S.sub.2. In this case, one end of the resistor R.sub.s can be connected between the cell capacitor and the inductance L.sub.i and/or one end of the diode D.sub.cl can be connected between the inductance L.sub.i and the semiconductor switch S.sub.1, S.sub.2.

(17) It is also possible for the resistor R.sub.s, the inductance L.sub.i and the diode D.sub.cl not to be connected to the terminal 14, but rather to the other terminal 16.

(18) In order to reduce the leakage inductance further, not just one snubber capacitor but rather a plurality of parallel-connected snubber capacitors C.sub.cl1, C.sub.cl2 can be used, which form a plurality of commutation loops 12, 12.

(19) As is shown in FIG. 4, the two semiconductor switches S.sub.1, S.sub.2 and the diode D.sub.cl can be arranged together in a stack 18. In this case a respective cooling element 20 or cooling plate 20 is arranged between two semiconductor components S.sub.1, S.sub.2.

(20) The stack can comprise a frame 22, by which the components S.sub.1, S.sub.2, D.sub.cl and 20 can be pressed together. A so-called presspack arises in this way.

(21) As is shown in FIG. 5, the diode D.sub.cl can also be arranged in an additional stack 24. The stack 18 then comprises only the semiconductor switches S.sub.1, S.sub.2 and the cooling elements 20.

(22) The stack 18 can be connected to the capacitors C.sub.cl1 and C.sub.cl2 and to the other elements R.sub.s, L.sub.i by means of cables, lines and/or busbars.

(23) Furthermore, the capacitors C.sub.cl1 and C.sub.cl2 and optionally the other components R.sub.s, L.sub.i are mechanically connected to the stack 18 and in particular the frame 18 thereof.

(24) In particular, the capacitors C.sub.cl1 and C.sub.cl2 arranged at the sides of the stack 18 form two parallel commutation loops 12, 12.

(25) FIG. 6 shows a circuit diagram for the presspack or stack 18 shown in FIG. 7 and comprising two series-connected half-bridges 10, 10 or two-level converters 10, 10. In the example illustrated, the semiconductor switches S.sub.1, S.sub.2, S.sub.3 and S.sub.4 are RC-IGCTs, but can also be RC-IGBTs or IGBTs or IGCTs with diodes.

(26) The semiconductor switches S.sub.1, S.sub.2, S.sub.3 and S.sub.4 are connected in series. Moreover, in the converter 10 the diode D.sub.cl, the inductor L.sub.i and the resistor R.sub.s are connected to the upper, first terminal 14, while in the converter 10 these components are connected to the lower, second terminal 16. In particular, there is no need for any additional insulation between the converters 10 and 10. The converters 10 and 10 can jointly use a heat sink 20 or a cooling box 20.

(27) Only the components enclosed by a border in FIG. 6 are illustrated in FIG. 7. The snubber diode D.sub.cl is connected to the semiconductor stack 18 or a mounting clamp 26. The electrically conductive cooling element 20 between the snubber diode D.sub.cl and the semiconductor switch S.sub.1 is connected via a conductive connection 28 to an upper, first snubber busbar 34. Spatially parallel to the stack 18, four snubber capacitors C.sub.cl1, C.sub.cl2, C.sub.cl1, C.sub.cl2 are arranged laterally alongside the stack 18 and are connected to the first snubber busbar 34 at an upper end.

(28) In this case, the capacitors C.sub.cl1, C.sub.cl1 are arranged on one side and the capacitors C.sub.cl2, C.sub.cl2 on the opposite side of the stack 18.

(29) At their lower end, the capacitors C.sub.cl1, C.sub.cl1 are connected to a first central snubber busbar 36 and the capacitors C.sub.cl2, C.sub.cl2 are connected to a second central busbar 38. The two busbars 36, 38 are constructed symmetrically with respect to one another and each comprise a metal sheet bent in a U-shaped manner. By the central part, the two busbars are connected to an electrically conductive cooling element 20 between the semiconductor switches S.sub.2 and S.sub.4.

(30) A lower, second snubber busbar 40 is connected to the diode D.sub.cl of the second converter 10. The capacitors C.sub.cl1, C.sub.cl2, C.sub.cl1, C.sub.c12 of the lower converter 10 are connected to said diode D.sub.cl via a busbar 40 and are arranged in a manner corresponding to the upper capacitors and are correspondingly connected to the central busbars 36, 38.

(31) In FIG. 7, four commutation loops can be discerned for each of the converters 10, 10.

(32) It should supplementarily be pointed out that comprising does not exclude other elements or steps and a(n) or one does not exclude a plurality. Furthermore it should be pointed out that features or steps that have been described with reference to one of the exemplary embodiments above can also be used in combination with other features or steps of other exemplary embodiments described above. Reference signs in the claims should not be regarded as a restriction.

LIST OF REFERENCE SIGNS

(33) 10, 10 Two-level converter 12, 12 Commutation loop S.sub.1, S.sub.2 Semiconductor switch C.sub.dc Cell capacitor L.sub.com, L.sub.s Leakage inductance C.sub.cl1, C.sub.cl2 Snubber capacitor D.sub.cl Snubber diode R.sub.s Snubber resistor L.sub.i Inductor inductance 14, 16 Terminal 18 Semiconductor stack 20 Cooling element 22 Frame 24 Auxiliary stack S.sub.3, S.sub.4 Semiconductor switch 26 Mechanical mounting clamp 28 Electrical connection 34 Upper, first snubber busbar 36, 38 Central snubber busbar 40 Lower, second snubber busbar