HIGH-VOLTAGE DIGITAL POWER AMPLIFIER WITH SINUSIOIDAL OUTPUT FOR RFID

Abstract

A Digital power amplifier (13) to drive an RFID antenna (10) with a substantial sinusoidal output current (I) which digital power amplifier (13) comprises: an integrated circuit (IC2) with a first transmission output pin (15) and a second transmission output pin (16) to provide an output signal (17); an adaption circuit (14) of discrete components (C2a, C2b) connected to the first and second transmission output pin (15, 16) to adapt the output signal (17) and feed the substantial sinusoidal output current (I) with a transmission resonance frequency to the RFID antenna (10), wherein the integrated circuit (IC2) comprises: a digital control section (19) with a number of N wave-forming contacts (20) to output a digital wave-forming bit combination of N bits with a clock frequency M-times the transmission resonance frequency; a number of N driver blocks (21) each connected with a first contact (22) to one of the wave-forming contacts (20) and a number of N/2 of them connected with a second contact to the first transmission output pin (15) and the other number of N/2 of them connected with their second contact to the second transmission output pin (16), which driver blocks (21) are built to provide increments of the substantial sinusoidal output current (I) to the first and second transmission output pin (15, 16).

Claims

1. Digital power amplifier (13) that uses digital wave-forming bit combinations to drive an RFID antenna (10) with a substantial sinusoidal output current (I) which digital power amplifier (13) comprises: an integrated circuit (IC2) with a first transmission output pin (15) and a second transmission output pin (16) to provide an output signal (17); an adaption circuit (14) of discrete components (C2a, C2b) connected to the first and second transmission output pin (15, 16) to adapt the output signal (17) and feed the substantial sinusoidal output current (I) with a transmission resonance frequency to the RFID antenna (10), characterized in that the integrated circuit (IC2) comprises: a digital control section (19) with a number of N wave-forming contacts (20) to output a digital wave-forming bit combination of N bits with a clock frequency M-times the transmission resonance frequency; a number of N driver blocks (21) each connected with a first contact (22) only to one of the wave-forming contacts (20) and a number of N/2 of them connected with a second contact only to the first transmission output pin (15) and the other number of N/2 of them connected with their second contact only to the second transmission output pin (16), which driver blocks (21) are built to provide increments of the substantial sinusoidal output current (I) to the first and second transmission output pin (15, 16) and wherein each of the N/2 driver blocks (21) connected to the first transmission output pin (15) is built identical and each of the other N/2 driver blocks (21) connected to the second transmission output pin (16) is built identical.

2. Digital power amplifier (13) according to claim 1, wherein each driver block (21) comprises a level shifter (LS) connected to the first contact (22) of the driver block (21) to shift the voltage provided at the wave-forming contact (20) to a higher voltage.

3. Digital power amplifier (13) according to claim 2, wherein each of the driver blocks (21) connected to the first transmission output pin (15) or each of the driver blocks (21) connected to the second transmission output pin (16) comprise an inverter (27) to invert the potential of the voltage provided by the level shifter (LS).

4. Digital power amplifier (13) according to claim 3, wherein each driver block (21) comprises a series capacitor (C) arranged between the inverter (27, 28) and the second contact (23, 24) of the driver block (21) and fed with the voltage/inverted voltage of the level shifter (LS).

5. Digital power amplifier (13) according to claim 4, wherein the integrated circuit (IC2) is realized in CMOS technology and wherein the series capacitors (C) are realized by Metal-Oxide-Metal capacitors that use the capacitive effect of the connecting lines within the integrated circuit (IC2).

6. Digital power amplifier (13) according to any of the claims 1 to 5, wherein the adaption circuit (14) comprises two resonance capacitors (C2a, C2b) each connected with their first contact to the first transmission output pin (15)/second transmission output pin (16) and both connected with their second contacts to a ground pin (18) of the integrated circuit (IC2).

7. Digital power amplifier (13) according to any of the claims 1 to 6, wherein the transmission resonance frequency of the RFID antenna (10) is 13.56 MHz and the clock frequency is a multiple of the transmission resonance frequency and in particular 8-, 16-, 32- or 64-times the transmission resonance frequency.

8. Digital power amplifier (13) according to any of the claims 1 to 7, wherein the digital control section (19) stores a table with a number of M digital wave-forming bit combinations for each of the data bits 0 and 1 and wherein the digital control section (19) is built to output the M digital wave-forming bit combinations of either data bit 0 or 1 at the N wave-forming contacts (20) to transform data bit 0 or 1 into the substantial sinusoidal output current (I).

9. Integrated circuit (IC2) for a digital power amplifier (13), characterized in, that the integrated circuit (IC2) comprises the elements as claimed in claims 1 to 8.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1 shows a high-voltage digital power amplifier of a reader according to the state of the art.

[0015] FIG. 2 shows a high-voltage digital power amplifier of a reader or tag according to the invention.

[0016] FIG. 3 shows part of the integrated circuit of the digital power amplifier according to FIG. 2.

[0017] FIG. 4 shows an example of the substantial sinusoidal output voltage U over half a period of the transmission resonance frequency at the RFID antenna according to FIG. 2.

[0018] FIG. 5 shows an example of different amplitudes of the substantial sinusoidal output voltage U over half a period of the transmission resonance frequency at RFID antenna generated with different wave-forming bit combinations in the digital power amplifier according to FIG. 2.

DETAILED DESCRIPTION OF EMBODIMENTS

[0019] FIG. 2 shows the transmission part of a high-voltage digital power amplifier 13 within a reader or tag that comprises an integrated circuit IC2 that processes digital data to be transmitted to a reader or tag. An adaption circuit 14 of discrete components connected to a first transmission output pin 15 and a second transmission output pin 16 is built to adapt output signal 17 of the integrated circuit IC2 and feed a substantial sinusoidal output current I with a transmission resonance frequency to RFID antenna 10. The adaptation circuit 14 comprises a first resonance capacitor C2a connected with its first contact to the first transmission output pin 15 and a second resonance capacitor C2b connected with its first contact to the second transmission output pin 16 and both resonance capacitors C2a and C2b are connected with their second contacts to a ground pin 18 of the integrated circuit IC2. The resonance capacitors C2a and C2b are tuned to build a resonance system together with the output impedance of the integrated circuit IC2 at the first and second transmission output pins 15 and 16 and the impedance of the parallel connected Ohmic resistance 9 and RFID antenna 10 to resonate at the transmission resonance frequency of 13.56 MHz. This transmission resonance frequency of 13.56 MHz is defined in standard ISO/IEC 14.443 to transmit and receive data over the magnetic field HF.

[0020] FIG. 3 shows part of the integrated circuit IC2 of the digital power amplifier 13 according to FIG. 2. Integrated circuit IC2 comprises a digital control section 19 with a number of N wave-forming contacts 20 to output a digital wave-forming bit combination of N bits which changes with a clock frequency that is M-times the transmission resonance frequency. The clock frequency in this embodiment with M=64 is 64*13.56 MHz=867.84 MHz. The number N defines the resolution or number of different amplitudes and the number M defines the resolution or split of one period of the substantial sinusoidal output current with its transmission resonance frequency of 13.56 MHz with which the digital power amplifier 13 drives the RFID antenna 10. In principle the higher the numbers N and M the better and smoother the form of the sinus SIN of the substantial sinusoidal output current I and substantial sinusoidal output voltage U. In the embodiment disclosed N=64 and M=64, but any other numbers may be used as well. M=64 provides a phase resolution of 360/64 degrees, about 6 degrees.

[0021] FIG. 4 shows an example of the substantial sinusoidal output voltage U with maximal amplitude possible over half a period of the transmission resonance frequency at the RFID antenna 10 generated by the power amplifier 13 according to FIG. 2 in comparison with a perfect sinus SIN. Such resonant output voltage U may be in the 100 Voltage peak-to-peak range or even more. FIG. 5 shows the different amplitudes of the substantial sinusoidal output voltage U over half a period of the transmission resonance frequency at the RFID antenna 10 that may be generated by the power amplifier 13 according to FIG. 2 depending on the content of the M/2 digital wave-forming bit combinations of the N bits provided at the N wave-forming contacts 20 with the clock frequency of the integrated circuit IC2.

[0022] Digital control section 19 stores a table with a number of M digital wave-forming bit combinations for each of the data bits 0 and 1 and digital control section 19 is built to output the M digital wave-forming bit combinations of either data bit 0 or 1 at the N wave-forming contacts 20 to transform data bit 0 or 1 into the substantial sinusoidal output current I.

[0023] Each of the N driver blocks 21 is connected with a first contact 22 to one of the wave-forming contacts 20. N/2 of the driver blocks 21 are connected with a second contact 23 to the first transmission output pin 15 and the other N/2 of the driver blocks 21 are connected with their second contact 24 to the second transmission output pin 16, which driver blocks 21 are built to provide increments of the substantial sinusoidal output current I to the first and second transmission output pins 15 and 16. This means that each of the driver blocks 21, if driven with a bit 1 in the digital wave-forming bit combination, adds an increment of for instance 5 mA for one clock period to the transmission output pin 15 or 16. All these increments add up to form the substantial sinusoidal output current I with for instance maximal N*5 mA=320 mA. Higher or lower increments would be possible as well.

[0024] This design of integrated circuit IC2 comprises the advantage that the output signal 17 at the first and second transmission output pins 15 and 16 is already an analogue signal with a signal form close to a perfect sinus SIN to satisfy the spurious emission levels required by regulations to avoid noise in other frequency ranges. Therefore no external filter means are needed in the adaption means 14, compared to state of the art integrated circuit IC1. All discrete components in block 25 of integrated circuit IC1 are not needed in adaption means 14 of integrated circuit IC2. This saves printed circuit board space. Furthermore the RFID antenna 10 may be directly connected to the first and second transmission output pins 15 and 16. In addition it is advantageous that the waveform of the substantial sinusoidal output current I and voltage U may be digitally programmed to achieve accurate output power modulation.

[0025] Each driver block 21 comprises a level shifter LS connected to the first contact 22 of the driver block 21 to shift the voltage provided at the wave-forming contacts 20 to a higher and in particular to an at least a two times higher voltage. In the embodiment disclosed the level shifters LS receive an input signal in the range of 0 Volt to 1.8 Volt at their first contact 22 and shift it into an output signal in the range of 0 Volt to 5 Volt at their second contact 26. Level shifters LS therefore transform from the low-voltage domain VD_PAdig of the digital control section 19 into the high voltage analog domain VD_PA the driver blocks 21 are supplied with.

[0026] Each of the driver blocks 21 is either connected with its second contact 23 to the first transmission output pin 15 or with its second contact 24 to the second transmission output pin 16. Those driver blocks 21 connected to the second transmission output pin 16 comprise an inverter 27 to invert the potential of the voltage provided by the level shifter LS. This enables to generate the negative half of the substantial sinusoidal output current I and output voltage U. Those driver blocks 21 connected to the first transmission output pin 15 comprise a buffer 28 to have similar influence on the output signal of the level shifter LS, but do not invert the potential of the voltage provided by the level shifter LS.

[0027] Each driver block 21 furthermore comprises a series capacitor C arranged either between the inverter 27 and the second contact 24 or between the buffer 28 and the second contact 23 of the driver block and fed with the voltage/inverted voltage of the level shifter LS. This enables that the current increments of each of the driver blocks 21 add up to a positive and a negative half wave of the substantial sinusoidal output current I. Typical capacity of capacitors C would be 10 pF each what sums up to 500 pF for the driver blocks 21 connected to the first transmission output pin 15 and what sums up to 500 pF for the driver blocks 21 connected the second transmission output pin 16. But each single capacitor C could have a lower capacity like 5 pF or 1 pF or a higher capacity like 20 pF or 50 pF than the example of 10 pF as well.

[0028] Integrated circuit IC2 is realized in CMOS technology and advantageously the series capacitors C are realized by Metal-Oxide-Metal capacitors that use the capacitive effect of the connecting lines within integrated circuit IC2. This enables a good integration of the series capacitors C within integrated circuit IC2 and allows high output voltage.

[0029] All driver blocks 21 are always conducting, even when no digital wave-forming bits are output at wave-forming contacts 20. This enables that resonance tuning is preserved and overvoltage on the driver blocks 21 is prevented. The number of driver blocks 21 used in combination with the pulse width of the digital wave forming bits defines the output power of the power amplifier 13.

[0030] In another embodiment series capacitors C could be realized outside of the integrated circuit within the adaptation means. Other transmission resonance frequencies may be realized as well.

[0031] A major advantage of the inventive high-power digital power amplifier is that it may be integrated in a tag or transponder as well as in a reader. This is only possible as the space needed on the printed circuit board is small.

[0032] The digital power amplifier as described above realizes a method to generate increments of current pulses to add them up into a substantial sinusoidal output current.

[0033] The digital power amplifier as described above is built to generate increments of current pulses to add them up into a substantial sinusoidal output current. A man skilled in the art will understand that this principle may be used as well to generate increments of voltage pulses with the length of one clock period to add them up into a substantial sinusoidal output voltage.