Method and apparatus for controlling a battery pack

Abstract

A method of controlling a battery including a first control circuit and a plurality of modules arranged in series between first and second terminals, each module including electric cells and switches and a second switch control circuit, the battery further including at least one first data transmission bus coupling the first control circuit to each second control circuit, the method including the transmission, by the first control circuit to the second control circuits, of first data representative of an electric cell configuration to be obtained to follow a set point for the delivery of a voltage and/or of a current between the first and second terminals, the second control circuits connecting or disconnecting the electric cells based on said first data and on a classification of the priorities of the electric cells.

Claims

1. A method of controlling an electric system comprising a first control circuit and a plurality of modules arranged in series between first and second terminals, each module comprising third and fourth terminals, at least one of the third and fourth terminals of each module being coupled to one of the third and fourth terminals of another module, each module comprising electric cells and switches coupling the cells to one another and to the third and fourth terminals of the module and a second switch control circuit, the electric system further comprising at least one first data transmission bus coupling the first control circuit to each second control circuit, the method comprising the transmission, by the first control circuit to the second control circuits, of first data representative of an electric cell configuration to be obtained to follow a set point for the delivery of a voltage or of a current between the first and second terminals, the second control circuits connecting or disconnecting the electric cells based on said first data and on a classification of the priorities of the electric cells, wherein the method further comprises the steps of: a) determination by the first control circuit of a new version of the priority classification; b) transmission, by the first control circuit to each second control circuit, of second data representative of at least a portion of the new version of the priority classification; c) transmission, by each second control circuit to the first control circuit, of third data indicating the reception by the second control circuit of said at least a portion of the new version of the priority classification; and d) transmission, by the first control circuit to the second control circuits, of an order to use the new version of the priority classification.

2. The control method according to claim 1, wherein the electric system further comprises a second data transmission bus coupling the first control circuit- to each second control circuit, wherein the first control circuit transmits the first data to the second control circuits over the first bus and transmits the second data to the second control circuits over the second bus.

3. The control method according to claim 2, wherein the second control circuits transmit the third data to the first control circuit over the second bus.

4. The control method according to claim 2, wherein the first control circuit transmits the order to use the new version of the priority classification to the second control circuits over the first bus.

5. The control method according to claim 2, wherein the first control circuit transmits the first data to the second control circuits over the first bus at a first rate and transmits the second data to the second control circuits over the second bus at a second rate smaller than the first rate.

6. The control method according to claim 1, wherein the first data are representative of the number of cells to be series-connected to follow the set point.

7. The control method according to claim 1, wherein the second data are representative of the entire priority classification.

8. The control method according to claim 1, wherein the second data are representative of the portion of the classification of the priorities of the electric cells of one of the modules.

9. The method of claim 1, wherein the first data are representative of an electric cell configuration to be obtained to follow a set point for the delivery of a voltage and of a current between the first and second terminals.

10. An electric system comprising a first control circuit and a plurality of modules arranged in series between first and second terminals, each module comprising third and fourth terminals, at least one of the third and fourth terminals of each module being coupled to one of the third and fourth terminals of another module, each module comprising electric cells and switches coupling the cells to one another and to the third and fourth terminals of the module and a second switch control circuit, the electric system further comprising a first data transmission bus coupling the first control circuit to each second control circuit and a second data transmission bus coupling the first control circuit to each second control circuit, wherein the first control circuit is configured to transmit, to the second control circuits, first data representative of an electric cell configuration to be obtained to follow a set point for the delivery of a voltage and/or or of a current between the first and second terminals, the second control circuits being configured to connect or disconnect the electric cells based on said first data and on an electric cell priority classification, wherein the first control circuit is configured to determine a new version of the priority classification and to transmit to each second control circuit second data representative of at least a portion of the new version of the priority classification, wherein each second control circuit is configured to transmit to the first control circuit third data indicating the reception by the second control circuit of said at least a portion of the new version of the priority classification, and wherein the first control circuit is configured to transmit to the second control circuits an order to use the new version of the priority classification.

11. The electric system of claim 10, wherein the first data are representative of an electric cell configuration to be obtained to follow a set point for the delivery of a voltage and of a current between the first and second terminals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

(2) FIG. 1, previously described, partially and schematically shows an example of a cell battery;

(3) FIG. 2 partially and schematically shows an embodiment of a cell battery;

(4) FIG. 3 partially and schematically shows an example of a module of the battery of FIG. 1 or 2;

(5) FIG. 4 is a timing diagram illustrating data exchanged between the master control circuit and the slave control circuits of the battery shown in FIG. 2 for an embodiment of a method of controlling the battery; and

(6) FIG. 5 is a timing diagram illustrating the data exchanged between the master control circuit and the slave control circuits of the battery shown in FIG. 1 for an embodiment of a method of controlling the battery.

DETAILED DESCRIPTION

(7) Like features have been designated by like references in the various figures. For the sake of clarity, only the elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail. In particular, the conventional functions carried out by the master and slave control circuits of a cell battery, such as the cell balancing, are well known by those skilled in the art and are not described in further detail hereafter. In the following description, the expressions “substantially”, “about”, “approximately”, and “in the order of” mean “within 10%”, preferably within 5%.

(8) An embodiment of a method of controlling systems with switched cells will be described in the case of a switched cell battery for which the cells correspond to switched cells. However, the present embodiments apply to any type of system with switched cells capable of supplying a variable voltage to a load. Each cell of the system with switched cells may correspond to an electric charge storage element or to an electric generator. An example of an electric charge storage element for example is an electric cell or a capacitor. An example of an electric generator is for example a fuel cell, a zinc-air cell, a photovoltaic cell, or a power recovery system, particularly a small wind power plant or a mini-turbine. The system which switched cells may comprise electric charge storage elements only, electric generators only, or both electric charge storage elements and electric generators. When the system with switched cells comprises electric generators only, the use is theoretically in discharge mode only. However, in case of a reactive power, for brief passages through a negative power at each period, the inertia of the generator may be sufficient to smooth the power, for example, due to the rotation inertia and to the stray capacitances. Further, each generator may be connected in parallel to a resistive element, to accept negative powers, by dissipating this power. In operation, the system is intended to be coupled to a device which absorbs or supplies power according to the envisaged application. As an example, this device corresponds to an electric machine, for example, to an electric motor, or to the electric distribution network.

(9) FIG. 2 shows an embodiment of a battery 10. Battery 10 comprises all the elements of the battery 5 shown in FIG. 1, with the difference that bus BUS is replaced with two buses BUS0 and BUS1, which each couple master control circuit BMS to each module E.sub.1 to E.sub.N.

(10) Bus BUS0 is a fast bus, that is, a bus over which the data are transmitted at a rate greater than 3 megabits per second, preferably in the range from 5 megabits per second to 7 megabits per second. Bus BUS0 may be a unidirectional bus. As an example, bus BUS0 is a bus according to the RS485 standard.

(11) Bus BUS1 is a slow bus, that is, a bus over which the data are transmitted at a rate smaller than 3 megabits per second, preferably in the range from 0.5 megabit per second to 1 megabit per second. Bus BUS1 is a bidirectional bus. As an example, bus BUS1 is a CAN data bus, particularly according to ISO standard 11898.

(12) Fast bus BUS0 is used for the transmission of the first data supplied by master control circuit BMS to follow set point C. According to another embodiment, the first data correspond to a number of cells to be connected to follow set point C.

(13) Slow bus BUS1 is used for the exchange of all the other data between master control circuit BMS and each module E.sub.1 to E.sub.N. In particular, slow bus BUS1 is used for the transmission of the second data relative of the updates of the priority table.

(14) Master control circuit BMS may correspond to a dedicated circuit and/or may comprise a processor, for example, a microprocessor or a microcontroller, capable of executing instructions of a computer program stored in the memory. Master control circuit BMS particularly comprises a data storage memory MEM.

(15) FIG. 3 shows an embodiment of module E.sub.i, where i varies from 1 to N, each module E.sub.1 to E.sub.N may have a similar structure.

(16) According to the present embodiment, module E.sub.i is capable of delivering a voltage U between positive terminal B+ and negative terminal B−. Module E.sub.i comprises cells C.sub.1 to C.sub.M, where M is an integer in the range from 2 to 10, preferably from 2 to 5, four cells C.sub.1, C.sub.2, C.sub.3, and C.sub.4 being shown as an example in FIG. 3. Cells C.sub.1 to C.sub.M are coupled together and to terminals B+ and B− by switches. In the present embodiment, for each cell C.sub.k, k being an integer varying from 1 to M, module E.sub.i comprises a first switch SW.sub.1,k in series with cell C.sub.k and a second switch SW.sub.2,k in parallel with the assembly comprising cell C.sub.k and switch SW.sub.Lk. The M assemblies comprising cell C.sub.k and first switch SW.sub.Lk are arranged in series between a node A and a node B. The control of switches SW.sub.1,k and SW.sub.2,k, with k varying from 1 to M, enables to place in series between nodes A and B from 1 to M cells among the M cells C.sub.1 to C.sub.M. In the present embodiment, module E.sub.i further comprises an inverter bridge, also called H bridge, between nodes A and B and terminals B+ and B−, which enables to apply the voltage present between nodes A and B between terminals B+ and B− in both directions. According to an embodiment, the inverter bridge comprises a switch SW.sub.3 coupling node A to terminal B+, a switch SW.sub.4 coupling node A to terminal B−, a switch SW.sub.5 coupling node B to terminal B+, and a switch SW.sub.6 coupling node B to terminal B−. As an example, each switch SW.sub.Lk and SW.sub.2,k, with k varying from 1 to M, SW.sub.3, SW.sub.4, SW.sub.5, and SW.sub.6 may correspond to an insulated-gate field effect transistor, also called MOS transistor, particularly a MOS power transistor, for example, an N-channel MOS transistor.

(17) Each module E.sub.i further comprises slave control circuit 12 (μC), capable of exchanging and of receiving data transmitted by master control circuit BMS over bus BUS0 and of exchanging data with master control circuit BMS over bus BUS1. Slave control circuit 12 may correspond to a dedicated circuit and/or may comprise a processor, for example, a microprocessor or a microcontroller, capable of executing instructions of a computer program stored in the memory.

(18) Each module E.sub.i further comprises a driver circuit 14 (Inverter bridge driver) coupled to switches SW.sub.3, SW.sub.4, SW.sub.5, and SW.sub.6 of the inverter bridge and a driver circuit 16 (Transistors driver) coupled to switches SW.sub.Lk and SW.sub.2,k, with k varying from 1 to M. Each driver circuit 14, 16 is capable of converting the control signals delivered by slave control circuit 12 into signals capable of controlling the switches.

(19) Each module E.sub.i further comprises sensors 18 (U, I, T° sensor) coupled to slave control circuit 12. Module E.sub.i may comprise, for each cell C.sub.k, a temperature sensor capable of measuring the temperature of cell C.sub.k. Module E.sub.i may further comprise, for each cell C.sub.k, a voltage sensor capable of measuring the voltage across cell C.sub.k. Module E.sub.i may further comprise, for each cell C.sub.k, a current sensor capable of measuring the current delivered by cell C.sub.k. The slave control circuit 12 of each module E.sub.i is capable of transmitting third data to master control circuit BMS over slow bus BUS1 representative of the measurements performed by the sensors 18 of module E.sub.i. The number and the type of sensors particularly depend on the arrangement of the cells of module E.sub.i. In the cell arrangement shown in FIG. 3, a single sensor of the current flowing at node A or at node B may be provided.

(20) In the embodiment illustrated in FIG. 3, an order of connection of a cell C.sub.k of a module E.sub.i means that cell C.sub.k should be series-connected between the nodes A and B of module E.sub.i, which is obtained by turning on switch SW.sub.1,k and by turning off switch SW.sub.2,k, and an order of disconnection of a cell C.sub.k of a module E.sub.i means that cell C.sub.k should not be series-connected between the nodes A and B of module E.sub.i, which is obtained by turning off switch SW.sub.1,k and by turning on SW.sub.2,k. However, for a different arrangement of the cells C.sub.k of module E.sub.i where cells C.sub.k may be arranged in series or in parallel between nodes A and B, an order of connection of cells C.sub.k should further specify in which configuration, series or parallel, cell C.sub.k is placed with respect to the other cells of module E.sub.i.

(21) Master control circuit BMS is capable of determining the cell priority table. According to an embodiment, the priority table is stored in memory MEM of master control circuit BMS in the form of a table, each row of the table for example corresponding to a row of memory MEM. For a battery comprising N cells, the priority table comprises N rows. The priority table may comprise a first column having identifiers of the battery cells stored therein. As an example, for a battery comprising N cells, the cell identifiers range from 1 to N. The priority table may comprise a second column having the priority levels of the cells stored therein. As an example, for a battery comprising N cells, the priority levels of the cells range from 1 to N, priority level “1” being the highest and priority level “N” being the lowest.

(22) Master control circuit BMS updates the priority table when the priority levels of the cells are modified. As an example, the priority levels of the cells may be modified by master control circuit BMS particularly based on the data measured by the cell sensors.

(23) Each slave control circuit 12 comprises a memory MEM′ for the storage of the priority table or of a portion of the priority table. According to an embodiment, master control circuit BMS sends to each slave control circuit 12 the entire priority table, which is stored in memory MEM′ of slave control circuit 12. According to another embodiment, control circuit BMS sends to each slave control circuit 12 the portion of the priority table relative to the cells controlled by slave control circuit 12. Each slave control circuit 12 then only keeps in memory MEM′ the portion of the priority table concerning it. In the rest of the disclosure, when it is spoken of a priority table stored by a slave control circuit 12, this may mean the entire priority table or the portion of the priority table relative to the cells controlled by slave control circuit 12 according to the implemented control method. For each module E.sub.i, the slave control circuit 12 of module E.sub.i determines, based on the number of cells requested by master control circuit BMS and on the priority levels of the cells forming it, the cells of module E.sub.i to be connected/disconnected to follow set point C. An advantage of such an embodiment is that the responsiveness of battery 10 on reception of a new set point C is optimal.

(24) FIG. 4 is a timing diagram illustrating the data exchanged between master control circuit BMS and the slave control circuits 12 of the battery 10 shown in FIG. 2 for an embodiment of a method of controlling battery 10.

(25) According to the present embodiment of the control method, the first data are transmitted by master control circuit BMS over fast bus BUS0. The first data may be representative of the total number of cells in series desired between terminals Phase and Neutral of battery 10 when modules E.sub.i have the configuration shown in FIG. 3. When the cells of each module can be placed in series and/or in parallel, the first data may be representative of the desired cell configuration. The first data may be transmitted over fast bus BUS0 in the form of frames T.sub.1, for example regularly transmitted.

(26) According to an embodiment of the data transmission method, each frame T.sub.1 transmitted by master control circuit BMS is sent to all modules E.sub.i, with i varying from 1 to N. The slave control circuit 12 of each module E.sub.i is thus used for each frame sent by master control circuit BMS over fast bus BUS0. The slave control circuit of each module E.sub.i is capable of analyzing frame T.sub.1 to extract therefrom the desired cell configuration to follow set point C, for example, the number of cells to be series-connected.

(27) According to the present embodiment of the control method, the second data transmitted by master control circuit BMS to slave control circuits 12 over slow bus BUS1 may be representative of the priority table or of a portion of the priority table when the latter is updated. In particular, an update of the priority table may be transmitted by master control circuit BMS to slave control circuits 12 for each modification of the priority table determined by master control circuit BMS. FIG. 4 shows frames T.sub.2 transmitted by master control circuit BMS to slave control circuits 12 over slow bus BUS1 and comprising data representative of the last version of the data table. As an example, in the case where only the portion of the priority table relative to the cells contained by module E.sub.i is transmitted to each module E.sub.i, the second data may be transmitted in the form of frames T.sub.2, each frame T.sub.2 comprising a header containing the address of the designated module E.sub.i followed by bytes relative to the portion of the priority table relative to module E.sub.i, and possible followed by at least one control byte. The slave control circuit 12 of each module E.sub.i is then capable of determining whether the control signal that it receives is addressed thereto. According to another example, each frame is sent to all modules E.sub.i. The slave control circuit 12 of each module E.sub.i is then used for each frame T.sub.2 sent by master control circuit BMS over slow bus BUS1.

(28) Master control circuit BMS associates a number with each version of the priority table. As an example, when master control circuit BMS updates the priority table, it modifies the version number associated with the new priority table. According to an embodiment, each frame T.sub.2 comprising data relative to a priority table further comprises a version number of the priority table.

(29) Each slave control circuit 12 is capable of regularly transmitting to master control circuit BMS the number of the most recent version in the priority table which is stored in memory MEM′. FIG. 4 represents with black frames T.sub.3 the data transmitted by slave control circuits 12 to master control circuit BMS over slow bus BUS1 and comprising the numbers of the last versions of the priority tables stored by the slave control circuits.

(30) In normal operation, in the absence of an update of the priority table, each slave control circuit 12 has stored in memory MEM′ a priority table which is used to determine the cells to be connected/disconnected. When master control circuit BMS updates the priority table, it transmits the priority table updated with the new version number to slave control circuits 12. Each slave control circuit 12 stores the new priority table while keeping in memory the previous version of the priority table. For each module E.sub.i, when the slave control circuit 12 of module E.sub.i has stored the new priority table, it transmits a frame T.sub.3 to master control circuit BMS, containing the number of the new version of the priority table as well as the identifier of module E.sub.i. However, slave control circuit 12 keeps on processing the first data received over fast bus BUS0 with the previous version of the priority table. Slave control circuit 12 then has in memory the previous version of the priority table and the new version of the priority table.

(31) Master control circuit BMS determines which slave control circuit 12 has received the new version of the priority table based on the received frames T.sub.3. At time t.sub.0, master control circuit BMS has received an acknowledgement of receipt of the new version of the priority table of each slave control circuit 12. At time t.sub.1, master control circuit BMS orders the slave control circuits 12 to now use the new version of the priority table. According to an embodiment where master control circuit BMS sends a frame T.sub.2 to all slave control circuits 12, master control circuit BMS may set to “1” a specific bit of frame T.sub.2, which indicates to each slave control circuit 12 that the new version of the priority table should be used.

(32) FIG. 5 is a timing diagram illustrating the data exchanged between master control circuit BMS and the slave control circuits 12 of the battery 5 shown in FIG. 1 for an embodiment of a method of controlling battery 5.

(33) In the present embodiment, the first data and the second data are transmitted over bus BUS. According to an embodiment, the frames T.sub.1 relative to the first data are transmitted as a priority over the frames relative to the second data T.sub.2 and over the frames T.sub.3 relative to the versions of priority tables used by modules E.sub.i. The rest of the method is identical to what has been previously described in relation with FIG. 4. In particular, at time t.sub.0, master control circuit BMS has received an acknowledgement of receipt for the new version of the priority table of each slave control circuit 12 and, at time t.sub.1, master control circuit BMS orders the slave control circuits 12 to now use the new version of the priority table.

(34) Specific embodiments of the present invention have been described. Various alterations and modifications will occur to those skilled in the art. Although FIG. 3 shows an embodiment of arrangement of the cells and of the switches of a module E.sub.i, it should be clear that the structure of each module E.sub.i may be different. In particular, the structure of each module E.sub.i may correspond to one of the structures described in patent application WO 2012/117110.