High energy density capacitor system and method

Abstract

A capacitor includes a first metal layer disposed on a wafer or substrate, a first polarized dielectric layer above the first metal layer and comprising a plurality of electrets formed by aligning molecular dipoles throughout a three-dimensional surface area of a polarizable dielectric material during polarization by applying a momentary electric field of positive or negative polarity, a second metal layer disposed on the first polarized dielectric layer to electrically isolate the first polarized dielectric layer, and a second polarized dielectric layer above the second metal layer, the second polarized dielectric layer comprising a plurality of electrets formed by aligning molecular dipoles throughout a three-dimensional surface area of a polarizable dielectric material during polarization by applying a second momentary electric field of opposing polarity. A plurality of alternating polarized dielectric layers and metal layers may be arranged in series to form a stack, with an internal passivation layer disposed between each stack.

Claims

1. A capacitor, comprising: a wafer or substrate; a first metal layer disposed on the wafer or substrate; a first polarized dielectric layer above the first metal layer, the first polarized dielectric layer comprising a plurality of electrets formed by aligning molecular dipoles throughout a three-dimensional surface area of polarizable dielectric material during polarization by applying a momentary electric field of positive or negative polarity to the polarizable dielectric material; a second metal layer disposed on the first polarized dielectric layer to electrically isolate the first polarized dielectric layer; and a second polarized dielectric layer above the second metal layer, the second polarized dielectric layer comprising one or more electrets formed by aligning molecular dipoles throughout a three-dimensional surface area of polarizable dielectric material during polarization by applying a second momentary electric field of opposing polarity to the polarizable dielectric material.

2. The capacitor of claim 1 wherein the polarizable dielectric material comprises a high K dielectric material.

3. The capacitor of claim 2 wherein each layer of polarizable dielectric material is comprised of high K material in the K>1000 range.

4. The capacitor of claim 1 wherein the first and second momentary electric fields are applied using capacitive plates disposed above and below the wafer or substrate and applying a designated voltage.

5. The capacitor of claim 4 wherein the designated voltage is about 1500 volts DC or greater.

6. The capacitor of claim 1 further comprising: a plurality of alternating polarized dielectric layers and metal layers arranged in series to form a stack; and at least one internal passivation layer disposed between each stack.

7. The capacitor of claim 1 wherein the first and second polarized dielectric layers are arranged in parallel.

8. The capacitor of claim 1 wherein the first and second polarized dielectric layers are arranged in series.

9. The capacitor of claim 1 wherein each polarized dielectric material has a dielectric constant in the range of about 10.sup.9 to about 10.sup.12 after application of said momentary electric fields.

10. The capacitor of claim 1 wherein polarity of the first and second momentary electric fields is selected dependent upon whether the first and second layers of polarizable dielectric material are arranged in parallel or in series, and further dependent upon direction the first or second layer needed to be polarized.

11. The capacitor of claim 1 further comprising sequential layers of polarizable dielectric material deposited using semiconductor fabrication techniques.

12. The capacitor of claim 11 wherein the sequential layers of polarizable dielectric material are deposited using atomic layer deposition.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The figures are for illustration purposes only and are not drawn to scale. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:

(2) FIG. 1 depicts a wafer or panel with layers of metal and dielectric layers, in accordance with disclosed embodiments of the present invention.

(3) FIG. 2 depicts the capacitors of the present invention in serial parallel arrays, in accordance with disclosed embodiments.

(4) FIG. 3 depicts the capacitors of the present invention having an alternating anode and cathode pole arrangement around the edge of the device in order to get the charge in and out quickly with minimal effective series resistance (ESR).

(5) FIG. 4 depicts the dielectric surface area of a capacitor in accordance with embodiments of the present invention, wherein surface area “A” is a three dimensional (3D) surface area, as opposed to two dimensional (2D).

(6) FIG. 5 depicts the capacitor layer anatomy of a capacitor in accordance with disclosed embodiments of the present invention.

(7) FIG. 6 depicts a deposition chamber used in an exemplary process for forming a capacitor in accordance with embodiments of the present invention.

(8) FIG. 7 depicts a deposition chamber used in a second exemplary process for forming a capacitor in accordance with embodiments of the present invention.

DESCRIPTION OF THE EMBODIMENT(S)

(9) In describing the embodiments of the present invention, reference will be made herein to FIGS. 1-7 of the drawings in which like numerals refer to like features of the invention.

(10) The high energy density capacitor of the present invention provides a solution for replacing slow charging, short-life batteries with quick charging, long-life capacitors. The method of forming the capacitor(s) of the present invention utilizes atomic layer deposition (ALD), metal oxide chemical vapor deposition (MOCVD), Electrospray, Sputtering, 3D printing and other semiconducting fabrication equipment to produce sub-micron thin layers and the capability for at least twelve (12) inch wafers and/or rectangular substrates, like those used for LED panels, which are available in a wide variety of generations and sizes. Wafers may also be sawed into any shape or size and stacked to any height.

(11) The instant invention takes advantage of these advances by utilizing a large array of ALD machines and other standard semiconducting fabrication machinery, 3D printing and robotic automation to apply up to thousands of layers per day to mass produce the capacitors in any shape or size.

(12) The primary advantage that batteries currently have over prior art capacitors is energy density. The capacitor of the present invention eliminates this barrier.

(13) Certain terminology is used herein for convenience only and is not to be taken as a limitation of the invention. For example, words such as “upper,” “lower,” “left,” “right,” “horizontal,” “vertical,” “upward,” and “downward” merely describe the configuration shown in the drawings. For purposes of clarity, the same reference numbers may be used in the drawings to identify similar elements.

(14) Additionally, in the subject description, the word “exemplary” is used to mean serving as an example, instance or illustration. Any aspect or design described herein as “exemplary” is not necessarily intended to be construed as preferred or advantageous over other aspects or design. Rather, the use of the word “exemplary” is merely intended to present concepts in a concrete fashion.

(15) Referring now to FIG. 1, an exemplary high energy density capacitor of the present invention is shown. The capacitor includes a wafer or substrate upon which is deposited alternating layers of metal and dielectric layers, and further includes a positive electrode 100, a negative electrode 101, and a “stack” of five (5) capacitors 102, which makes a 25 volt stack at one-fifth (⅕.sup.th) the capacitance of a single instantiation, since the five are in series. It should be understood by those skilled in the art that a “stack” of five capacitors is being shown for exemplary purposes only, and that any number of capacitors may be implemented, in series, in order to achieve the desired voltage per design requirements, as will be described below. A passivation layer 103 or insulator isolates the “stacks” 102. A metal layer 104, an ultra-dielectric material (UDM) layer 105, and the substrate or wafer 106 complete the assembly, in accordance with disclosed embodiments of the present invention.

(16) FIG. 2 depicts how a plurality of capacitors are organized in serial parallel arrays, in accordance with disclosed embodiments. Capacitor 201 is a single capacitor formed with UDM and metal layers. Stack 202 depicts a stack of five (5) capacitors in series. Putting capacitors in series lowers the capacitance, but it is necessary to increase the voltage. By way of example herein, each capacitor 201 is rated at 5 volts, therefore the stack 202 is rated up to 25 volts, albeit at one-fifth (⅕.sup.th) the capacitance of a single capacitor. The total capacitance is increased by arranging an array of stacks in parallel, because capacitors in parallel sum. Up to n stacks 203 may be created until the desired level of energy storage is achieved.

(17) Capacitance is defined as:
C=(kε.sub.0A)/d
where:

(18) C=Capacitance (Farads)

(19) k=Dielectric multiplier

(20) ε.sub.0=permittivity constant

(21) A=Area of the plates (m.sup.2)

(22) d=distance between plates (μm)

(23) The present invention produces a high capacitance EDLC-type electrochemical capacitor by substantially increasing the dielectric constant “k”, while shrinking the distance between the plates.

(24) Referring now to FIG. 3, the capacitors' alternating anode 300 and cathode 301 pole arrangement around the edge of the capacitor device is shown. Alternating poles in such a way allows the charge in and out quickly with minimal effective series resistance (ESR). In larger capacitors, additional positive and negative electrodes may be dispersed intermittently in the interior of the capacitor device, and may be arranged around the center of the device. As shown in the side view of FIG. 3, the electrodes extend along the full height of the capacitor array, even though these poles only attach to the metal layers periodically. In one embodiment, the electrodes 301 are attached to every fifth layer (as depicted in FIG. 1), in order to achieve 25 volt stacks. The unconnected layers may be masked to create a gap between the metal layers 501 and the electrodes 300, 301.

(25) FIG. 4 depicts the dielectric surface area of an embodiment of a capacitor of the present invention. Of particular note is that surface area “A” is a three dimensional (3D) surface area, not 2D. The atomic layer of conducting atoms snuggle in around the dielectric atoms, forming a three dimensional structure which yields a much higher surface area than just the 2D. It's the 3D surface area which in this case is the surface area for a bunch of half spheres, i.e. ½*(4πr.sup.2) multiplied by the number of atoms or molecules in the length by width area.

(26) FIG. 5 depicts the capacitor layer anatomy of one embodiment of the capacitor of the present invention, comprising anode and cathode metal layers 501, with layers of high surface area dielectric material (such as silica) and positive and negative atomic layers disposed therebetween. FIG. 5 illustrates how the dipoles 502 in the dielectric layer 500 align with the electric field 503 of the capacitor, but in the opposite direction, which leads to a reduction in the total field, and an increase in the total quantity of charge that the capacitor can hold for a given voltage/applied field. As a result, more charge can build up on the positive and negative electrodes 501. The “k” in physics is determined by the degree of polarization that the dielectric layers 500 can undergo, in other words, how many dipoles 502 are available inside the “N”-type and “P”-type atomic layers to reduce the applied field across the capacitor, thereby allowing more charge to be stored on the plates.

(27) The metal atoms with their conduction band and free electrons snuggle in around the hemispherical surfaces of the top of the dielectric layer (FIG. 4). Using pairs of high voltage plates to align the dipoles, as will be described in more detail below, the dielectric layers become “electrets,” equivalent to magnets; however, instead of aligning magnetic domains, the high energy density capacitor of the present invention comprises aligning electric dipole domains.

(28) The present invention optimizes energy density by maximizing the operating voltage. Some polar organic solvents have breakdown voltages three (3) to four (4) times higher than distilled water, and some are in the 5V range at micron thicknesses. By contrast, distilled water breakdown voltage limits the operating voltage to 0.8 to 1.2 volts per cell. The present invention also encompasses replacing the polar protic solvents with electric dipole materials, electrets, that are deposited and aligned to oppose the main electric field created when the capacitor is charging.

(29) One advantage of the present invention is that each capacitor may have a thickness of much less than 1 micron (μm) to optimize energy density while increasing capacitance.

(30) The ultra-dielectric materials (UDM) utilized in one embodiment comprise a combination of a polar organic solvent from Table 1 below, an electrolyte from Table 2 below, and a high surface area dielectric material from Table 3 below. In an embodiment, polar protic solvents are used for their high dielectric constants and high dipole moments. In other embodiments, polar aprotic solvents work well also, e.g., DMSO, KCl, and SiO.sub.2 or DMSO, NaCl, and SiO.sub.2, and therefore it should be understood by those skilled in the art that the present invention encompasses such alternative compositions which include a polar aprotic solvent in place of a polar protic solvent.

(31) TABLE-US-00001 TABLE 1 Polar Protic/Aprotic Solvents Protic Break or Dielectric Dipole Down Polar Solvents Apriotic Constant Moment Volts.sup.1 Ammonia protic 25 1.40 D t-Butanol protic 12 1.70 D t-Propanol protic 20 1.68 D Ethanol protic 25 1.69 D Methanol protic 33 1.70 D Acetic Acid protic 6.2 1.74 D Water protic 80 1.85 D .8-1.2 Acetone aprotic 25 1.40 D Dimethylformamide (DMF) aprotic 12 1.70 D Acetontrile (MeCN) aprotic 20 1.68 D Dimethyl Sulfoxide (DMSO) aprotic 25 1.68 D Dichloromethane aprotic 9.1 1.50 D Tetrahydrofuran (THF) aprotic 7.5 1.75 D Ethyl Acetate aprotic 6 1.78 D

(32) TABLE-US-00002 TABLE 2 Electrolyte Materials NaCL NH.sub.4CL KCI

(33) TABLE-US-00003 TABLE 3 High Surface Area Dielectric materials High Surface Area Dielectric Materials In situ k Pyrogenic Silica (Fumed Silica) 10.sup.10 to 10.sup.11 Silicon Dioxide (SiO.sub.2) ~10.sup.10 Alumina 10.sup.9 to 10.sup.10

(34) In one exemplary embodiment, ammonia (NH.sub.3) is used as the polar protic solvent, NH.sub.4CL is the electrolyte, and silicon dioxide is the high surface area dielectric material.

(35) In an embodiment, these materials are each deposited in sequential layers onto the wafer or substrate to build up a half micron (0.5 μm) layer of UDM material 105 using semiconductor processing equipment and/or 3D printers. Then a quarter micron (0.25 μm) layer of metal 104 is deposited on top of the UDM layer 105. This is repeated in an alternating process until five (5) complete UDM/metal sandwich layers are completed, thereby forming a 25 volt stack 102.

(36) The three UDM compounds are built up sequentially in molar percentages of about three percent (3%) to about twenty percent (20%) electrolyte (Table 2), about three percent (3%) to about twenty percent (20%) dielectric materials (Table 3), and about sixty percent (60%) to about ninety-four percent (94%) polar organic solvent (Table 1).

(37) These UDM compounds yield dielectric k values in the 10.sup.8 to 10.sup.11 range.

(38) Table 4 below reveals the high energy density of an embodiment of the capacitor of the present invention using a six (6) inch wafer and assuming k is at the median point of the range of about 10.sup.10. The UDM dielectric layer thickness is 0.5 μm in this example. Stacks of five layers in series creates a 25 volt capacitor. This embodiment yields 56.1 kWh of capacity with only 100 stacks.

(39) TABLE-US-00004 TABLE 4 A six inch wafer at the median k range k ε.sub.c A d F/lyr Lyrs F/stk Par Stks F Total J = CV.sup.2/2 kWh 1.00E+10 8.85E−12 0.182415 5.00E−07 3.23E+04 5 6560.5 100 646,055 201,892,084 56.1

(40) In one embodiment, the Fumed Silica utilized was 7 nm Aldrich powder.

(41) Capacitors made in accordance with the present invention may have a life cycle of more than 1,000,000 cycles even at deep discharge rates, e.g., eighty percent (80%) depth of discharge (“DoD”). The charge time for each capacitor may be about 30 seconds for full recharge.

(42) After the wafers or panels are processed, the capacitors may be sawed in various shapes and sizes and placed into the final packaging using activated carbon, graphene or other type electrodes.

(43) These capacitors may be used in electric vehicles (EVs) and charged using a “Capacitive Wireless Charging System and Method,” as described in patent application Ser. No. 62/511,754, filed May 26, 2017, by the same inventor, which may be easily installed in existing service stations. Other applications for the improved high energy density capacitor of the present invention include not only vehicles, but other modes of transportation including planes or trains, backup storage for utilities, windmills, and any other type of electrical facilities.

(44) In another embodiment, the wafers or substrates may be twelve (12″) inch (˜300 mm), but any size wafer or even rectangular LED panels will work in ALD, MOCVD and other semiconductor or 3D printing systems. Up to 370 mm×470 mm panels may be used to make rectangular capacitors. It is further contemplated by the present invention that larger panels may be used as they become available in the future.

(45) In one embodiment according to the present invention is a two solvent mixture of ethylene glycol and a polar organic cosolvent from Table 1. Boric acid is dissolved in this mixture with a carboxylic acid.

(46) A deposition chamber used in an exemplary solid state process for forming a capacitor in accordance with embodiments of the present invention is shown in FIG. 6. Dipoles structures in each dielectric layer are fabricated by depositing a layer of polarized dielectric material and aligning the dipoles using high voltage plates. This process requires minimal layers per capacitor.

(47) Capacitive plates are placed above and below the deposition chamber external to the chamber and a high voltage DC is applied. One capacitive plate takes on a high positive Voltage and the other a high negative Voltage, to ensure that the dipoles remain aligned while applying each subsequent layer. During ion deposition, the small dipoles in the Oxide layer align in the opposite direction of the Electric Field. After each layer is completed, the dipoles will remain aligned after the external Electric Field is removed. Consequently, the dielectric k value increases by several orders of magnitude and the breakdown voltages increase by an order of magnitude or more over what is conventionally expected. An advantage of this solid state deposition process is that many layers may be built up to make very large capacitors.

(48) Referring now to FIG. 7, an atomic layer deposition (ALD) chamber used in a second, different solid state process for forming a high energy density capacitor of the present invention is shown. In this process, the dipole structures are fabricated in a sandwich of alternating layers of ions and dielectric by first depositing a layer of dielectric 605 disposed above the p-Electrode 606, then a layer of n-ions 604, another layer of dielectric 603, a layer of p-ions 602, and another layer of dielectric 601 to insulate the p-ions from the n-Electrode 600. This process requires more layers per capacitor.

(49) As shown in FIG. 7, a wafer or substrate is placed at the bottom of the deposition chamber, and aligned with the positive electrode or p-Electrode. The first layer of ions is deposited by filling the chamber with ionic gas and placing a High Voltage plate inside the chamber beneath the substrate or wafer, as well as placing a High Voltage plate having an opposite voltage above and external to the chamber, to create a strong Electric Field by applying a DC Voltage. The stronger the Electric field applied, the more densely the layer of ions is able to be packed. Next, the chamber is cleared, and a dielectric layer is applied to hold the ions (up to five atomic layers may be required), before removing the Electric field. The chamber is then flooded with a positive ion gas and the voltage on the plates is reversed. As the Positive ions get close to the dielectric layer, the Negative ions underneath the dielectric layer attract the Positive ions and align them overhead, creating smaller dipoles. On each successive layer, the process of reversing the chamber plate Voltage is repeated, selecting the other ionizing tip, as necessary. It is further contemplated by the present invention that the positive and negative ions may instead be replaced by a mixture of bare electrons and protons. In another embodiment, electrospray may be used to deposit the ion layers.

(50) It is contemplated that other low cost, high fidelity methods may be used to deposit the dielectric layer. For example, technologies that may be suitable for producing dielectric layers of appropriate thickness include spin-coating, spray-coating, or screen printing. Generally, roll-to-roll coating methods are considered suitable.

(51) Thus, the present invention achieves one or more of the following advantages. The capacitor of the present invention provides a solution for replacing slow charging, short-life batteries with quick charging, long-life capacitors having a significant higher energy density than prior art capacitors. The method of forming the capacitor(s) of the present invention utilizes atomic layer deposition (ALD), metal oxide chemical vapor deposition (MOCVD), 3D printing and other semiconducting fabrication equipment to produce sub-micron thin layers and the capability for 12 inch wafers and/or rectangular substrates, like those used for LED panels, which are available in a wide variety of generations and sizes. Wafers may also be sawed into any shape or size and stacked to any height. The instant invention takes advantage of these advances by utilizing a large array of ALD machines and other standard semiconducting fabrication machinery, 3D printing and robotic automation to apply up to thousands of layers per day to mass produce the capacitors of the present invention in any shape or size.

(52) While the present invention has been particularly described, in conjunction with specific embodiments, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.