SIGNAL PROCESSING

Abstract

A signal processing device is configured to compensate for process and temperature variations deviating from a nominal process and temperature condition. A transconductance amplifier circuit produces a current output dependent on a voltage input and a transconductance gain. A transimpedance amplifier circuit produces a voltage output dependent on the current. A bias circuit comprises transistors (M.sub.1, M.sub.2) configured such that the gate and drain of the first transistor (M.sub.1) are connected to the gate of the second transistor (M.sub.2) and to a PTAT current source. The source of the first transistor (M.sub.1) is connected to a node via a first resistor (R.sub.1), and the source of the second transistor (M.sub.2) is connected to that node via a second, trimmable resistor (R.sub.2). A feedback circuit for the transimpedance amplifier comprises a third, trimmable resistor (R.sub.3). The ratio between a resistance of the second and third resistors (R.sub.2, R.sub.3) is constant.

Claims

1. A signal processing device configured to compensate for process and temperature variations deviating from a nominal process and temperature condition, the signal processing device comprising: i) a transconductance amplifier circuit portion having a respective voltage input and a current output, wherein the current output is dependent on the voltage input and a transconductance gain of said transconductance amplifier circuit portion; ii) a transimpedance amplifier circuit portion having a respective current input and a voltage output, wherein the voltage output is dependent on the current input and a transimpedance gain of said transimpedance amplifier circuit portion, wherein said transconductance and transimpedance amplifier circuit portions are arranged in series; iii) a bias circuit portion comprising first and second transistors configured such that: a gate terminal and a drain terminal of the first transistor are connected to a gate terminal of the second transistor and to a reference current input configured to receive a reference current from a proportional-to-absolute-temperature current source; a drain terminal of the second transistor is connected to a current supply input of the transconductance amplifier; a source terminal of the first transistor is connected to a node via a first resistor; and a source terminal of the second transistor is connected to said node via a second resistor, wherein the second resistor is trimmable; and iv) a feedback circuit portion connected between the input and output of the transimpedance amplifier, said feedback circuit portion comprising a third resistor, wherein the third resistor is trimmable; wherein a resistance of the first resistor is a predetermined value, said predetermined value being a resistance of the trimmable third resistor at the nominal process and temperature condition.

2. The signal processing device as claimed in claim 1, wherein a ratio between a resistance of the trimmable second resistor and the resistance of the trimmable third resistor is constant when said resistances are varied.

3. The signal processing device as claimed in claim 1, wherein a resistance of the second resistor is substantially equal to the resistance of the third resistor.

4. The signal processing device as claimed in claim 3, wherein the resistance of the first resistor is set to a value R.sub.typ typical of the third resistor at the nominal temperature and process condition, and each of the respective resistances of the second and third resistors are set to (1+?)*R.sub.typ.

5. The signal processing device as claimed in claim 1, wherein a resistance of the second resistor is different from the resistance of the third resistor.

6. The signal processing device as claimed in claim 5, wherein the resistance of the first resistor is set to a value R.sub.typ typical of the third resistor at the nominal temperature and process condition, the resistance of the second resistor is set to (1+?)*R.sub.typ, and the resistance of the third resistor is set to N*(1+?)*R.sub.typ.

7. The signal processing device as claimed in claim 1, further comprising the proportional-to-absolute-temperature current source.

8-10. (canceled)

11. The signal processing device as claimed in claim 1, wherein the third resistor has a first terminal thereof connected to the input of the transimpedance amplifier, and a second terminal thereof connected to the output of the transimpedance amplifier.

12. The signal processing device as claimed in claim 1, wherein the feedback circuit portion further comprises a capacitor connected in parallel with the third resistor.

13. The signal processing device as claimed in claim 12, wherein the capacitor has a first terminal thereof connected to a first terminal of the third resistor, and a second terminal thereof connected to a second terminal of the third resistor.

14. The signal processing device as claimed in claim 1, configured such that: the transconductance amplifier circuit portion comprises a respective input configured to receive an input voltage, and a respective output configured to generate a current dependent on said input voltage; and the transimpedance amplifier circuit portion comprises a respective input configured to receive the current from said transconductance amplifier, and a respective output configured to generate an output voltage dependent on said current.

15. The signal processing device as claimed in claim 1, wherein the transconductance amplifier circuit portion comprises an inverting input and a non-inverting input, wherein the transconductance amplifier circuit portion is configured to receive a differential input voltage across the inverting and non-inverting inputs of the transconductance amplifier circuit portion.

16. The signal processing device as claimed in claim 1, wherein an output of the transconductance amplifier circuit portion is single-ended.

17. The signal processing device as claimed in claim 1, wherein an output of the transconductance amplifier circuit portion is differential.

18. The signal processing device as claimed in claim 1, wherein the transimpedance amplifier circuit portion comprises an inverting input and a non-inverting input.

19. The signal processing device as claimed in claim 18, wherein a current from the transconductance amplifier circuit portion is supplied to the inverting input of the transimpedance amplifier circuit portion.

20. The signal processing device as claimed in claim 18, wherein the non-inverting input of the transimpedance amplifier circuit portion is connected to a fixed level.

21. The signal processing device as claimed in claim 19, wherein the fixed level is ground or virtual ground.

22. A method of configuring a signal processing device to compensate for process and temperature variations deviating from a nominal process and temperature condition, the signal processing device comprising: i) a transconductance amplifier circuit portion having a respective voltage input and a current output, wherein the current output is dependent on the voltage input and a transconductance gain of said transconductance amplifier circuit portion; ii) a transimpedance amplifier circuit portion having a respective current input and a voltage output, wherein the voltage output is dependent on the current input and a transimpedance gain of said transimpedance amplifier circuit portion, wherein said transconductance and transimpedance amplifier circuit portions are arranged in series; iii) a bias circuit portion comprising first and second transistors configured such that: a gate terminal and a drain terminal of the first transistor are connected to a gate terminal of the second transistor and to a reference current input configured to receive a reference current from a proportional-to-absolute-temperature current source; a drain terminal of the second transistor is connected to a current supply input of the transconductance amplifier; a source terminal of the first transistor is connected to a node via a first resistor; and a source terminal of the second transistor is connected to said node via a second resistor, wherein the second resistor is trimmable; and iv) a feedback circuit portion connected between the input and output of the transimpedance amplifier, said feedback circuit portion comprising a third resistor, wherein the third resistor is trimmable; wherein a resistance of the first resistor is a predetermined value, said predetermined value being a resistance of the trimmable third resistor at the nominal process and temperature condition; wherein the method comprises: varying a respective resistance of each of the trimmable second and third resistors such that a ratio between the resistances of said trimmable second and third resistors is constant.

23. A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to carry out the method of claim 22.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0090] Certain embodiments of the invention will now be described, by way of non-limiting example only, with reference to the accompanying drawings in which:

[0091] FIG. 1 is a schematic diagram of a prior art electronic device having cascaded transconductance and transimpedance amplifier stages;

[0092] FIG. 2 is a schematic diagram of a electronic device having cascaded transconductance and transimpedance amplifier stages in accordance with an embodiment of the present invention;

[0093] FIG. 3 is a schematic diagram of a prior art electronic device having differential cascaded transconductance and transimpedance amplifier stages; and

[0094] FIG. 4 is a schematic diagram of a electronic device having differential cascaded transconductance and transimpedance amplifier stages in accordance with a further embodiment of the present invention.

DETAILED DESCRIPTION

[0095] FIG. 2 is a schematic diagram of a electronic device 200 having cascaded transconductance amplifier circuit portion 202 and transimpedance amplifier circuit portion 204 stages in accordance with an embodiment of the present invention. The transimpedance amplifier circuit portion 204 is provided with a feedback circuit portion 206. Elements having reference numerals starting with a 2 correspond in structure and function to those elements having corresponding reference numerals starting with a 1 described previously with reference to FIG. 1, unless context dictates otherwise.

[0096] To compensate the gain change (across process variations) introduced by trimming of the feedback resistor R.sub.3 as outlined previously with respect to FIG. 1, the bias current I.sub.bias supplied to the transconductance amplifier circuit portion 202 by the bias circuit portion 208 is made resistance-dependent.

[0097] The bias circuit portion 208 comprises first and second transistors M.sub.1, M.sub.2 which are configured such that the gate and drain terminals of the first transistor M.sub.1 are connected to the gate terminal of the second transistor M.sub.2. These terminals (i.e. the gates of M.sub.1 and M.sub.2 and the drain of M.sub.1) are connected (or are connectable) to a reference PTAT current source that supplies a reference current I.sub.PTAT. The drain terminal of the second transistor M.sub.2 is connected to the current supply input of the transconductance amplifier 202. The source terminal of the first transistor M.sub.1 is connected to a node 210 via a first resistor R.sub.1, and the source terminal of the second transistor M.sub.2 is connected to that same node 210 via a second resistor R.sub.2, where the second resistor R.sub.2 is trimmable.

[0098] Thus rather than simply mirroring the PTAT current I.sub.PTAT (as in FIG. 1), the current mirror M.sub.1, M.sub.2 within the bias circuit portion 208 in FIG. 2 provides a variably degenerated version of the reference current I.sub.PTAT, generated by the current mirror arrangement M.sub.1, M.sub.2, R.sub.1 and R.sub.2, as outlined below. Newly introduced degeneration resistors R.sub.1 and R.sub.2, added to the source terminals of M.sub.1 and M.sub.2 respectively, provide for this degenerated version of I.sub.PTAT to be supplied as I.sub.bias to the transconductance amplifier 202.

[0099] The first resistor R.sub.1 is a fixed resistor having a resistance R.sub.typ, which is a default value corresponding to the typical value of the resistance of the trimmed feedback resistor R.sub.3 with a typical process. Conversely, the second resistor R.sub.2 is trimmable and may be set to the same resistance as the third resistor R.sub.3, i.e. the resistor in the feedback circuit portion 208, or may be set to an appropriate scale factor multiple of the resistance of the third resistor R.sub.3.

[0100] By setting the resistance R.sub.1 of the first resistor to R.sub.typ, and by setting the respective resistances R.sub.2 and R.sub.3 of the second and third resistors to R.sub.typ (1+?) and N*R.sub.typ (1+?) respectively, the expression for the transconductance amplifier biasing current I.sub.bias can be rewritten as per Equation 4, which is reproduced below:

[00006]$\begin{array}{cc}\begin{array}{c}{I}_{bias}=I_{\mathrm{PTAT}}\frac{R_1}{R_2}=I_{300}\frac{q}{k}\frac{1}{1+?}\\ \mathrm{Bias}\mathrm{current}\mathrm{supplied}\mathrm{to}\mathrm{transconductance}\mathrm{amplifier}\end{array}& \mathrm{Equation}4\end{array}$

[0101] As outlined previously, substituting this into the expression for the total gain yields Equation 5, reproduced below:

[00007]$\begin{array}{cc}\begin{array}{c}{K}_{tot}=K_{\mathrm{OTA}}{I}_{300}\frac{q}{k}G\left(I\right)N\frac{1}{1+?}{R}_{\mathrm{typ}}\left(1+?\right)=\mathrm{CONST}\left(T\right)?R_{\mathrm{typ}}\\ \mathrm{Temperature}\mathrm{and}\mathrm{process}\mathrm{invariant}\mathrm{gain}\end{array}& \mathrm{Equation}5\end{array}$

[0102] It can be seen from Equation 5 that this results in the gain being independent of both temperature and process variation.

[0103] If the respective resistances R.sub.2 and R.sub.3 of the second and third resistors are both set to R.sub.typ (1+?), i.e. such that their ratio N=1, this simplifies further to Equation 6 below:

[00008]$\begin{array}{cc}\begin{array}{c}{K}_{tot}=K_{\mathrm{OTA}}{I}_{300}\frac{q}{k}G\left(I\right)\frac{1}{1+?}{R}_{\mathrm{typ}}\left(1+?\right)=\mathrm{CONST}\left(T\right)?R_{\mathrm{typ}}\\ \mathrm{Temperature}\mathrm{and}\mathrm{process}\mathrm{invariant}\mathrm{gain}\mathrm{where}{R}_2\mathrm{and}{R}_3\mathrm{are}\mathrm{equal}\end{array}& \mathrm{Equation}6\end{array}$

[0104] It will be appreciated that as the ratio value N is constant (whether it is unity or not), it does not change the end result that the total gain K.sub.tot is constant with respect to temperature. The particular N chosen is a scaling factor, and does not alter the functionality of the device.

[0105] FIG. 3 is a schematic diagram of a prior art electronic device 300 having differential cascaded transconductance and transimpedance amplifier stages. Elements having reference numerals starting with a 3 correspond in structure and function to those elements having corresponding reference numerals starting with a 1 described previously with reference to FIG. 1, unless context dictates otherwise.

[0106] It will be appreciated that, when compared to the device 100 of FIG. 1, the differential device 300 of FIG. 3 makes use of both the inverting and non-inverting inputs of the transimpedance amplifier circuit portion 304, where the output current I.sub.out from the transconductance amplifier circuit portion 302 is differential (depending on the input voltage V.sub.in across its input terminals), and where the output voltage V.sub.out of the transimpedance amplifier circuit portion 304 is also differential.

[0107] The transimpedance amplifier circuit portion 304 is provided with two identical feedback circuits 306a, 306b each respectively constructed from a trimmable resistor R.sub.3 and a capacitor C.sub.1 connected in parallel between an input and output of the transimpedance amplifier 304. The first feedback circuit 306a is connected between the inverting output and non-inverting input of the transimpedance amplifier 304. The second feedback circuit 306b is connected between the non-inverting output and inverting input of the transimpedance amplifier 304.

[0108] FIG. 4 is a schematic diagram of a electronic device 400 having differential cascaded transconductance and transimpedance amplifier stages in accordance with a further embodiment of the present invention. Elements having reference numerals starting with a 4 correspond in structure and function to those elements having corresponding reference numerals starting with a 2 described previously with reference to FIG. 2, and to those elements having corresponding reference numerals starting with a 3 described previously with reference to FIG. 3, unless context dictates otherwise.

[0109] Unlike the prior art device 300 of FIG. 3, however, the device 400 uses the same resistance-dependent bias circuit portion 408 arrangement as the device 200 of FIG. 2 as outlined above, in accordance with the present invention.

[0110] Thus it will be appreciated that embodiments of the present invention provide an improved arrangement in which the total gain of the device (i.e. the product of the respective gains of the transconductance and transimpedance amplifier stages) is constant across temperature and process variations. This may be particularly advantageous in, for example, analogue signal processing chains such as those found in radio receiver devices, where having constant gain and bandwidth across such variations in temperature and process is advantageous, e.g. to avoid the need for post-processing steps to rectify issues caused by such variations. In other words, the effects of process and temperature variation can be cancelled out by the present invention.

[0111] While specific embodiments of the present invention have been described in detail, it will be appreciated by those skilled in the art that the embodiments described in detail are not limiting on the scope of the claimed invention.