DC-DC CONVERTER WITH GALVANIC ISOLATION AND CORRESPONDING METHOD OF CONTROL OF A DC-DC CONVERTER

Abstract

Provided is a DC-DC converter with galvanic isolation comprising a resonant oscillator coupled to a primary winding of a galvanic isolation transformer. A rectifier is coupled to a secondary winding of the transformer to provide an output voltage. The DC-DC converter comprises a regulation loop configured to regulate an output voltage with respect to a reference voltage by controlling a current flowing in the resonant oscillator as a function of a result of a signal indicative of the comparison between the output voltage and the reference voltage. The resonant oscillator is configured to operate at a frequency, in particular tuned at sub-resonant point, in particular sub-harmonic frequency, below a resonance frequency of the resonant oscillator which maximizes a quality factor of the resonant oscillator, in particular below a resonance frequency of a LC tank circuit comprised in the resonant oscillator which maximizes a quality factor of the LC tank circuit.

Claims

1. A DC-DC converter, comprising: a resonant oscillator coupled to a primary winding of a galvanic isolation transformer, a rectifier being coupled to a secondary winding of the galvanic isolation transformer to provide an output voltage; and a regulation loop configured to regulate the output voltage with respect to a reference voltage by controlling a current flowing in the resonant oscillator based on a signal indicative of a comparison between the output voltage and the reference voltage, wherein the resonant oscillator is configured to operate at a frequency that is below a resonance frequency of the resonant oscillator and which improves a quality factor of the resonant oscillator.

2. The converter of claim 1, wherein the resonant oscillator is configured to operate at the frequency that is below a resonance frequency of an LC tank circuit of the resonant oscillator which maximizes a quality factor of the LC tank circuit.

3. The converter of claim 1, wherein the resonant oscillator is configured to operate at the frequency that is tuned at a sub-harmonic frequency.

4. The converter of claim 1, wherein an operating frequency is a sub-harmonic of the resonance frequency.

5. The converter of claim 1, wherein the galvanic isolation transformer includes: a central tap on the primary winding to which an output of the resonant oscillator is coupled; and a central tap on the secondary winding to which an input of the rectifier is coupled, and the rectifier is a synchronized rectifier.

6. The converter of claim 1, wherein the regulation loop includes: a current generator stage configured to determine the current flowing in the resonant oscillator current sink, wherein the current generator stage includes a plurality of current generators in parallel that set a respective current path from the resonant oscillator when activated.

7. The converter of claim 6, wherein the regulation loop includes: a logic stage configured to: receive the signal indicative of the comparison between the output voltage and the reference voltage; and select for activation a corresponding set of current generators of the plurality of current generators.

8. The converter of claim 7, wherein the logic stage is configured to: switch off the plurality of current generators in sequence from a current generator drawing a largest current to a current generator drawing a smallest current in response to the output voltage being greater than the reference voltage; and switch on the plurality of current generators in sequence from the current generator drawing the smallest current to the current generator drawing the largest current in response to the output voltage being less than the reference voltage.

9. The converter of claim 8, wherein the logic stage is configured to: switch on the plurality of current generators in sequence from the current generator drawing the smallest current to the current generator drawing the largest current during a power on interval indicated by a respective power on signal.

10. The converter of claim 1, wherein the transformer is an integrated coreless transformer.

11. The converter of claim 1, wherein the converter operates at a frequency in a range between 10 and 200 megahertz (MHz).

12. A method, comprising: providing an output voltage by a rectifier that is coupled to a secondary winding of a galvanic isolation transformer, a resonant oscillator being coupled to a primary winding of the galvanic isolation transformer; regulating, by a regulation loop, the output voltage with respect to a reference voltage by controlling a current flowing in the resonant oscillator based on a signal indicative of a comparison between the output voltage and the reference voltage; and operating, by the resonant oscillator, at a frequency that is below a resonance frequency of the resonant oscillator and which improves a quality factor of the resonant oscillator.

13. The method of claim 12, comprising: switching off a plurality of current generators in sequence from a current generator drawing a greatest current to a current generator drawing a smallest current in response to the output voltage being greater than the reference voltage; and switching on the plurality of current generators in sequence from the current generator drawing the smallest current to the current generator drawing the greatest current in response to the output voltage being less than the reference voltage.

14. The method of claim 13, comprising: switching on the plurality of current generators in sequence from the current generator drawing the smallest current to the current generator drawing the greatest current in response to a power on interval indicated by a respective power on signal.

15. The method of claim 12, comprising: operating, by the resonant oscillator, at the frequency that is below a resonance frequency of an LC tank circuit of the resonant oscillator which maximizes a quality factor of the LC tank circuit.

16. The method of claim 12, comprising: operating, by the resonant oscillator, at the frequency that is tuned at a sub-harmonic frequency.

17. The method of claim 12, wherein an operating frequency is a sub-harmonic of the resonance frequency.

18. The method of claim 12, wherein the galvanic isolation transformer includes: a central tap on the primary winding to which an output of the resonant oscillator is coupled; and a central tap on the secondary winding to which an input of the rectifier is coupled, and the rectifier is a synchronized rectifier.

19. The method of claim 12, comprising: determining, by a current generator stage of the regulation loop, the current flowing in the resonant oscillator current sink, wherein the current generator stage includes a plurality of current generators in parallel that set a respective current path from the resonant oscillator when activated.

20. The method of claim 19, comprising: receiving, by a logic stage of the regulation loop, the signal indicative of the comparison between the output voltage and the reference voltage; and selecting, by the logic stage, for activation a corresponding set of current generators of the plurality of current generators.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0048] One or more embodiments will now be described, by way of example only, with reference to the annexed figures wherein:

[0049] FIG. 1 shows a DC-DC converter with galvanic isolation,

[0050] FIG. 2 shows a DC-DC converter including an oscillator that drives a coreless transformer,

[0051] FIG. 3 shows an architecture having, on a primary side of a power transformer, an N-MOS cross coupled auto-resonant oscillator,

[0052] FIG. 4 is a circuit schematics of a converter according to embodiments,

[0053] FIG. 5 details an embodiment of a logic module of the converter here described,

[0054] FIG. 6 is a time diagram of signals formed in the converter in embodiments during a startup phase and a regulation phase, and

[0055] FIG. 7 is a time diagram of signals formed in the converter in embodiments during a regulation phase.

DETAILED DESCRIPTION

[0056] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0057] Reference to an embodiment or one embodiment in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as in an embodiment or in one embodiment that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0058] The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0059] With reference to FIG. 4, it shown schematically an architecture 40 of fully integrated DC-DC converter with galvanic isolation according to the solution here described.

[0060] The architecture 40 comprises a circuit block 41 which includes a pair of cross coupled NMOS transistors N1 and N2 with respective capacitors C1, C2 arranged in series on the coupling between the gate of one of the NMOS N1, N2 and the drain of the other. The drains of the NMOS transistors N1, N2 are coupled one to the other by means of a tank capacitor CT and are respectively coupled to the two terminals of a primary winding 42a of a power transformer 42, which is in particular an integrated coreless power transformer, ensuring the galvanic isolation. The circuit block 41 with the primary winding 42a forms a self-resonant NMOS oscillator.

[0061] The power transformer 42 comprises also a central tap Tc1, which is coupled to the DC input voltage VIN. A synchronous rectifier 43 is provided on the secondary side, which includes a pair of cross coupled NMOS transistors N3, N4 with respective capacitors C3, C4 on the coupling between the gate of one of the NMOS transistors N3, N4 and the drain of the other. The drains of the NMOS transistors N3, N4 are respectively coupled to the two terminals of a secondary winding 42b of the power transformer 42. An output node of the DC-DC converter 40 is taken on a central tap Tc2 on the secondary winding 42b, on which is taken the output voltage VOUT, to which a load ZL is shown coupled, and to which is coupled also control loop 44.

[0062] The synchronous rectifier 43 is coupled to the terminals of the secondary winding of the power transformer 42. Circuit 43 operates as self-driven synchronous rectifier, i.e., the gate source voltages of the NMOS transistors N3, N4 vary in a complementary manner with period or duty cycle depending on the period or duty cycle of the voltage at the input of the transformer 42, determined by the oscillator 41. Therefore, the resulting waveform on the load ZL combining such two complementary waveforms is rectified. In the synchronous rectifier 43, capacitor C3 and C4 are used as voltage divider with the equivalent capacitance on the gates of the NMOS gates to guarantee the correct and safe gate source voltage.

[0063] The control loop 44 comprises a voltage divider 441, i.e., a resistor R1 coupled to the output node VOUT in series with a resistor R2 coupled to ground, providing at its output node, i.e., the node common between resistors R1 and R2, a voltage proportional to the output voltage VOUT to an differential amplifier 442, in particular implemented by an operational amplifier, which at its inverting input receives a reference voltage REF. The differential amplifier 442 operates substantially as a comparator issuing a feedback signal FB which is for instance logic high if the voltage VOUT is over the reference voltage VREF inputted to a control logic module 443, which, on the basis of the value of the feedback signal FB, drives the gate of a NMOS generator module, N5, coupled to the sources of NMOS transistors N1 and N2 and its source to ground, controlling the current flowing in the self-resonant NMOS oscillator 41 and 42a. The NMOS generator module N5 is shown as a NMOS transistor with drain coupled to the sources of NMOS N1, N2 and source to ground, nevertheless, as shown in the following, included a plurality of generators in parallel.

[0064] Thus, the converter 40 comprises at the primary side a typical self-resonant NMOS structure, i.e., oscillator 41 and transformer 42, with central tap and a control logic module 443 for performing a feedback control loop of the output voltage VOUT. On the secondary side there is a synchronous rectifier 43 with the central tap of transformer 42 and the control circuitry, i.e., voltage divider 441 and differential amplifier 442, that generates the feedback signal FB. As shown, with respect to FIG. 3 in this case the feedback signal FB correspond substantially to the error between the regulated quantity, the voltage output VOUT, and the reference quantity, reference voltage, without any PWM generation, while block 443 represents substantially the controller of the loop. It is noted that for feedback signal FB is intended here (and in FIG. 3) the signal fed back to the primary side, although from a control point view represents the error between the regulated quantity and the set point or reference, while the regulated quantity, the output voltage VOUT is fed back through the divider 441, which represent the measurement system according to one of the most diffused schematization of control loops.

[0065] The cross coupled NMOS oscillator 41 and 42a is configured to operate at sub-resonant frequency (in the example at 60 MHz), by tuning the LC-tank, i.e., tank capacitor CT. Typical value of capacitance of the tank capacitor CT are in the order of tens pF while inductance is in the order of tens nH.

[0066] BCD (Bipolar CMOS DMOS) Technology used for the exemplary embodiment shows losses at high frequency >100 MHz. This is a trade-off for overall system efficiency.

[0067] Then, choosing the central tap on both sides of transformer 42, the magnetic flux during the switching phases is optimized. The central tap solution in the secondary side reduces the resistive loss during rectification (compared to a full bridge diode) halving the transformer resistive path.

[0068] With respect to the solution with a passive bridge rectifier with Schottky diode such as in block 33 in FIG. 3, here a synchronous rectifier 33 is implemented. Such type of rectifier, to the difference of Schottky diodes, can be implemented in BCD technology. Such type of rectifier guarantees a low on drain to source voltage drop, even lower than the voltage drop of the Schottky diodes, which results in less power losses in favor of the efficiency of the system.

[0069] The control logic module 443 is designed to avoid dangerous voltage spikes. The design is oriented to better control the system and energy management.

[0070] As shown in FIG. 5, the control logic module 443 implements a soft start logic module 4431 and soft regulation logic module 4432, both logic modules which may be for instance implemented as software modules in a processing device, such as a microprocessor or a DSP, that guarantee safety against voltage peaks due the LC tank CT and prevents from using other protections that are often expensive in terms of area and efficiency.

[0071] The soft start logic module 4431 is driven by a PowerON signal PON while the regulation logic module 4432 by the feedback signal FB. The PowerON signal may be provided by an external logic module, e.g., the processor controlling the converter 40. A further generator switch on/off logic 4433 issues a value Z, integer between 0 and N to a set of N+1, 0 to N, buffers 4434 in parallel driving the gate of a respective NMOS generator module N5. Each buffer in the set of buffers 0 to N is greater, i.e., drives a greater current at its output than the other, increasing from 0 to N. The NMOS generator module, N5 corresponds in fact to N+1 NMOS N5.sub.0 . . . . N5.sub.N in parallel with their drain coupled to the sources of the NMOS N1 and N2, in particular through respective resistors R5.sub.0 . . . . R5.sub.N which may represent the on drain source resistance RDS.sub.ON of their relative NMOS switch N5.sub.0 . . . . N5.sub.N, and the source coupled to ground, while each gate of the NMOS N5.sub.0 . . . . N5.sub.N is driven by a respective buffer 4434, BF.sub.0 . . . . BF.sub.N in the set of N+1 buffers. Thus, N5 represents a quantized current generator to quantize the Source current of primary side through N+1 current path I.sub.0 . . . . I.sub.N, through the respective NMOS N5.sub.0 . . . . N5.sub.N which draws an increasing current from 0 to N. The law according to which the currents I.sub.0 . . . . I.sub.N increase from 0 to N may be different depending on the transformer characteristics (also it may depend more generically on processing limitation of the technology), it may be monotonously increasing, it may increase by a fixed multiplication factor, e.g., double, with each subsequent value of the index i from 0 to N, it may follow a 2.sup.i law of increase or other increase law depending on index i or it may simply have a set of selected increasing values. In the exemplary case N may be equal to 4, thus five current generators are provided. Thus, the NMOS N5.sub.0 . . . . N5.sub.N draw an increasing current, which can be obtained by using NMOS with increasing aspect ratio, while, buffers BF.sub.0 . . . . BF.sub.N have increasing size one with respect to the other, i.e., are able to output an increasing driving current, indicated as gate signal Gate<0 . . . N> to the gate of the respective NMOS, i.e., adapt to the size of the NMOS. The form Signal<0 . . . N> here and in the following indicates that the signal by the name Signal carries one of the values from 0 to N.

[0072] Currents, number of paths and timing may be adapted according to frequency and energy of spikes.

[0073] The way to switch the current paths is managed by the generator switch on/off logic 4433 which selects the buffer BF.sub.0 . . . . BF.sub.N in the module 4434 according to signal Start<0 . . . N> issued by the soft start logic module 4431 on the basis of the power on signal PON or according to signal Reg <0 . . . N> issued by the regulation logic module 4432 on the basis of the feedback signal FB.

[0074] As shown with reference to FIG. 6, the logic 4433 is driven by module 4431 in a startup time interval ST, while is driven by the module 4432 at a regulation phase RG, which occurs at a different time.

[0075] The feedback signal FB may be brought to the logic module 443 by a respective isolation transformer, in the same way as shown in FIG. 3, or more generally by an isolated data channel.

[0076] In FIG. 6 it is shown a time diagram, indicating as a function of time t the PowerON signal PON, and the opening/closure state of the N+1 NMOS N5.sub.0 . . . N5.sub.N (which may be equivalent to the drain source current flowing through them) with N=4, the coil voltage VCoil, i.e., the voltage on the inductive coil of transformer 42, and the output voltage VOUT.

[0077] FIG. 6 represents the startup time interval ST, which beginning is identified by the PowerOn signal PON going to high level (or the logic level which asserted indicates power on). During a startup time interval ST with PowerOn signal PON asserted, the NMOS switches NMOS N5.sub.0 . . . N5.sub.N are switched on in sequence from turn on from N5.sub.0 to N5.sub.N, that is from the smallest to the largest increasing accordingly the current flowing in the oscillator 41.

[0078] This startup time interval ST, which is commanded by module 4431 to module 4433 which in turn selects the buffer to activate among buffers BF.sub.0 . . . BF.sub.N to obtain the sequence of switch on shown in FIG. 6, allows to obtain a smooth start of all power nets that gradually go up. The gate voltage of the MOS N5.sub.0 in startup phase is managed differently from others MOS in particular increased gradually with input voltage VIN. It allows a gradually soft start of the Vcoil.

[0079] In FIG. 7 it is shown a time diagram, indicating as a function of time t the feedback signal FB, and the opening/closure state of the N+1 NMOS N5.sub.0 . . . N5.sub.N, with N=4, the coil voltage VCoil and the output voltage VOUT. FIG. 7 represents only the regulation phase RG, which is also visible in the diagram of FIG. 6, following the startup interval ST after an interval in which the output voltage VOUT reaches the set point value, i.e., reference voltage REF.

[0080] When the feedback signal FB is low level (or the logic level to which is asserted indicates that VOUT, in particular the value of VOUT divided by the divider value is below REF), all the N+1 NMOS N5.sub.0 . . . N5.sub.N are conducting, thus the NMOS N5.sub.0 . . . N5.sub.N are all closed drawing the respective currents I.sub.0 . . . I.sub.N from the NMOS N1, N2. The output voltage VOUT therefore increases.

[0081] When the feedback signal FB goes high, i.e., the output signal VOUT is above the reference voltage REF the NMOS N5.sub.0 . . . N5.sub.N turn off one after the other starting from N5.sub.N, where N=4 in this case, with a given time delay between one closure and the other. This makes the coil voltage Vcoil to decrease gradually, without dangerous peaks.

[0082] When the feedback signal FB goes low, i.e., the output signal VOUT is below the reference voltage REF the NMOS N5.sub.0 . . . N5.sub.N turn on one after the other starting from N5.sub.0 to N5.sub.N where N=4 in this case, with a given time delay. This makes the coil voltage Vcoil to increase gradually, without dangerous peaks.

[0083] From the description here above are clear the advantages of the solution here described.

[0084] Such advantages in an area of integrated power conversion with galvanic isolation are essentially linked to the simplification of the entire system, accompanied by low consumption and area occupation, guaranteeing high safety and efficiency standards.

[0085] Thus, by operating at a frequency of the system tuned at sub-resonant point, in particular at a sub-harmonic frequency, lower than the resonant frequency at the highest Q of the LC-Tank, the switching losses on the analog power switches are decreased.

[0086] Then, the secondary side is advantageously made with central tap and works as synchronous rectifier, increasing the efficiency on the secondary side.

[0087] The use of a quantized current to control the oscillator makes possible to manage in safe the current and avoid voltage spikes.

[0088] Advantageously, the control logic implements soft start and soft regulation circuit that guarantees safety against voltage peaks due LC tank and prevents from using other protections that are often expensive in terms of area and efficiency.

[0089] Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the scope of protection.

[0090] The DC-DC converter with galvanic isolation here described can be used as standalone isolated DC-DC converter. Also it can be used in other architectures requiring DC-DC conversion with galvanic isolation such as the DC-DC conversion supplying an isolated supply voltage to an isolated driver.

[0091] As mentioned applications may also include PLC analog input and output modules, Isolated Interface and sensors, motor control, industrial automation, isolated voltage and current sensing, RS-485/RS-422/CAN transceivers, medical equipment.

[0092] In embodiments the converter may operates at a frequency frequencies may between 10 and 100 MHz, in variant embodiments may be between 10 and 200 MHz. The range of the frequencies may depend on the technology used, e.g., frequency limits for losses, if BCD technology is used an upper limit of the frequencies may be around 100 MHz.

[0093] The extent of protection is defined by the annexed claims.

[0094] A DC-DC converter (30; 40) with galvanic isolation may be summarized as including a resonant oscillator (31; 41, 42a) coupled to a primary winding (42a) of a galvanic isolation transformer (32; 42), a rectifier (33; 43) being coupled to a secondary winding (42b) of said galvanic isolation transformer (32; 42) to provide an output voltage (VOUT), said DC-DC converter (30; 40) comprising a regulation loop (44) configured to regulate said output voltage (VOUT) with respect to a reference voltage (REF) by controlling a current flowing in said resonant oscillator (41, 42a) as a function of the result of a signal indicative of the comparison (PFB; FB) between said output voltage (VOUT) and said reference voltage (REF), wherein said resonant oscillator (41, 42a) is configured to operate at a frequency, in particular tuned at sub-resonant point, in particular at sub-harmonic frequency, below the resonance frequency of said resonant oscillator (41, 42a) which maximizes the quality factor of the resonant oscillator (41, 42a), in particular below the resonance frequency of a LC tank circuit (CT, 42a) comprised in said resonant oscillator (41, 42a) which maximizes the quality factor of said LC tank circuit (CT, 42a).

[0095] Said operating frequency may be a sub-harmonic of the resonance frequency.

[0096] Said galvanic isolation transformer (42) may include a central tap (Tc1) on the primary winding (42a) to which the output of the resonant oscillator (41) may be coupled and a central tap (Tc2) on the secondary winding (42b) to which the input of the rectifier is coupled, and the rectifier is a synchronized rectifier

[0097] Said regulation loop (44) may include a current generator module (N5) which may determine the current flowing in said resonant oscillator current sink, which may include a plurality of current generators (N5.sub.0 . . . N5.sub.N) in parallel setting a respective current path (I.sub.0 . . . I.sub.N) from the resonant oscillator (41) when activated.

[0098] Said regulation loop (44) may include a logic module (441) receiving as input said signal indicative of the comparison (FB) between said output voltage (VOUT) and said reference voltage (REF) and configured to select for activation a corresponding set of current generators (N5.sub.0 . . . N5.sub.N) in said plurality of current generators (N5.sub.0 . . . N5.sub.N).

[0099] Said logic module (441) may be configured to switch off the plurality of current generators (N5.sub.0 . . . N5.sub.N) in sequence, in particular from the current generator (N5.sub.0 . . . N5.sub.N) drawing the greater current to the smaller, when the output voltage (VOUT) is greater than the reference voltage (REF), and to switch on the plurality of current generators (N5.sub.0 . . . N5.sub.N) in sequence, in particular from the current generator (N5.sub.0 . . . N5.sub.N) drawing the smaller current to the greater, when the output voltage (VOUT) is smaller than the reference voltage (REF).

[0100] Said logic module (441) may be configured to switch on the plurality of current generators (N5.sub.0 . . . N5.sub.N) in sequence, in particular from the current generator (N5.sub.0 . . . N5.sub.N) drawing the smaller current to the greater, during a power on interval (ST) indicated by a respective power on signal (PON).

[0101] Said transformer (42) may be an integrated coreless transformer, in particular to be integrated in a System in Package (SiP).

[0102] Said converter may operate at a frequency in a range between tens and hundreds of MHz, in particular between 10 and 200 MHz.

[0103] A method of controlling a DC-DC converter may be summarized as including switching off the plurality of current generators (N5.sub.0 . . . N5.sub.N) in sequence, in particular from the current generator (N5.sub.0 . . . N5.sub.N) drawing the greater current to the smaller, when the output voltage (VOUT) is greater than the reference voltage (REF), and to switch on the plurality of current generators (N5.sub.0 . . . N5.sub.N) in sequence, in particular from the current generator (N5.sub.0 . . . N5.sub.N) drawing the smaller current to the greater, when the output voltage (VOUT) is smaller than the reference voltage (REF).

[0104] A method of controlling a DC-DC converter may be summarized as including switching on the plurality of current generators (N5.sub.0 . . . N5.sub.N) in sequence, in particular from the current generator (N5.sub.0 . . . N5.sub.N) drawing the smaller current to the greater, during a power on interval (ST) indicated by a respective power on signal (PON).

[0105] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.