High-voltage fast-avalanche diode

Abstract

A method of using a diode device including providing a diode that includes an active region including a 525 micron thick. 10 k?-cm, n-type, float zone wafer, and operating the diode as a silicon-avalanche semiconductor switch.

Claims

1. A diode device comprising: a diode comprising a silicon-avalanche semiconductor switch that has an active region comprising a 525 micron thick, 10 k?-cm, n-type, float zone wafer, wherein a cathode of said diode is connected to ground via a 1 pF peaking capacitor, and also to a 6-kV, 1-ns pulsed-power generator via a 200 pF DC-block capacitor and a 20 nH coil.

2. The diode device according to claim 1, wherein said silicon-avalanche semiconductor switch has a rise time of 100 ps.

3. The diode device according to claim 1, wherein said silicon-avalanche semiconductor switch has an output voltage of 7.9 kV.

4. The diode device according to claim 1, wherein said silicon-avalanche semiconductor switch comprises a vertical p+-n.sub.0-n.sup.+ structure with a substrate comprising a float-zone, N-type Si wafer.

5. A method of using a diode device comprising: providing a diode comprising an active region comprising a 525 micron thick, 10 k?-cm, n-type, float zone wafer; and comprising operating said diode as a 7.9-kV, 100-ps rise-time silicon-avalanche semiconductor switch.

6. A method of using a diode device comprising: providing a diode comprising an active region comprising a 525 micron thick, 10 k?-cm, n-type, float zone wafer; and operating said diode as a silicon-avalanche semiconductor switch, wherein operating said diode comprises connecting a cathode of said diode to ground via a 1 pF peaking capacitor, and also to a 6-kV, 1-ns pulsed-power generator via a 200 pF DC-block capacitor and a 20 nH coil.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates SAS structure (not to scale), in accordance with an embodiment of the invention.

(2) FIG. 2 illustrates an experimental setup circuitry for the device of the invention.

(3) FIG. 3 shows the load voltage versus time, measured on a 50? load.

DETAILED DESCRIPTION

(4) Reference is now made to FIGS. 1 and 2.

(5) The SAS diode may be prepared by the following process, in accordance with a non-limiting embodiment of the invention:

(6) First Implant, of the p.sup.+ Layer:

(7) 1. A thermal oxide, SiO.sub.2, is deposited on both sides of a 525 micron, 10 k?-cm, n-type, float zone wafer. 2. Selective opening in the top (boron) side is made via a mask which includes the p.sup.+-n.sub.0 junction, as in FIG. 1. 3. A boron-SOD is applied to the structure top side. It is noted that this step can be replaced by a standard method such as ion-implantation, or diffusion using a solid or a gas source. Also, other acceptor materials such as aluminum can be used as well. 4. A drive-in of the boron for a depth of a few microns is made.
Second Implant, of the n+ Layer: 1. Etching of the oxide in the bottom (phosphorous) side of the wafer is made. 2. A phosphorous SOD is applied to the structure bottom side. It is noted that this step can be replaced by a standard method such as ion-implantation, or diffusion using a solid or a gas source. Also, other donor materials such as arsenic can be used as well. 3. A drive-in of the phosphorous for a depth of about a few microns is made.
Finally, Metallic Contacts are Applied to the Structure.

(8) A diode with a junction cross section of 4 mm.sup.2 may be thus prepared. Its leakage current is measured at a reverse voltage of 3 kV. A 72 ?A current is measured without a breakdown. When two diodes are connected in series the leakage current is reduced by a factor of 2.

(9) In order to test it dynamically, the inventors connected its cathode to the ground via a 1 pF peaking capacitor, and also to a 6-kV, 1-ns pulsed-power generator (measured on a 50-? load) via a 200 pF DC-block capacitor and a 20 nH coil, as shown in FIG. 2. The SAS anode was connected to a 50? load and measured by a high-voltage attenuator and an 8-GHz oscilloscope. The inventors estimate that the maximum voltage obtained at the peaking capacitor before the SAS was turned on was about 14 kV.

Experimental Result

(10) FIG. 3 shows the load voltage, measured on a 50? load. A peak voltage of 7.9 kV was obtained. Following a pre-pulse of about 1.5 kV, a sharp, 100-ps rise time was obtained. The maximum voltage rise-rate at the load was 52 kV/ns. The experimental results are supported by a numerical simulation (not shown here).

Comparison

(11) Table 1 shows a comparison of this invention to two other state-of-the-art sharpening devices from the literature (first column). The second column shows the width of the active region. It is noted that the width in this invention is substantially wider, which enables working with a thick wafer, and alleviates the need for deep diffusion. Therefore it simplifies the process and reduces the cost.

(12) The third and fourth columns describe the input and output pulse, respectively, in terms of peak voltage and rise-time. The fifth column describes the maximum rise-rate of the load voltage. The sixth column refers to the number of diodes used, in case of a high-voltage stack [13], thus, the seventh column calculates the rise-rate per diode. The eighth column shows a figure of merit for the sharpening quality, in terms of output rise-rate to input voltage and its rise-time.

(13) It is seen that in this invention the voltage rise rate (single diode) and the quality of sharpening is higher than the prior art.

(14) TABLE-US-00001 Max # of sharpening Active dV.sub.o/dt diodes, (dV.sub.o/dt)/N (dV.sub.o/dt)/ Ref. region V-in V-out [kV/ns] N [kV/ns] (Vin/tr) Lyubutin 180 ?m 180 kV/ 150 kV/100 ps 1580 44 36 3.5 (2010) [13] 400 ps Brylevskiy 100 ?m 2.2 kV/ 1.25 kV/100 ps 10 1 10 3.2 (2019) [14] 700 ps This 520 ?m 10 kV/ 7.9 kV/100 ps 48 1 52 5.2 invention 1 ns

REFERENCES

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