POWER CORD LCDI AND HOTSPOT DETECTOR CIRCUIT

Abstract

A LCDI power cord circuit is provided. The circuit includes energizing shielded wires and monitoring the energized shields for surges, e.g., arcing, and/or voltage drops, e.g., shield breaks detected by a Power Cord Fault Circuit (PCFC). In addition to shield breaks the PCFC also monitors the energized shields for shield degradation due to, for example, galvanic corrosion.

Claims

1. A Leakage Current Detection Interrupter (LCDI) circuit for interrupting AC power from an AC source connected to a load via an insulated neutral wire and an insulated line wire, the LCDI circuit comprising: the insulated neutral wire surrounded by a neutral wire shield (NWS); the insulated line wire surrounded by a line wire shield (LWS), wherein the LWS is connectable to the NWS; a power cord fault circuit (PCFC) for monitoring the NWS and LWS integrity and leakage current, wherein the PCFC comprises: a non-linear device (NLD) connectable to the NWS; a bi-stable latching device for interrupting the AC power from the AC source; and a power supply circuit for supplying a first rectified voltage waveform to the PCFC and the LWS.

2. The LCDI circuit as in claim 1 wherein the NLD comprises: a NPN transistor having an emitter, a base, a collector, and configured as a common emitter amplifier; at least one first base biasing resistor connectable to the NWS and the base; at least one second base biasing resistor connectable to the LWS and the power supply circuit; and at least one collector biasing resistor connectable to the collector and the power supply circuit.

3. The LCDI circuit as in claim 2 further comprising: the NPN transistor collector connected to a bi-stable latching device having on/off states, the NPN being selectively turned on and the bi-stable latching device turned off based on a first sufficient portion of the first rectified signal applied to the base of the NPN transistor.

4. The LCDI circuit as in claim 3 further comprising: the NPN transistor selectively turned off and the bi-stable latching device turned on based on a first insufficient portion of the first rectified signal applied to the base of the NPN transistor and wherein the bi-stable latching device is selectively turned on within a first period.

5. The LCDI circuit as in claim 4 further comprising: a first capacitor connected to the NPN transistor collector and the at least one collector biasing resistor and wherein the NPN transistor, the first capacitor, the at least one collector biasing resistor, the at least one base biasing resistor, and a degraded NWS or degraded LWS determine the first period.

6. The LCDI circuit as in claim 5 further comprising: the NPN transistor selectively turned off and the bi-stable latching device turned on based on a second insufficient portion of the first rectified signal applied to the base of the NPN transistor and wherein the bi-stable latching device is selectively turned on within a second period and wherein the first capacitor and the at least one collector biasing resistor determine the second period, and wherein the second period is less than the first period.

7. The LCDI circuit as in claim 6 further comprising: the NPN transistor selectively turned off and the bi-stable latching device turned on based on a negative voltage applied to the NPN transistor base.

8. A Power Cord Shield Monitoring (PCSM) circuit for interrupting AC power from an AC source connected to a load via an insulated neutral wire surrounded by a neutral wire shield (NWS) and an insulated line wire surrounded by a line wire shield (LWS), wherein the NWS and LWS are connected via a shield connector, the PCSM circuit comprising: a non-linear device (NLD) connectable to the NWS, wherein the NLD comprises: a saturation mode; a cut-off mode; an active mode; and a bi-stable latching device connected to the NLD for interrupting the AC power from the AC source based on the NLD mode.

9. The PCSM circuit as in claim 8 wherein the NLD comprises: a NPN transistor having an emitter, a base, and a collector; a base biasing circuit for biasing the base of the NPN transistor comprising: at least one resistor; the NWS; the LWS; the shield connector; at least one collector biasing resistor connectable to the collector and the bi-stable latching device wherein the NPN transistor, the base biasing circuit and the at least one collector biasing resistor determine the NPN transistor mode; and at least one capacitor connectable to the at least one collector biasing resistor and the bi-stable latching device.

10. The PCSM circuit as in claim 9 further comprising: the NPN transistor selectively turned on and the bi-stable latching device turned off when the NPN transistor is in the saturation mode.

11. The PCSM circuit as in claim 9 further comprising: the NPN transistor selectively turned off and the bi-stable latching device turned on within a first period when the NPN transistor is in the cut off mode, wherein the first period is determined by the at least one collector biasing resistor and the at least one capacitor.

12. The PCSM circuit as in claim 9 further comprising: the NPN transistor selectively turned partially off and the bi-stable latching device turned on within a second period when the NPN transistor is in the active mode, wherein the second period is determined by the NPN transistor the base biasing circuit, the at least one collector biasing resistor and the at least one capacitor.

13. A Power Cord Shield Monitoring (PCSM) circuit for interrupting AC power from an AC source connected to a load via an insulated neutral wire surrounded by a neutral wire shield (NWS) and an insulated line wire surrounded by a line wire shield (LWS), wherein the NWS and LWS are connected via a shield connector, the PCSM circuit comprising: a non-linear device (NLD) connectable to the NWS, wherein the NLD comprises: a saturation mode; a cut-off mode; an active mode; wherein the NLD comprises: a NPN transistor having an emitter, a base, and a collector; a base biasing circuit for biasing the base of the NPN transistor, the base biasing circuit comprising: at least one base biasing resistor; the NWS; the LWS; the shield connector; at least one collector biasing resistor connectable to the collector and a bi-stable latching device, wherein the NPN transistor, the base biasing circuit and the at least one collector biasing resistor determine the NPN transistor mode; a mechanically latched double pole switch disposed between the AC source and the load; a relay for delatching the double pole switch; the bi-stable latching device connected to the NLD and the relay for interrupting the AC power from the AC source based on the NLD mode; at least one capacitor connectable to the NLD and the bi-stable latching device; and a power supply circuit for biasing the NLD and the bi-stable latching device.

14. The PCSM circuit as in claim 13 wherein the power supply circuit comprises a full wave bridge rectifier.

15. The PCSM circuit as in claim 13 further comprising: the NPN transistor selectively turned on and the bi-stable latching device turned off when the NPN transistor is in the saturation mode.

16. The PCSM circuit as in claim 13 further comprising: the NPN transistor selectively turned off and the bi-stable latching device turned on within a first period when the NPN transistor is in the cut off mode, wherein the first period is determined by the at least one collector biasing resistor and the at least one capacitor.

17. The PCSM circuit as in claim 13 further comprising: the NPN transistor selectively turned partially off and the bi-stable latching device turned on within a second period when the NPN transistor is in the active mode, wherein the second period is determined by the NPN transistor the base biasing circuit, the at least one collector biasing resistor and the at least one capacitor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The subject matter which is regarded as the invention is pointed out and distinctly claimed at the end of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the drawings in which:

[0013] FIG. 1 is a circuit block diagram of the LCDI Power Cord Circuit in accordance with the present invention;

[0014] FIG. 1A is a detailed schematic diagram of the block diagram in FIG. 1;

[0015] FIG. 2 is a waveform diagram for the normal operating condition of the Power Cord Circuit in FIGS. 1, 1A;

[0016] FIG. 3 is a waveform diagram for the leakage current detection condition of the Power Cord Circuit in FIGS. 1, 1A;

[0017] FIG. 4 is a waveform diagram for the shield open condition of the Power Cord Circuit in FIGS. 1, 1A;

[0018] FIG. 5 is a waveform diagram for the shield degraded condition of the Power Cord Circuit in FIGS. 1, 1A;

DETAILED DESCRIPTION

[0019] The following brief definition of terms shall apply throughout the application:

[0020] The term comprising means including but not limited to, and should be interpreted in the way it is typically used in the patent context;

[0021] The phrases in one embodiment, according to one embodiment, generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present invention, and may be included in more than one embodiment of the present invention (such phrases do not necessarily refer to the same embodiment);

[0022] If the specification describes something as exemplary or an example, it should be understood that refers to a non-exclusive example; and

[0023] If the specification states a component or feature may, can, could, should, preferably, possibly, typically, optionally, for example, or might (or other such language) be included or have a characteristic, that particular component or feature is not required to be included or to have the characteristic.

[0024] Referring to FIG. 1 there is shown a circuit block diagram of a LCDI POWER CORD CIRCUIT 10 (LCDI). LCDI circuit 10 includes Line Wire Shield (LWS) 24A and Neutral Wire Shield (NWS) 24B, TEST switch 18, power supply circuit 100, power cord fault circuit (PCFC) 110, relay 16; and, manually engaged ganged switches 12A, 12B, the manual reset switch. LCDI circuit 10 also includes R4 and LED for indicating normal operation. Also included are metal oxide varistors MOV1 and MOV2 for circuit overload protection.

[0025] When manual reset switches 12, 12A are set, line voltage is connected to LOAD and to power supply circuit 10 via relay 16. Power supply circuit 100 supplies bias voltages to PCFC 110, and shields 24A and 24B. Shields 24A and 24B are connected in series at the Load end. As discussed and shown in more detail herein, the PCFC 110 lets a small amount of relay current flow through relay 16 but less than the energizing current needed to energize relay 16 to disengage manual reset switches 12A,12B. It is appreciated that not starting from zero energizing current lets solenoid 16 energize faster when a fault is detected.

[0026] Referring also to FIG. 1A there is shown a detailed circuit 10A of the block diagram 10 in FIG. 1. LCDI circuit 10A includes Line Wire Shield (LWS) 24A, Neutral Wire Shield (NWS) 24B, SHIELD CONNECTOR 24C, TEST switch 18, power supply circuit 100A, and PCFC 110A. PCFC 110A includes transistor Q1, capacitor C1, and silicon-controlled rectifier SCR. It will be understood that Q1 may be any suitable non-linear device having a saturation mode, a cut-off mode, and an active mode. SCR may be any suitable bi-stable latching device. Line Wire Shield (LWS) 24A and Neutral Wire Shield (NWS) 24B may be any suitable conductive shield surrounding the line and neutral wires as discussed in more detail herein. When manual reset switches 12, 12A are set line voltage is connected to LOAD and to power supply circuit 100A via relay 16. Power supply circuit 100A supplies bias voltages to PCFC 110A, and shields 24A and 24B. As discussed and shown in more detail herein, the PCFC 110 lets a small amount of relay current flow through relay 16 but less than the energizing current needed to energize relay 16 to disengage manual reset switches 12, 12A. It is appreciated that not starting from zero energizing current lets relay 16 energize faster when a fault is detected.

[0027] Referring now to FIG. 1A and FIG. 2. When switches 12, 12A are mechanically (manually) engaged AC line voltage is connect to LOAD. 60 Hz AC line voltage is also connected to power supply circuit 110A via manually engaged relay 16. Power supply circuit 110A, comprising bridge rectifier (diodes D1-D4) outputs a rectified unsmoothed DC signal at BRIDGEOUT. The rectified unsmoothed DC signal at BRIDGEOUT is routed through Q1 base via shields 24A, 24B and resistors R1 and R3. The rectified unsmoothed DC signal at BRIDGEOUT is also routed through R2 and R2A to Q1 collector and SCR1 gate.

[0028] Still referring to FIG. 1A and FIG. 2, the rectified unsmoothed DC signal at BRIDGEOUT is routed to the base of npn transistor Q1, R1 and R3 biasing Q1 into an on condition during the positive cycle of the rectified unsmoothed DC, dropping the rectified voltage across R2 and R2A. When Q1(B) voltage drops below Q1's V.sub.BE saturation voltage Q1 turns off. The voltage at Q1(C) and SCR1 gate are near 0v due to the unsmoothed DC signal at BRIDGEOUT dropping to near 0v in the cycle. When the unsmoothed DC signal at BRIDGEOUT swings positive, Q1 is again biased on, dropping the unsmoothed DC signal at BRIDGEOUT across R2 and R2A, keeping SCR1 in an off condition during normal operation.

[0029] Still referring to FIG. 1A, it is understood that under normal conditions the rectified unsmoothed DC signal at BRIDGEOUT is dropped across resistor R2 and R2A and that R2 and R2A are sized to allow an amount of AC current less than the relay 16 energizing current to flow through R2 and R2A through Q1 back to neutral when Q1 is conducting. During Q1's off state, or non-conducting state, relay 16 inductively opposes the change in current until Q1 again turns on, thus maintaining, or nearly maintaining the current flow through relay 16. It is understood and appreciated that the small amount of relay current flowing through relay 16 is less than the energizing current needed to energize relay 16 to disengage manual reset switches 12,12A. It is further appreciated that not starting from zero energizing current lets relay 16 energize faster when a fault is detected.

[0030] Still referring to FIG. 1A and now FIG. 4, when either shield 24A or 24B integrity is compromised, e.g., open, , the bias-on voltage V.sub.BE at the base of Q1 is not enough to keep Q1 in its full conductive state. The voltage at the Q1 collector (V(SCRGATE)) rises on the first positive rectified input cycle to trigger SCR1 into an on condition, sufficiently increasing current flow through relay 16 to energize relay 16 to disengage manual reset switches 12,12A. Thus, interrupting power from the AC line source to the load. It is understood and appreciated that the full wave bridge rectifier 100A enables the PCFC 110A to detect and disconnect the AC line source from the load when a fault is detected during the positive or negative cycle of an input AC waveform (not shown).

[0031] Referring also to FIG. 5 there is shown a waveform diagram for the shield degraded condition of the Power Cord Circuit in FIGS. 1, 1A. It will be appreciated that R1, Shield 24A, Shield 24B, connector 24C and R3 form the base biasing circuit for Q1. As shield resistance goes up, e.g, due to galvanic corrosion due to dissimilar metals in the power cord shields, Q1 V.sub.BE will begin to fall below Q1's V.sub.BEsaturation voltage thus decreasing I.sub.CE. As I.sub.CE decreases C1 begins to charge. When the charge on C1 reaches SCR1 gate trigger voltage, the SCR triggers into an on condition, which increases current flow through relay 16 to energize relay 16 to disengage manual reset switches 12,12A. Thus, interrupting power from the AC line source to the load.

[0032] It will be appreciated that the present invention detects degraded shields and open shields. Further, it should be understood that the foregoing descriptions are only illustrative of the invention. Thus, various alternatives and changes can be devised by those skilled in the art without departing from the invention. For example, solid state devices SCR1 or Q1 can be any suitable solid-state device. For example, Q1 may be any suitable non-linear device or transistor configuration, such as a common base configuration. The present invention is intended to embrace all such alternatives, changes and variances that fall within the scope of the appended claims.