FIVE STAGE COMPLIMENTARY METAL-OXIDE SEMICONDUCTOR RECTIFIER WITH ENERGY HARVESTING ANTENNA

Abstract

A circuit and methods describing a complementary metal-oxide semiconductor (CMOS) rectifier for use in radio frequency (RF) energy harvesting with body biasing by the RF input to control the threshold voltage of each transistor. The CMOS rectifier includes an energy harvesting antenna, and multiple rectifier stages. The antenna receives electromagnetic radiation from the environment and generates a DC current. The oscillating input current is an RF.sup.+ positive current during a first half cycle and is an RF.sup.? negative current during a second half cycle. A first rectifier stage includes a first capacitor connected to the RF.sup.+ positive current, a second capacitor connected to the RF.sup.? negative current and a cross coupled CMOS circuit connected to the antenna.

Claims

1-7. (canceled)

8. A five-stage complementary metal-oxide semiconductor (CMOS) rectifier with energy harvesting antenna, comprising: a plurality of rectifier stages including an input rectifier stage, three intermediate rectifier stages and an output rectifier stage, wherein each rectifier stage of the plurality rectifier stages is connected to an energy harvesting antenna selected from the group consisting of a copper wire, a copper wire coil, a silver wire coil, a ferrite coil and a combination thereof and configured to receive an electromagnetic radiation and generate an oscillating current, wherein the oscillating current is an RF.sup.+ positive current during a first half cycle and is an RF.sup.? negative current during a second half cycle, wherein each rectifier stage includes an input and an output; an input of the input rectifier stage is connected to a ground and an output of the input rectifier stage is connected to an input stage output capacitor C.sub.s1, wherein input stage output capacitor C.sub.s1 has a first stage voltage output terminal and is connected to the ground, wherein the input rectifier stage is connected to the RF.sup.+ current by a first energy harvesting capacitor C.sub.1 and to the RF.sup.? current by a second energy harvesting capacitor C.sub.2; an input of a first intermediate rectifier stage is connected to the first stage voltage output terminal and an output of the first intermediate rectifier stage is connected to a first intermediate stage output capacitor C.sub.s2, wherein the first intermediate output capacitor C.sub.s2 has a first intermediate stage voltage output terminal and is connected to the first stage voltage output terminal, and wherein the first intermediate rectifier stage is connected to the RF.sup.+ current by a third energy harvesting capacitor C.sub.3 and to the RF.sup.? current by a fourth energy harvesting capacitor C.sub.4; an input of a second intermediate rectifier stage is connected to the first intermediate stage voltage output terminal and an output of the second intermediate rectifier stage is connected to a second intermediate stage output capacitor C.sub.s3, wherein the second intermediate stage output capacitor C.sub.s3 has a second intermediate stage voltage output terminal and is connected to first intermediate stage voltage output terminal, and wherein the second intermediate rectifier stage is connected to the RF.sup.+ current by a fifth energy harvesting capacitor C.sub.5 and to the RF.sup.? current by a sixth energy harvesting capacitor C.sub.6; an input of a third intermediate rectifier stage is connected to the second intermediate stage voltage output terminal and an output of the third intermediate rectifier stage is connected to a third intermediate stage output capacitor C.sub.s4, wherein the third intermediate stage output capacitor C.sub.s4 has a third intermediate stage voltage output terminal and is connected to the second intermediate stage voltage output terminal, and wherein the third intermediate rectifier stage is connected to the RF.sup.+ current by a seventh energy harvesting capacitor C.sub.7 and to the RF.sup.? current by an eighth energy harvesting capacitor C.sub.8; an input of the output rectifier stage is connected to the third intermediate stage voltage output terminal and an output of the output rectifier stage is connected to an output stage capacitor C.sub.sout, wherein the output stage capacitor C.sub.sout has an output stage voltage output terminal and is connected to the third intermediate stage voltage output terminal, and wherein the output rectifier stage is connected to the RF.sup.+ current by a ninth energy harvesting capacitor C.sub.9 and to the RF.sup.? current by an tenth energy harvesting capacitor C.sub.10; a third capacitor C.sub.3 connected between the RF.sup.? negative current and a body contact of the first NMOS transistor; a fourth capacitor C.sub.4 connected between the RF.sup.? negative current and a body contact of the first PMOS transistor; a fifth capacitor C.sub.5 connected between the RF.sup.+ positive current and a body contact of the second PMOS transistor; a sixth capacitor C.sub.6 connected between the RF.sup.+ positive current and a body contact of the second NMOS transistor; and wherein each rectifier stage includes a cross coupled CMOS circuit connected to the antenna, wherein the cross coupled CMOS circuit includes: a first P-channel metal oxide semiconductor (PMOS) transistor connected at its drain to an RF.sup.+ voltage, at its source to the output, at its gate to an RF-voltage, and at its body contact to a body biasing capacitor connected to the RF.sup.? current; a first N-channel metal oxide semiconductor (NMOS) transistor connected at its drain to an RF.sup.+ voltage, at its source to the input, at its gate to an RF.sup.? voltage, and at its body contact to a body biasing capacitor connected to the RF.sup.? current; a second PMOS transistor connected at its drain to the RF.sup.? voltage, at its source to the output, at its gate to an RF.sup.+ voltage and at its body contact to a body biasing capacitor connected to the RF.sup.+ current; and a second NMOS transistor connected at its drain to the RF.sup.? voltage, at its source to the input, at its gate to the RF.sup.+ voltage, and at its body contact to a body biasing capacitor connected to the RF.sup.+ current.

9. The five-stage CMOS rectifier of claim 8, wherein: the first PMOS transistor and the second NMOS transistor are configured to operate in an ON state during the first half cycle and in an OFF state during the second half cycle; and the second PMOS transistor and the first NMOS transistor are configured to operate in an OFF state during the first half cycle and in an ON state during the second half cycle.

10. The five-stage CMOS rectifier of claim 8, further comprising: a load connected in parallel with the first stage output capacitor C.sub.s1, the first intermediate output capacitor C.sub.s2, the second intermediate stage output capacitor C.sub.s3, the third intermediate stage output capacitor C.sub.s4 and output stage capacitor C.sub.sout, wherein the five-stage CMOS rectifier is configured to convert the oscillating current generated by the energy harvesting antenna to a DC voltage and provide the DC voltage to the load.

11. The five-stage CMOS rectifier of claim 8, wherein a threshold voltage of each first NMOS transistor is configured to increase during the first half cycle of the oscillating current and decrease during the second half cycle due to the charging and discharging charging respectively of the body biasing capacitor which biases the body contact of each first NMOS transistor.

12. The five-stage CMOS rectifier of claim 8, wherein a threshold voltage of each first PMOS transistor is configured to decrease during the first half cycle of the oscillating current and increase during the second half cycle due to the charging and discharging respectively of the body biasing capacitor which biases the body contact of the first PMOS transistor.

13. The five-stage CMOS rectifier of claim 8, wherein a threshold voltage of each second PMOS transistor is configured to increase during the first half cycle of the oscillating current and decrease during the second half cycle due to the charging and discharging respectively of the body biasing capacitor which biases the body contact of each second PMOS transistor.

14. The five-stage CMOS rectifier of claim 8, wherein a threshold voltage of each second NMOS transistor is configured to decrease during the first half cycle of the oscillating current and increase during the second half cycle due to the charging and discharging respectively of the body biasing capacitor which biases the body contact of each second NMOS transistor.

15-20. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] A more complete appreciation of this disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

[0019] FIG. 1 illustrates a block diagram of a cross-coupled rectifier;

[0020] FIG. 2 illustrates a block diagram of a complementary metal-oxide semiconductor (CMOS) rectifier, according to aspects of the present disclosure;

[0021] FIG. 3 illustrates a circuit diagram showing a configuration of a five-stage CMOS rectifier, according to aspects of the present disclosure;

[0022] FIG. 4 represents an exemplary block diagram of the five-stage CMOS rectifier, according to aspects of the present disclosure;

[0023] FIG. 5 is an exemplary graph illustrating variation in threshold voltage with body voltage, according to aspects of the present disclosure;

[0024] FIG. 6 is an exemplary graph illustrating voltage versus time across MP1 of the source voltage, the body voltage, and the difference between the source voltage and the body voltage at an input voltage=0.8 V, according to aspects of the present disclosure;

[0025] FIG. 7 is an exemplary graph illustrating power conversion efficiency (PCE) versus an input power at R.sub.L=10 k? at 953 MHz, according to aspects of the present disclosure;

[0026] FIG. 8 is an exemplary graph illustrating the PCE efficiency versus the input power at R.sub.L=100 k? at 953 MHz, according to aspects of the present disclosure;

[0027] FIG. 9 is an exemplary graph illustrating the DC output voltage versus the input power, according to aspects of the present disclosure;

[0028] FIG. 10 is an exemplary graph illustrating a DC output voltage waveform of the CMOS rectifier versus time, according to aspects of the present disclosure;

[0029] FIG. 11 is an exemplary graph illustrating a variation in DC output voltage versus the number of stages of the CMOS rectifier at R.sub.L=100 k?, according to aspects of the present disclosure;

[0030] FIG. 12 is an exemplary graph illustrating an effect of load variation on peak PCE of the CMOS rectifier, according to aspects of the present disclosure; and

[0031] FIG. 13 is an exemplary graph illustrating a post-layout simulation result of the CMOS rectifier at R.sub.L=10 k?, according to aspects of the present disclosure.

DETAILED DESCRIPTION

[0032] In the drawings, like reference numerals designate identical or corresponding parts throughout the several views. Further, as used herein, the words a, an and the like generally carry a meaning of one or more, unless stated otherwise.

[0033] Furthermore, the terms approximately, approximate, about, and similar terms generally refer to ranges that include the identified value within a margin of 20%, 10%, or preferably 5%, and any values therebetween.

[0034] Aspects of this disclosure are directed to a complementary metal-oxide semiconductor (CMOS) rectifier for use in radio frequency (RF) energy harvesting. The present CMOS rectifier includes a modified cross-coupled architecture. The CMOS rectifier employs an adaptive body biasing technique to lower the transistor threshold voltage (V.sub.th) when a P-channel metal-oxide-semiconductor (PMOS) is ON. The modified cross-coupled architecture is configured to increase the conduction current. The modified cross-coupled architecture increases V.sub.th when the PMOS is OFF, thereby minimizing the current flowing in a reverse bias condition. The CMOS rectifier was simulated using a TSMC 0.18 ?m CMOS technology (also known as CMOSP18) under various loading conditions at an input frequency of 953 MHz. The CMOS rectifier showed a peak power conversion efficiency (PCE) of 78.2% at an input power of ?27.5 dBm and a 100 k? load.

[0035] A radio frequency (RF) energy harvester harvests RF energy from the environment. The RF energy harvester employs a wireless power transfer technique in which the received RF signals are converted into electricity. The RF energy harvester is implemented in various applications including, wireless sensor networks, wearable electrical devices, wireless charging, and IoT devices. The RF energy harvester includes, inter alia an antenna, an impedance matching circuit, a plurality of voltage multipliers (rectifier circuits), and an energy storage unit. The RF energy harvester converts RF energy to DC energy, thus it is also referred to as a RF to DC converter.

[0036] In an operative aspect, the RF waves present in the environment are captured by an antenna. The antenna converts the captured RF waves (electromagnetic waves) into AC electrical signals. An impedance matching circuit ensures that maximum power is delivered from the antenna to a rectifier circuit (voltage multiplier circuit). The matching circuit is made of capacitor and inductor components. The rectifier circuit converts the AC electrical signals received from the antenna into DC power. After passing through the impedance matching circuit, the rectifier circuit (voltage multiplier circuit) rectifies and amplifies the signal as per the needs of the load. In an aspect, the rectifier circuit may be a voltage multiplier (a special rectifier) circuit which rectifies the signal and also boosts the rectified signal based on the application requirement. The converted DC electricity is stored in the energy storage unit. The energy storage unit uses a capacitor or battery to store the electricity and supplies the stored DC electricity to the load whenever needed.

[0037] The antenna is employed as a first stage of the RF energy harvester to capture RF waves. The antenna is coupled to the impedance matching network to match the impedance of the antenna to that of the rectifier circuit to achieve maximum power transfer. The rectifier circuit converts the incoming AC signal into DC signal, which is delivered to the energy storage unit to store the obtained DC energy. The rectifier circuit plays a crucial role in overall performance of the RF energy harvester. Therefore, an improvement in the rectifier circuit would lead to a better RF energy harvesting. In an aspect, a figure of merit in the RF rectifier circuit is the power conversion efficiency (PCE). The PCE is defined as a ratio of power absorbed by the load to the total input power, expressed as:

[00001]$\begin{array}{cc}PCE=\frac{\mathrm{out}\mathrm{power}}{.Math.\mathrm{input}\mathrm{power}.Math.}=\frac{V_{out}?I_{out}}{.Math.V_{AC}.Math.?I_{\mathrm{in}}}?100.& \left(1\right)\end{array}$

[0038] FIG. 1 illustrates a block diagram of a conventional cross-coupled rectifier 100. The conventional cross-coupled rectifier 100 includes a first P-channel metal oxide semiconductor (PMOS) transistor MP1, a first N-channel metal oxide semiconductor (NMOS) transistor MN1, a first N-channel metal oxide semiconductor (NMOS) transistor MN1, a second PMOS transistor MP2, and a second NMOS transistor MN2.

[0039] In an aspect of the present disclosure, the conventional cross-coupled rectifier 100 is coupled to an antenna. The antenna is configured to receive an electromagnetic radiation from the environment or a RF generating source. The antenna is configured to generate an oscillating current. The oscillating current is an RF.sup.+ positive current during a first half cycle and is an RF-negative current during a second half cycle.

[0040] In an operative aspect, during the positive half cycle (RF.sup.+ positive current), the transistors MP1 and the MN2 are conducting, and their corresponding threshold voltages (V.sub.th) are reduced by applying an input voltage differentially. At the same time, MP2 and MN1 are reversely biased to reduce their leakage current, and vice versa in the negative half cycle. The conventional cross-coupled rectifier 100 suffers from leakage of reverse current through the conducting PMOS (either MP1 or MP2) during the operating cycle, when V.sub.x<V.sub.out. A detailed analysis and modeling of the conventional cross-coupled rectifier 100 has been carried out and verified using simulation.

[0041] In an aspect, the models of the conventional cross-coupled rectifier 100 are derived under the assumption that all transistors have the same absolute value of V.sub.th. Moreover, it is considered that all transistors are designed such that they all have the same conduction current. The intermediate voltages V.sub.x and V.sub.y are given by:

[00002]$\begin{array}{cc}{V}_x=\frac{C1}{2\left(C1+C_{eq}\right)}{V}_p\cos \left(wt\right)+0.5V_{\mathrm{out}}.& \left(2\right)\end{array}$$\begin{array}{cc}{V}_y=-\frac{C2}{2\left(C2+C_{eq}\right)}{V}_p\cos \left(wt\right)+0.5V_{\mathrm{out}}.& \left(3\right)\end{array}$

where V.sub.p is the peak voltage of the differential RF input, V.sub.in, C.sub.1 and C.sub.2 are DC coupling capacitors, C.sub.eq is an equivalent capacitor seen by V.sub.x and V.sub.y, and V.sub.out is an output DC voltage. In an aspect, the conventional cross-coupled rectifier 100 works in two regimes depending on the difference between V.sub.x and V.sub.y, which is the gate to source voltage across each transistor. When V.sub.x?V.sub.y<V.sub.th and V.sub.x>V.sub.out, MP1 transistor operates in weak inversion in which the conduction current is given by:

[00003]$\begin{array}{cc}{I}_{D,sub}=I_{so}{e}^{\frac{V_{GS}-V_{\mathrm{th}}-V_{\mathrm{off}}}{{\mathrm{nV}}_t}}\left(1-e^{-\frac{V_{DS}}{V_t}}\right),& \left(4\right)\end{array}$$\mathrm{where}$$\begin{array}{cc}{I}_{s0}={?}_0\frac{W}{L}\sqrt{\frac{q{?}_{si}{N}_{ch}}{2{?}_s}}{V}_t^2,& \left(5\right)\end{array}$

with V.sub.off as an offset voltage and n as a swing parameter, both of which are for sub-threshold operation. V.sub.t is the thermal voltage, ?.sub.0 is the electron mobility, q is electron charge, ?.sub.si is the silicon primitivity, N.sub.ch is the doping concertation in the channel, and ?.sub.s is the surface potential. When V.sub.out>V.sub.x, a reverse current given by (4) flows from a storage element to source.

[0042] On the other hand, when V.sub.x?V.sub.y>V.sub.th and V.sub.x>V.sub.out, MP1 transistor is in the inversion state, in which the conduction current is given as:

[00004]$\begin{array}{cc}{I}_{D,\mathrm{tri}}={?}_0{C}_{ox}\frac{W}{L}\left(\left(V_{GS}-V_{\mathrm{th}}\right)V_{DS}-0.5V_{DS}^2\right).& \left(6\right)\end{array}$

[0043] This inversion continues until V.sub.out becomes greater than V.sub.x, in which case a reverse current given by (6) will flow. When V.sub.x drops even further, MP1 enters into a saturation region and the reverse current takes the following form:

[00005]$\begin{array}{cc}{I}_{D,\mathrm{sat}}=\frac{1}{2}{?}_0{C}_{ox}\frac{W}{L}{\left(V_{GS}-V_{\mathrm{th}}\right)}^2.& \left(7\right)\end{array}$

[0044] FIG. 2 illustrates a block diagram of a complementary metal-oxide semiconductor (CMOS) rectifier for use in radio frequency (RF) energy harvesting (hereinafter referred to as CMOS rectifier 200), according to an aspect of the present disclosure.

[0045] Referring to FIG. 2, the CMOS rectifier 200 includes various components such as an energy harvesting antenna 202 and a first rectifier stage 204. In an aspect, the CMOS 200 is configured to include a plurality of rectifier stages as per application and requirement. In an aspect, the CMOS rectifier 200 is configured to receive electromagnetic radiation from the environment or from an RF source. For example, the RF source includes radio signals, cellular signals, global system for mobile (GSM) signals, or digital or analog television signals. In some examples, the CMOS rectifier 200 harvests RF power from a single RF source, such as an RFID interrogator, at a single frequency. In an example, the CMOS rectifier 200 harvests RF power from multiple RF sources at multiple frequencies.

[0046] The energy harvesting antenna 202 is configured to receive an electromagnetic radiation from the environment or the RF source and generate an oscillating current. In an aspect, the electromagnetic radiation acts as a differential input signal V.sub.in. The oscillating current is an RF.sup.+ positive current during a first half cycle. The oscillating current is an RF.sup.? negative current during a second half cycle. In an aspect, the energy harvesting antenna 202 is coupled to a receiver. For example, the receiver may include an antenna wire, a tuning coil of copper wire, a rectifier, and other components. In an aspect, the energy harvesting antenna 202 may include various types of antennas and various electrical components, such as capacitors, resistors, inductors, and diodes. In some examples, the energy harvesting antenna 202 may be a conventional crystal radio antenna. In an aspect, the energy harvesting antenna 202 includes a copper wire coil, a silver wire coil, or a ferrite coil. In an example, the energy harvesting antenna 202 may be a Yagi, log-periodic, fiberglass, cable, repeater, or other type of antennas, including those used in the existing knowledge. The energy harvesting antenna 202 may be manufactured from a printed circuit board, aluminum, copper, silver, other metals, or other materials. The energy harvesting antenna 202 may omni-directional antenna that collects the available electromagnetic (radio) signals. The shape, size, circumference, and composition of the energy harvesting antenna 202 may be altered for a specific application and/or to enhance the gain associated with the antenna.

[0047] In an aspect of the present disclosure, the CMOS rectifier 200 includes an impedance matching circuit. The impedance matching circuit is configured to be tuned to capture certain frequencies from the RF source. In order to achieve maximal power output, an impedance of the energy harvesting antenna 202 needs to be matched with an output impedance of the first rectifier stage 204. The impedance matching circuit include capacitive and inductive circuitry configured to provide maximum power transfer from the RF energy source. The rectifier component may be used to convert alternating current generated from the RF signal to direct current.

[0048] As shown in FIG. 2, in a circuitry aspect, the first rectifier stage 204 includes a first energy harvesting capacitor C.sub.1, a second energy harvesting capacitor C.sub.2, and a cross coupled CMOS circuit 206. The first rectifier stage 204 includes the energy harvesting antenna 202 and receives a differential RF input from the energy harvesting antenna 202. The first energy harvesting capacitor C.sub.1 is connected to the energy harvesting antenna 202 and receives the RF.sup.+ positive current during the first half cycle. The second energy harvesting capacitor C.sub.2 is connected to the energy harvesting antenna 202 and receives the RF.sup.? negative current during the second half cycle. The cross coupled CMOS circuit 206 is also connected to the energy harvesting antenna 202 and receives the RF.sup.+ positive current and the RF.sup.? negative current from the energy harvesting antenna 202.

[0049] As shown in FIG. 2, the cross coupled CMOS circuit 206 includes a first output capacitor C.sub.s1, a first P-channel metal oxide semiconductor (PMOS) transistor MP1, a first N-channel metal oxide semiconductor (NMOS) transistor MN1, a second PMOS transistor MP2, a second NMOS MN2, a first body biasing capacitor C.sub.b1, a second body biasing capacitor C.sub.b2, a third body biasing capacitor C.sub.b3, and a fourth body biasing capacitor C.sub.b4.

[0050] The first output capacitor C.sub.s1 has a first stage voltage output terminal. A second terminal of C.sub.s1 is connected to the ground. The first PMOS transistor MP1 is connected to the first energy harvesting capacitor C.sub.1 at a drain terminal. The first PMOS transistor MP1 is connected to the first stage voltage output terminal at a source terminal. The first PMOS transistor MP1 is connected to the second energy harvesting capacitor C.sub.2 at a gate terminal.

[0051] The first NMOS transistor MN1 is connected to the first harvesting capacitor C.sub.1 at a drain terminal. The first NMOS transistor MN1 is connected to a ground terminal at a source terminal. The first NMOS transistor MN1 is connected to the second energy harvesting capacitor C.sub.2 at a gate terminal.

[0052] The second PMOS transistor MP2 is connected to the second energy harvesting capacitor C.sub.2 at a drain terminal. The second PMOS transistor MP2 is connected to the first stage voltage output terminal at a source terminal. The second PMOS transistor MP2 is connected to the first energy harvesting capacitor C.sub.1 at a gate terminal.

[0053] The second NMOS transistor MN2 is connected to the second harvesting capacitor C.sub.2 at a drain terminal. The second NMOS transistor MN2 is connected to the ground at a source terminal. The second NMOS transistor MN2 is connected to the first harvesting capacitor C.sub.1 at a gate terminal.

[0054] In an operating aspect, the first PMOS transistor MP1 and the second NMOS transistor MN2 are configured to operate in an ON state during the first half cycle and in an OFF state during the second half cycle. In an operating aspect, the second PMOS transistor MP2 and the first NMOS transistor MN1 are configured to operate in an OFF state during the first half cycle and in an ON state during the second half cycle.

[0055] The first body biasing capacitor C.sub.b1 is connected between the RF.sup.? negative current and a body contact of the first NMOS transistor MN1. The second body biasing capacitor C.sub.b2 is connected between the RF.sup.? negative current and a body contact of the first PMOS transistor MP1. The third body biasing capacitor C.sub.b3 is connected between the RF.sup.+ positive current and a body contact of the second NMOS transistor MN2. The fourth body biasing capacitor C.sub.b4 connected between the RF.sup.+ positive current and a body contact of the second PMOS transistor MP2.

[0056] In an aspect, the CMOS rectifier 200 includes a load (R.sub.L) that is connected in parallel with the first output capacitor C.sub.s1. The cross coupled CMOS circuit 206 is configured to convert the oscillating current generated by the energy harvesting antenna to a DC voltage at the first output capacitor C.sub.s1 and provide the DC voltage to the load (R.sub.L).

[0057] In an aspect, a threshold voltage of the first NMOS transistor MN1 is configured to increase during the first half cycle of the oscillating current and decrease during the second half cycle due to the charging and discharging respectively, of the body biasing first capacitor C.sub.b1 which biases the body contact of the first NMOS transistor MN1.

[0058] In an aspect, a threshold voltage of the first PMOS transistor MP1 is configured to decrease during the first half cycle of the oscillating current and increase during the second half cycle due to the charging and discharging respectively, of the body biasing second capacitor C.sub.b2 which biases the body contact of the first PMOS transistor MP1.

[0059] In an aspect, a threshold voltage of the second NMOS transistor MN2 is configured to decrease during the first half cycle of the oscillating current and increase during the second half cycle due to the charging and discharging respectively, of the body biasing third capacitor C.sub.b3, which biases the body contact of the second NMOS transistor MN2.

[0060] In an aspect, a threshold voltage of the second PMOS transistor MP2 is configured to increase during the first half cycle of the oscillating current and decrease during the second half cycle due to the charging and discharging respectively, of the body biasing fourth capacitor C.sub.b4 which biases the body contact of the second PMOS transistor MP2.

[0061] The present disclosure presents a CMOS RF-DC converter based on the threshold voltage self-compensation. To improve the PCE of the CMOS rectifier 200, the following relation between V.sub.th and the body voltage (V.sub.b) of the transistor can be used:

[00006]$\begin{array}{cc}{V}_{\mathrm{th}}=V_{\mathrm{th}0}+?\left(\sqrt{.Math.2{?}_F+V_{sb}.Math.}-\sqrt{.Math.2{?}_F.Math.}\right),& \left(8\right)\end{array}$

where V.sub.th0, ?.sub.F, and y are process dependent parameters, and V.sub.sb denotes a potential difference between the source terminal and body terminal of a MOSFET. From equation (8), it can be seen that variation in V.sub.b results in either an increase or a decrease in V.sub.th, depending on whether a PMOS or an NMOS is used. This characteristic of the MOSFET device can be utilized to obtain an improved rectifier for RF energy harvesting applications. In order to vary the body voltage of the NMOS, the NMOS is required to be fabricated in a deep n-well structure.

[0062] The present disclosure is configured to improve a cross-coupled design of the rectifier by employing an adaptive body biasing. When V.sub.x is positive, corresponding to the ON state of MP1, and V.sub.bp is negative, then a differential voltage between the source terminal and body terminal of MP1, V.sub.sb=V.sub.x-V.sub.bp, is positive and relatively high. The positive and high differential voltage results in a lower V.sub.th for MP1 as suggested by equation (8), since for a PMOS V.sub.th0,?>?.sub.F<0. The common mode voltage is cancelled since V.sub.sb is a differential mode signal.

[0063] On the other hand, when V.sub.x is negative, which represents an OFF state of MP1, V.sub.bp is positive, resulting in a high negative value for V.sub.sb. This high negative value of V.sub.sb results in a higher V.sub.th, which reduces the current flowing in the reverse bias condition.

[0064] For the second NMOS transistor MN2, when V.sub.x is negative, and V.sub.bp is positive, the differential voltage between the source terminal and body terminal of MN2, V.sub.sb?V.sub.x?V.sub.bp, is generated. The generated differential voltage results in a lower V.sub.th for MN2. On the other hand, when V.sub.x is positive, which represents an OFF state of MN2, V.sub.bp is positive, resulting in a high negative value for V.sub.sb. This high negative value of V.sub.sb results in a higher V.sub.th, which reduces the current flowing in the reverse bias condition.

[0065] In an operating aspect, for MP2, when V.sub.x is negative, corresponding to the ON state of MP2, and V.sub.bp is negative, a differential voltage between the source terminal and body terminal of MP2, V.sub.sb=V.sub.x?V.sub.bp, is generated. The differential voltage is positive and relatively high resulting in a lower V.sub.th for MP2 as suggested by equation (8).

[0066] On the other hand, when V.sub.x is negative, which represents an OFF state of MP2, V.sub.bp is positive, resulting in a high negative value for V.sub.sb. This high negative value of V.sub.sb results in a higher V.sub.th, which reduces the current flowing in the reverse bias condition.

[0067] On the other hand, for the first NMOS transistor MN1, when V.sub.x is negative, and V.sub.bp is positive, then the differential voltage between the source terminal and body terminal of MN2, V.sub.sb?V.sub.x?V.sub.bp, generated. The generated differential voltage results in a lower V.sub.th for MN2. On the other hand, when V.sub.x is positive, which represents an OFF state of MN1, V.sub.bp is positive, resulting in a high negative value for V.sub.sb. This high negative value of V.sub.sb results in a higher V.sub.th, which reduces the current flowing in the reverse bias condition.

[0068] To analyze mathematically, equation (8) can be rewritten as:

[00007]$\begin{array}{cc}{V}_{\mathrm{th},b}=V_{\mathrm{th}0}+?\left(\sqrt{.Math.2{?}_F+V_s-V_b.Math.}-\sqrt{.Math.2{?}_F.Math.}\right),& \left(9\right)\end{array}$

where V.sub.s is the source voltage and V.sub.b is the body voltage of the transistor. Thus, in the modified analysis, each V.sub.th should be replaced by V.sub.th,b. In the positive half cycle, when V.sub.RF.sub.+>0, V.sub.RF.sub.?<0, V.sub.x?V.sub.y<V.sub.th,b, and V.sub.x>V.sub.out, MP1 operates in the weak inversion, and as a consequence of body biasing, the new conduction current through MP1 is given by:

[00008]$\begin{array}{cc}{I}_{D,\mathrm{sub},b}=I_{so}{e}^{\frac{V_{GS}-V_{\mathrm{th},b}-V_{\mathrm{of}}}{\mathrm{nVt}}}\left(1-e^{-\frac{V_{DS}}{V_t}}\right),& \left(10\right)\end{array}$$\mathrm{where}$$\begin{array}{cc}{V}_{\mathrm{th},b}=V_{\mathrm{th}0}+?\left(\sqrt{.Math.2{?}_F+V_s-V_{bp}.Math.}-\sqrt{.Math.2{?}_F.Math.}\right).& \left(11\right)\end{array}$

[0069] As V.sub.bp<0, the term V.sub.s?V.sub.bp is higher than the case of the conventional cross-coupled structure when the voltage V.sub.b=V.sub.out. As a result, a lower V.sub.th is achieved.

[0070] From equation (10), it can be seen that V.sub.th reduction results in a higher conduction current.

[0071] In the other case, when V.sub.x?V.sub.y>V.sub.th,b, and V.sub.x>V.sub.out, MP1 operates in the strong inversion, with a new conduction current given as:

[00009]$\begin{array}{cc}{I}_{D,\mathrm{tri},b}={?}_0{C}_{ox}\frac{W}{L}\left(\left(V_{GS}-V_{\mathrm{th},b}\right)V_{DS}-0.5V_{DS}^2\right),& \left(12\right)\end{array}$

where V.sub.th,b still has the form of equation (11) but with V.sub.bp having a greater negative (absolute value) value, resulting in an even lower V.sub.th,b. When V.sub.out becomes greater than V.sub.x, a reverse current flows as a result of body biasing. The reverse current will be given by:

[00010]$\begin{array}{cc}{I}_{D,\mathrm{tri},b,r}={?}_0{C}_{ox}\frac{W}{L}\left(\left(V_{GS}-V_{\mathrm{th},b}\right)V_{DS}-0.5V_{DS}^2\right),& \left(13\right)\end{array}$

where V.sub.th,b will have the same form as equation (11).

[0072] As V.sub.x becomes lower, V.sub.bp changes and becomes less negative. Therefore, V.sub.th,b would be higher in the reverse mode. Subsequently, when V.sub.x drops even further, MP1 enters into a saturation region with a reverse current given by:

[00011]$\begin{array}{cc}{I}_{D,\mathrm{sat},b,r}=\frac{1}{2}{?}_0{C}_{ox}\frac{W}{L}{\left(V_{GS}-V_{\mathrm{th},b}\right)}^2& \left(14\right)\end{array}$

Nevertheless, V.sub.bp will continue to increase, resulting in higher V.sub.th,b. A similar operation takes place in the negative half cycle when V.sub.RF.sub.+<0, V.sub.RF.sub.?>0, and MP2 starts conducting.

[0073] When MP1 is conducting, the output voltage is given by:

[00012]$\begin{array}{cc}{V}_{\mathrm{out}}=V_x-V_{\mathrm{thp}1},& \left(15\right)\end{array}$

where V.sub.thp1 is the threshold voltage of MP1. Lowering the V.sub.thp1 results in increasing the output voltage as shown below:

[00013]$\begin{array}{cc}{V}_{\mathrm{out}}=V_x-\left(V_{\mathrm{th}0}+?\left(\sqrt{.Math.2{?}_F+V_x-V_{bp}.Math.}-\sqrt{.Math.2{?}_F.Math.}\right)\right).& \left(16\right)\end{array}$

[0074] FIG. 3 illustrates a circuit diagram showing a configuration of a five-stage CMOS rectifier 300 for use in radio frequency (RF) energy harvesting (hereinafter referred to as CMOS rectifier 300), according to one or more aspects of the present disclosure. The five-stage CMOS rectifier 300 is configured to convert the oscillating current generated by the energy harvesting antenna to the DC voltage and provide the DC voltage to the load.

[0075] Referring to FIG. 3, the CMOS rectifier 300 includes an energy harvesting antenna (V.sub.in) 301 and a plurality of rectifier stages (302, 304, 310). The plurality of rectifier stages (302, 304, 310) includes an input rectifier stage 302, three intermediate rectifier stages 304 and an output rectifier stage 310. Each rectifier stage of the plurality rectifier stages (302, 304, 310) is connected to the energy harvesting antenna 301. In an aspect, the electromagnetic radiation is fed in parallel to each of the stages. Each stage is configured to receive the oscillating current from the energy harvesting antenna 301 and generate the DC voltage. The DC voltage produced by each stage is summed in series to produce the output DC Voltage, which is supplied to the load.

[0076] As shown in FIG. 3, each rectifier stage (302, 304, 310) includes an input and an output. The input of the input rectifier stage 302 is connected to ground, and an output of the input rectifier stage 302 is connected to an input stage output capacitor C.sub.s1. The input stage output capacitor C.sub.s1 has a first stage voltage output terminal and is connected to the ground. The input rectifier stage 302 is connected to the RF.sup.+ current by a first energy harvesting capacitor C.sub.1, and to the RF.sup.? current by a second energy harvesting capacitor C.sub.2.

[0077] In a connecting aspect, an input of a first intermediate rectifier stage 304 is connected to the first stage voltage output terminal. An output of the first intermediate rectifier stage is connected to a first intermediate stage output capacitor C.sub.s2. The first intermediate output capacitor C.sub.s2 has a first intermediate stage voltage output terminal and is connected to the first stage voltage output terminal. The first intermediate rectifier stage 304 is connected to the RF.sup.+ current by a third energy harvesting capacitor C.sub.3, and to the RF.sup.? current by a fourth energy harvesting capacitor C.sub.4.

[0078] Referring to both FIG. 3 and FIG. 4, in a connecting aspect, an input of a second intermediate rectifier stage is connected to the first intermediate stage voltage output terminal. An output of the second intermediate rectifier stage is connected to a second intermediate stage output capacitor C.sub.s3. The second intermediate stage output capacitor C.sub.s3 has a second intermediate stage voltage output terminal and is connected to the first intermediate stage voltage output terminal. The second intermediate rectifier stage is connected to the RF.sup.+ current by a fifth energy harvesting capacitor C.sub.5 and to the RF.sup.? current by a sixth energy harvesting capacitor C.sub.6.

[0079] In a connecting aspect, an input of a third intermediate rectifier stage is connected to the second intermediate stage voltage output terminal. An output of the third intermediate rectifier stage is connected to a third intermediate stage output capacitor C.sub.s4. The third intermediate stage output capacitor C.sub.s4 has a third intermediate stage voltage output terminal and is connected to the second intermediate stage voltage output terminal. The third intermediate rectifier stage is connected to the RF.sup.+ current by a seventh energy harvesting capacitor C.sub.7 and to the RF.sup.? current by an eighth energy harvesting capacitor C.sub.8.

[0080] In a connecting aspect, an input of the output rectifier stage 310 is connected to the third intermediate stage voltage output terminal. An output of the output rectifier stage 310 is connected to an output stage capacitor C.sub.sout. The output stage capacitor C.sub.sout has an output stage voltage output terminal and is connected to the third intermediate stage voltage output terminal. The output rectifier stage 310 is connected to the RF.sup.+ current by a ninth energy harvesting capacitor C.sub.9 and to the RF.sup.? current by a tenth energy harvesting capacitor C.sub.10. The output rectifier stage 310 includes a load connected in parallel with the capacitor C.sub.sout.

[0081] Each rectifier stage includes a cross coupled CMOS circuit that is connected to the energy harvesting antenna 301. For example, the input rectifier stage 302 has a first cross coupled CMOS circuit. The first cross coupled CMOS circuit includes a first P-channel metal oxide semiconductor (PMOS) transistor MP1, a first N-channel metal oxide semiconductor (NMOS) transistor MN1, a second PMOS transistor MP2, and a second NMOS transistor MN2.

[0082] The first PMOS transistor MP1 is connected to an RF.sup.+ voltage at a drain terminal. The first PMOS transistor MP1 is connected to the output, at a source terminal. The first PMOS transistor MP1 is connected to an RF.sup.? voltage at a gate terminal. The first PMOS transistor MP1 is connected to a body biasing capacitor connected to the RF.sup.? current at body contact. In an aspect, a fourth capacitor C.sub.4 is connected between the RF.sup.? negative current and a body contact of the first PMOS transistor MP1.

[0083] The first NMOS transistor MN1 is connected to an RF.sup.+ voltage at a drain terminal. The first NMOS transistor MN1 is connected to the input at a source terminal. The first NMOS transistor MN1 is connected to an RF.sup.? voltage at a gate terminal. The first NMOS transistor MN1 is connected to a body biasing capacitor connected to the RF.sup.? current at body contact. In an aspect, a third capacitor C.sub.3 is connected between the RF.sup.? negative current and a body contact of the first NMOS transistor MN1.

[0084] The second PMOS transistor MP2 is connected to the RF.sup.? voltage at a drain terminal. The second PMOS transistor MP2 is connected to the output at a source terminal The second PMOS transistor MP2 is connected to an RF.sup.+ voltage at a gate terminal. The second PMOS transistor MP2 is connected to a body biasing capacitor connected to the RF.sup.+ current at body contact. In an aspect, a fifth capacitor C.sub.5 is connected between the RF.sup.+ positive current and a body contact of the second PMOS transistor MP2.

[0085] The second NMOS transistor MN2 is connected to the RF.sup.? voltage at a drain terminal. The second NMOS transistor MN2 is connected to the input at a source terminal. The second NMOS transistor MN2 is connected to the RF.sup.+ voltage at a gate terminal. The second NMOS transistor MN2 is connected to a body biasing capacitor connected to the RF.sup.+ current at a body contact. In an aspect, a sixth capacitor C.sub.6 is connected between the RF.sup.+ positive current and a body contact of the second NMOS transistor MN2.

[0086] The first PMOS transistor MP1 and the second NMOS transistor MN2 are configured to operate in an ON state during the first half cycle and in an OFF state during the second half cycle. The second PMOS transistor MP2 and the first NMOS transistor MN1 are configured to operate in an OFF state during the first half cycle and in an ON state during the second half cycle.

[0087] In an aspect, the first intermediate rectifier stage 304 includes a second cross coupled CMOS circuit. An input of a second cross coupled CMOS circuit is connected to a third linking capacitor C.sub.13 and a fourth linking capacitor C.sub.14. The second cross coupled CMOS circuit includes a second output capacitor C.sub.s2, a first PMOS transistor MP3, a first NMOS transistor MN3, a second PMOS transistor MP4, a seventh capacitor C.sub.7, an eight capacitor C.sub.8, a fifth capacitor C.sub.5, and a sixth capacitor C.sub.6.

[0088] The second output capacitor C.sub.s2 includes a second stage voltage output terminal which is connected to the ground. The first PMOS transistor MP3 is connected to the first capacitor C.sub.1 at a drain terminal. The first PMOS transistor MP3 is connected to the second stage voltage output terminal at a source terminal. The first PMOS transistor MP3 is connected to the second capacitor C.sub.2 at a gate terminal.

[0089] The first NMOS transistor MN3 is connected to the first capacitor C.sub.1 at a drain terminal. The first NMOS transistor MN3 is connected to the input at a source terminal. The first NMOS transistor MN3 is connected to the second capacitor C.sub.2 at a gate terminal.

[0090] The second PMOS transistor MP4 is connected to the second capacitor C.sub.2 at a drain terminal. The second PMOS transistor MP4 is connected to the second stage voltage output terminal at a source terminal. The second PMOS transistor MP4 is connected to the first capacitor C.sub.1 at a gate terminal.

[0091] The second NMOS transistor MN4 is connected to the second capacitor C.sub.2 at a drain terminal. The second NMOS transistor MN4 is connected to the input at a source terminal. The second NMOS transistor MN4 is connected to the first capacitor C.sub.1 at a gate terminal.

[0092] The seventh capacitor C.sub.7 is connected between the RF.sup.? negative current and a body contact of the first NMOS transistor MN3. The eight capacitor C.sub.8 is connected between the RF negative current and a body contact of the first PMOS transistor MP3. The fifth capacitor C.sub.5 is connected between the RF.sup.+ positive current and a body contact of the second PMOS transistor MP2. The sixth capacitor C.sub.6 is connected between the RF.sup.+ positive current and a body contact of the second NMOS transistor MN2.

[0093] In an aspect, each stage of the five-stage CMOS rectifier 300 is connected to a load (R.sub.L) connected in parallel with the output capacitor C.sub.sout and a load capacitor C.sub.L. For example, the first stage includes the load connected in parallel with the output capacitor C.sub.s1. The first intermediate includes the load connected in parallel with the output capacitor C.sub.s2. The second intermediate stage includes the load connected in parallel with the output capacitor C.sub.s3. The third intermediate stage includes the load connected in parallel with the output capacitor C.sub.s4.

[0094] In an aspect, a threshold voltage of each first NMOS transistor MN1 is configured to increase during the first half cycle of the oscillating current and decrease during the second half cycle due to the charging and discharging charging, respectively, of the body biasing capacitor which biases the body contact of each first NMOS transistor MN1.

[0095] In an aspect, a threshold voltage of each first PMOS transistor MP1 is configured to decrease during the first half cycle of the oscillating current and increase during the second half cycle due to the charging and discharging, respectively, of the body biasing capacitor which biases the body contact of the first PMOS transistor MP1.

[0096] In an aspect, a threshold voltage of each second PMOS transistor MP2 is configured to increase during the first half cycle of the oscillating current and decrease during the second half cycle due to the charging and discharging, respectively, of the body biasing capacitor which biases the body contact of each second PMOS transistor MP1.

[0097] In an aspect, a threshold voltage of each second NMOS transistor MN2 is configured to decrease during the first half cycle of the oscillating current and increase during the second half cycle due to the charging and discharging, respectively, of the body biasing capacitor which biases the body contact of each second NMOS transistor MN1.

[0098] FIG. 4 represents an exemplary block diagram of the five-stage CMOS rectifier 400 (hereinafter referred to as CMOS rectifier 400), according to one or more aspects of the present disclosure. The construction of CMOS rectifiers 300 and 400 are substantially similar as described in FIG. 3 and FIG. 4, and thus the construction is not repeated here in detail for the sake of brevity.

[0099] Referring to FIG. 4, the CMOS rectifier 400 includes an energy harvesting antenna (not shown) and a plurality of rectifier stages (402, 404, 406, 408, 410). The plurality of rectifier stages (402, 404, 406, 408, 410) includes an input rectifier stage 402, three intermediate rectifier stages (404, 406, 408), and an output rectifier stage 410. Each rectifier stage of the plurality rectifier stages (402, 404, 406, 408, 410) is connected to the energy harvesting antenna. Each stage (402, 404, 406, 408, 410) is configured to receive the oscillating current from the energy harvesting antenna and generate a DC voltage.

[0100] As shown in FIG. 4, each rectifier stage (402, 404, 406, 408, 410) includes an input and an output. An input of the input rectifier stage 402 is connected to the ground, and an output of the input rectifier stage 402 is connected to an input stage output capacitor C.sub.s1. An input of a first intermediate rectifier stage 404 is connected to the first stage voltage output terminal, and an output of the first intermediate rectifier stage 404 is connected to an input stage output capacitor C.sub.s2. An input of the second intermediate rectifier stage 406 is connected to the first intermediate stage voltage output terminal, and an output of the second intermediate rectifier stage 406 is connected to an input stage output capacitor C.sub.s3. An input of the third intermediate rectifier stage 408 is connected to the second intermediate stage voltage output terminal, and an output of the third intermediate rectifier stage 408 is connected to an input stage output capacitor C.sub.s4. An input of the output rectifier stage is connected to the third intermediate stage voltage output terminal, and an output of the output rectifier stage is connected to an output stage capacitor C.sub.sout. In an aspect, the voltage output terminal of the input rectifier stage 402 may be connected to the input of the second intermediate rectifier stage 406 via the f.sub.b1. Similarly, the voltage output terminal of the first rectifier intermediate stage 404 may be connected to the input of the third intermediate rectifier stage 406 via the f.sub.b2. In an aspect, the voltage output terminal of the second rectifier intermediate stage 406 may be connected to the input of the output rectifier stage 410 via the f.sub.b3. Similarly, the voltage output terminal of the third rectifier intermediate stage 404 may be connected to the output stage capacitor C.sub.sout via the f.sub.b4.

[0101] The following examples are provided to illustrate further and to facilitate the understanding of the present disclosure.

[0102] In an aspect, the functionality of the present CMOS rectifier 200 was verified using Tanner T-spice in a 0.18 ?m Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology. In an example, each of MP1 and MP2 has a width/length (W/L) equal to 18 ?m/0.18 ?m. In another example, MN1 and MN2 have the W/L equal to 10 ?m/0.18 ?m. The value of the threshold voltage used in the simulation was 516.84 mV for NMOS, and ?511.69 mV for PMOS. The smoothing capacitor (C.sub.sout) had a value of 300 pF, and all other capacitors had a value of 1.13 pF. For the purpose of comparison, the CMOS rectifier 200 was simulated with the values and parameters as used in conventional rectifiers.

[0103] FIG. 5 is an exemplary graph 500 showing the variation in threshold voltage V.sub.th with body voltage V.sub.b. Curve 502 represents the variation in the threshold voltage with body voltage of the PMOS having W/L=18 u/0.18 u. Curve 504 represents the variation in the threshold voltage with the body voltage of the NMOS having W/L=10 u/0.18 u. From FIG. 5, it can be seen that variation in V.sub.b resulted in either an increase or a decrease in V.sub.th depending on whether the PMOS or the NMOS is used.

[0104] FIG. 6 is an exemplary graph 600 showing various waveforms across MP1 having a source voltage (V.sub.x), a body voltage (V.sub.bp), and a voltage difference (V.sub.sb) at input voltage=0.8 V, according to aspects of the present disclosure. Curve 602 represents the variation in the source voltage (V.sub.x). Curve 604 represents the variation in the body voltage (V.sub.bp). Curve 606 represents the voltage difference (V.sub.sb) between the source voltage (V.sub.x) and the body voltage (V.sub.bp). As shown in FIG. 6, when V.sub.x is positive, MP1 is in an ON state. When V.sub.bp is negative, then the differential voltage between the source and body terminals of MP1, V.sub.sb?V.sub.x?V.sub.bp, will be positive and relatively high. This results in a lower V.sub.th for MP1 as suggested by equation (8), since for the PMOS V.sub.th0,?,?.sub.F<0.

[0105] FIG. 7 is an exemplary graph 700 showing the relationship of a power conversion efficiency (PCE) versus input power (P.sub.in) at R.sub.L=10 k? at 953 MHz. Curve 702 represents the PCE of the present CMOS rectifier 200. Curve 704 represents the PCE of the conventional cross coupled rectifier 100.

[0106] FIG. 8 is an exemplary graph 800 showing a relationship of the PCE versus the input power (P.sub.in) at R.sub.L=100 k? at 953 MHz. Curve 802 represents PCE of the CMOS rectifier 200. Curve 804 represents PCE of the conventional cross coupled rectifier 100.

[0107] FIG. 7 and FIG. 8 demonstrate the performance of the CMOS rectifier 200 for different loads at 953 MHz. It can be seen from FIG. 7 and FIG. 8 that the CMOS rectifier 200 outperforms the conventional cross-coupled structure at low input levels. Inspection of FIG. 7 and FIG. 8 show that the CMOS rectifier 200 reaches to its peak first, and then the CMOS rectifier 200 follows a downward trend in efficiency.

[0108] The CMOS rectifier 200 achieves high PCE at low input power levels. Therefore, it can be used with one or more other designs that are more efficient at higher input power levels but perform poorly at low input power levels. Complementing each other results in a design that achieves high PCE at both low and high input power levels.

[0109] FIG. 9 is an exemplary graph 900 showing variation in DC output voltage versus the input power, according to aspects of the present disclosure. Curve 902 represents variation in DC output voltage of the CMOS rectifier 200. As shown in FIG. 9, the output DC voltage as a function of the input power (P.sub.in) for R.sub.L=10 k?. To meet the high voltage requirement of microcontrollers, a multistage configuration is required. To examine whether the cross coupled CMOS circuit is capable of producing a high DC output voltage, a five-stage rectifier 300 using the cross coupled CMOS circuit shown in FIG. 2, was simulated under the conditions of 0.8V peak input voltage, a frequency of 953 MHz and 100 k? load.

[0110] FIG. 10 is an exemplary graph 1000 showing the DC output voltage waveform. The DC output voltage for five stages is shown in FIG. 10. It can be seen that the output of the CMOS rectifier 300 achieved a better steady state value of 3.2V. Curve 1002 represents variation in DC output voltage of the CMOS rectifier 200. Curve 1004 represents DC output voltage of the conventional cross coupled rectifier 100.

[0111] FIG. 11 is an exemplary graph 1100 illustrating a variation in DC output voltage versus the number of stages at R.sub.L=100 k?, according to aspects of the present disclosure. Curve 1102 represents variation in DC output voltage of the CMOS rectifier 300. The DC output voltage as a function of the number of stages is shown in FIG. 11. It can be seen that beyond the five stages, the improvement ceased to be significant.

[0112] FIG. 12 is an exemplary graph 1200 illustrating an effect of load variation on peak PCE, according to aspects of the present disclosure. Curve 1202 represents PCE of the CMOS rectifier 200 corresponding to the load variation. To see the effects of the load variation on the efficiency, the simulation was carried out for different loads. The simulation result shown in FIG. 12 indicates that the efficiency is highest in the vicinity of a 100 k? load.

[0113] FIG. 13 is an exemplary graph 1300 illustrating post-layout simulation result at R.sub.L=10 k?, according to aspects of the present disclosure. Curve 1302 represents pre-layout simulation of the CMOS rectifier 200. Curve 1304 represents post-layout simulation of the CMOS rectifier 200. The post layout simulation for the circuit shown in FIG. 2 is carried out for R.sub.L=10 k?. The simulation results shown in FIG. 13 confirm the agreement between circuit diagram and post-layout simulation with small deviation.

[0114] A figure of merit (FoM) is used to provide a comprehensive evaluation of the rectifier's performance. The FOM is given as:

[00014]$\begin{array}{cc}\mathrm{FoM}=\frac{PCE?VCR}{N}{\log }_{10}\left(\frac{f}{f_0}\right)& \left(17\right)\end{array}$

where VCR is ratio of the DC output voltage to the peak RF differential input voltage, N is the number of stages, f is the frequency of operation, and f.sub.0 is a normalization factor. In an aspect, f.sub.0 M 5 MHz.

[0115] The performance of the CMOS rectifier 200 was compared with the recent designs and a summary of the comparison is shown in Table. 1.

TABLE-US-00001 TABLE 1 Comparison with relevant designs References Present CMOS Khan Kotani, Li, Khan, Basim, rectifier 200 et al. et al. et al. et al. et al. Technology 0.18 ?m 0.18 ?m 0.18 ?m 0.18 ?m 0.18 ?m 0.18 ?m 0.18 ?m frequency 953 MHz 953 MHz 13.56 MHz 953 MHz 915 MHz 900 MHz 902 MHz Load 100 k? 10 k? 2 k? 10 k? 5 k? 100 k? 1 M? P.sub.in ?27.5 dBm ?16.1 dBm 11.98 dBm ?12.5 dBm ?3.7 dBm ?19.6 dBm 12 dBm Peak PCE 78.2% 73.8% 87% 67.5% 72.3% 66% 40% FoM 1.51 1.23 0.33 1.08 Expr./Sim. Sim. Sim. Sim. Expr./ Sim. Expr./ Sim. V.sub.th Body Body Bootstrapping Differential Body Differential Auxiliary compensation Biasing Biasing Capacitors Drive Biasing Drive Transistors technique Sensitivity ?7.1 dBm ?5 dBm ?12.9 dBm ?18.2 dBm ?20 dBm Area (mm.sup.2) 0.0004 0.0768 0.0084 0.019

[0116] It is evident that the CMOS rectifier 200 achieves a higher efficiency than the conventional designs.

[0117] The present disclosure describes an enhanced CMOS rectifier design for RF energy harvesting. The rectifier design inserts an adaptive body biasing circuit in the conventional cross-coupled structure. This adaptive body biasing varies V.sub.th of the four transistors to increase the conduction current and reduce the current flowing in the reverse bias condition, resulting in a high peak PCE. The performance of the circuit was evaluated at different loading conditions. Simulation results showed that the CMOS rectifier 200 exhibited a peak efficiency of 78.2% at input power of ?27.5 dBm, a load of 100 k?, and a 953 MHz frequency.

[0118] The first embodiment is illustrated with respect to FIGS. 1-13. The first embodiment describes a complementary metal-oxide semiconductor (CMOS) rectifier 200 for use in radio frequency (RF) energy harvesting. The CMOS rectifier 200 includes an energy harvesting antenna 202, and a first rectifier stage 204. The energy harvesting antenna 202 is configured to receive an electromagnetic radiation and generate an oscillating current, wherein the oscillating current is an RF.sup.+ positive current during a first half cycle and is an RF.sup.? negative current during a second half cycle. The first rectifier stage 204 includes a first energy harvesting capacitor C.sub.1 connected to the RF.sup.+ positive current, a second energy harvesting capacitor C.sub.2 connected to the RF.sup.? negative current, and a cross coupled CMOS circuit 206 connected to the antenna 202. The cross coupled CMOS circuit 206 includes a first output capacitor C.sub.s1 having a first stage voltage output terminal, wherein a second terminal of C.sub.s1 is connected to a ground; a first P-channel metal oxide semiconductor (PMOS) transistor MP1 connected at its drain to the first energy harvesting capacitor C.sub.1, at its source to the first stage voltage output terminal and at its gate to the second energy harvesting capacitor C.sub.2; a first N-channel metal oxide semiconductor (NMOS) transistor MN1 connected at its drain to the first harvesting capacitor C.sub.1, at its source to a ground terminal and at its gate to the second energy harvesting capacitor C.sub.2; a second PMOS transistor MP2 connected at its drain to the second energy harvesting capacitor C.sub.2, at its source to the first stage voltage output terminal and at its gate to the first energy harvesting capacitor C.sub.1; a second NMOS MN2 connected at its drain to the second harvesting capacitor C.sub.2, at its source to the ground and at its gate to the first harvesting capacitor C.sub.1; a first body biasing capacitor C.sub.b1 connected between the RF.sup.? negative current and a body contact of the first NMOS transistor MN1; a second body biasing capacitor C.sub.b2 connected between the RF.sup.? negative current and a body contact of the first PMOS transistor MP1; a third body biasing capacitor C.sub.b3 connected between the RF.sup.+ positive current and a body contact of the second NMOS transistor MN2; and a fourth body biasing capacitor C.sub.b4 connected between the RF.sup.+ positive current and a body contact of the second PMOS transistor MP2.

[0119] In an aspect, the first PMOS transistor MP1 and the second NMOS transistor MN2 are configured to operate in an ON state during the first half cycle and in an OFF state during the second half cycle; and the second PMOS transistor MP2 and the first NMOS transistor MN1 are configured to operate in an OFF state during the first half cycle and in an ON state during the second half cycle.

[0120] In an aspect, the CMOS rectifier 200 includes a load connected in parallel with the first output capacitor C.sub.s1, wherein the cross coupled CMOS circuit 206 is configured to convert the oscillating current generated by the energy harvesting antenna 202 to a DC voltage at the first output capacitor C.sub.s1 and provide the DC voltage to the load.

[0121] In an aspect, a threshold voltage of the first NMOS transistor MN1 is configured to increase during the first half cycle of the oscillating current and decrease during the second half cycle due to the charging and discharging respectively of the body biasing first capacitor C.sub.b1 which biases the body contact of the first NMOS transistor MN1.

[0122] In an aspect, a threshold voltage of the first PMOS transistor MP1 is configured to decrease during the first half cycle of the oscillating current and increase during the second half cycle due to the charging and discharging respectively of the body biasing second capacitor C.sub.b2 which biases the body contact of the first PMOS transistor MP1.

[0123] In an aspect, a threshold voltage of the second NMOS transistor MN2 is configured to decrease during the first half cycle of the oscillating current and increase during the second half cycle due to the charging and discharging respectively of the body biasing third capacitor C.sub.b3 which biases the body contact of the second NMOS transistor MN2.

[0124] In an aspect, a threshold voltage of the second PMOS transistor MP2 is configured to increase during the first half cycle of the oscillating current and decrease during the second half cycle due to the charging and discharging respectively of the body biasing fourth capacitor C.sub.b4 which biases the body contact of the second PMOS transistor MP2.

[0125] The second embodiment is illustrated with respect to FIGS. 1-13. The second embodiment describes a five-stage complementary metal-oxide semiconductor (CMOS) rectifier 300 for use in radio frequency (RF) energy harvesting. The CMOS rectifier 300 includes a plurality of rectifier stages including an input rectifier stage 302, three intermediate rectifier stages and an output rectifier stage 310, wherein each rectifier stage of the plurality rectifier stages is connected to an energy harvesting antenna 301 configured to receive an electromagnetic radiation and generate an oscillating current, wherein the oscillating current is an RF.sup.+ positive current during a first half cycle and is an RF.sup.? negative current during a second half cycle, wherein each rectifier stage includes an input and an output; an input of the input rectifier stage is connected to a ground and an output of the input rectifier stage is connected to an input stage output capacitor C.sub.s1, wherein input stage output capacitor C.sub.s1 has a first stage voltage output terminal and is connected to the ground, wherein the input rectifier stage is connected to the RF.sup.+ current by a first energy harvesting capacitor C.sub.1 and to the RF.sup.? current by a second energy harvesting capacitor C.sub.2; an input of a first intermediate rectifier stage is connected to the first stage voltage output terminal and an output of the first intermediate rectifier stage is connected to a first intermediate stage output capacitor C.sub.s2, wherein the first intermediate output capacitor C.sub.s2 has a first intermediate stage voltage output terminal and is connected to the first stage voltage output terminal, and wherein the first intermediate rectifier stage is connected to the RF.sup.+ current by a third energy harvesting capacitor C.sub.3 and to the RF.sup.? current by a fourth energy harvesting capacitor C.sub.4; an input of a second intermediate rectifier stage is connected to the first intermediate stage voltage output terminal and an output of the second intermediate rectifier stage is connected to a second intermediate stage output capacitor C.sub.s3, wherein the second intermediate stage output capacitor C.sub.s3 has a second intermediate stage voltage output terminal and is connected to first intermediate stage voltage output terminal, and wherein the second intermediate rectifier stage is connected to the RF.sup.+ current by a fifth energy harvesting capacitor C.sub.5 and to the RF.sup.? current by a sixth energy harvesting capacitor C.sub.6; an input of a third intermediate rectifier stage is connected to the second intermediate stage voltage output terminal and an output of the third intermediate rectifier stage is connected to a third intermediate stage output capacitor C.sub.s4, wherein the third intermediate stage output capacitor C.sub.s4 has a third intermediate stage voltage output terminal and is connected to the second intermediate stage voltage output terminal, and wherein the third intermediate rectifier stage is connected to the RF.sup.+ current by a seventh energy harvesting capacitor C.sub.7 and to the RF.sup.? current by an eighth energy harvesting capacitor C.sub.8; an input of the output rectifier stage is connected to the third intermediate stage voltage output terminal and an output of the output rectifier stage is connected to an output stage capacitor C.sub.sout, wherein the output stage capacitor C.sub.sout has an output stage voltage output terminal and is connected to the third intermediate stage voltage output terminal, and wherein the output rectifier stage is connected to the RF.sup.+ current by a ninth energy harvesting capacitor C.sub.9 and to the RF.sup.? current by an tenth energy harvesting capacitor C.sub.10; a third capacitor C.sub.3 connected between the RF.sup.? negative current and a body contact of the first NMOS transistor; a fourth capacitor C.sub.4 connected between the RF.sup.? negative current and a body contact of the first PMOS transistor; a fifth capacitor C.sub.5 connected between the RF.sup.+ positive current and a body contact of the second PMOS transistor; a sixth capacitor C.sub.6 connected between the RF.sup.+ positive current and a body contact of the second NMOS transistor; and wherein each rectifier stage includes a cross coupled CMOS circuit connected to the antenna, wherein the cross coupled CMOS circuit includes: a first P-channel metal oxide semiconductor (PMOS) transistor connected at its drain to an RF.sup.+ voltage, at its source to the output, at its gate to an RF-voltage, and at its body contact to a body biasing capacitor connected to the RF.sup.? current; a first N-channel metal oxide semiconductor (NMOS) transistor connected at its drain to an RF.sup.+ voltage, at its source to the input, at its gate to an RF.sup.? voltage, and at its body contact to a body biasing capacitor connected to the RF.sup.? current; a second PMOS transistor connected at its drain to the RF.sup.? voltage, at its source to the output, at its gate to an RF.sup.+ voltage and at its body contact to a body biasing capacitor connected to the RF.sup.+ current; and a second NMOS transistor connected at its drain to the RF.sup.? voltage, at its source to the input, at its gate to the RF.sup.+ voltage, and at its body contact to a body biasing capacitor connected to the RF.sup.+ current.

[0126] In an aspect, the first PMOS transistor and the second NMOS transistor are configured to operate in an ON state during the first half cycle and in an OFF state during the second half cycle; and the second PMOS transistor and the first NMOS transistor are configured to operate in an OFF state during the first half cycle and in an ON state during the second half cycle.

[0127] In an aspect, the five-stage CMOS rectifier 300 includes a load connected in parallel with the first stage output capacitor C.sub.s1, the first intermediate output capacitor C.sub.s2, the second intermediate stage output capacitor C.sub.s3, the third intermediate stage output capacitor C.sub.s4 and output stage capacitor C.sub.sout, wherein the five-stage CMOS rectifier 300 is configured to convert the oscillating current generated by the energy harvesting antenna 301 to a DC voltage and provide the DC voltage to the load.

[0128] In an aspect, a threshold voltage of each first NMOS transistor is configured to increase during the first half cycle of the oscillating current and decrease during the second half cycle due to the charging and discharging charging respectively of the body biasing capacitor which biases the body contact of each first NMOS transistor.

[0129] In an aspect, a threshold voltage of each first PMOS transistor is configured to decrease during the first half cycle of the oscillating current and increase during the second half cycle due to the charging and discharging respectively of the body biasing capacitor which biases the body contact of the first PMOS transistor.

[0130] In an aspect, a threshold voltage of each second PMOS transistor is configured to increase during the first half cycle of the oscillating current and decrease during the second half cycle due to the charging and discharging respectively of the body biasing capacitor which biases the body contact of each second PMOS transistor.

[0131] In an aspect, a threshold voltage of each second NMOS transistor is configured to decrease during the first half cycle of the oscillating current and increase during the second half cycle due to the charging and discharging respectively of the body biasing capacitor which biases the body contact of each second NMOS transistor.

[0132] The third embodiment is illustrated with respect to FIGS. 1-13. The third embodiment describes a method for harvesting radio frequency (RF) energy. The method includes receiving, by an energy harvesting antenna 202, an electromagnetic radiation. The method includes generating, by the energy harvesting antenna 202, an oscillating current, wherein the oscillating current is an RF.sup.+ positive current during a first half cycle and is an RF.sup.? negative current during a second half cycle. The method includes connecting a first energy harvesting capacitor C.sub.1 to the RF.sup.+ positive current. The method further includes connecting a second energy harvesting capacitor C.sub.2 to the RF.sup.? negative current. The method further includes connecting a cross coupled CMOS circuit 206 to the first energy harvesting capacitor C.sub.1 and the second energy harvesting capacitor C.sub.2, wherein connecting the cross coupled CMOS circuit includes: connecting the first stage voltage output terminal to a first output capacitor C.sub.s1 having and connecting a second terminal of C.sub.s1 to a ground; connecting a first P-channel metal oxide semiconductor (PMOS) transistor MP1 at its drain to the first energy harvesting capacitor C.sub.1, at its source to the first stage voltage output terminal and at its gate to the second energy harvesting capacitor C.sub.2; connecting a first N-channel metal oxide semiconductor (NMOS) transistor MN1 at its drain to the first energy harvesting capacitor C.sub.1, at its source to a ground terminal and at its gate to the second energy harvesting capacitor C.sub.2; connecting a second PMOS transistor MP2 at its drain to the second energy harvesting capacitor C.sub.2, at its source to the first stage voltage output terminal and at its gate to the first energy harvesting capacitor C.sub.1; connecting a second NMOS transistor MN2 connected at its drain to the second energy harvesting capacitor C.sub.2, at its source to the ground and at its gate to the first energy harvesting capacitor C.sub.1; connecting a first body biasing capacitor C.sub.b1 between the RF.sup.? negative current and a body contact of the first NMOS transistor MN1; connecting a second body biasing capacitor C.sub.b2 between the RF.sup.? negative current and a body contact of the first PMOS transistor MP1; connecting a third body biasing capacitor C.sub.b3 between the RF.sup.+ positive current and a body contact of the second NMOS transistor MN2; and connecting a fourth body biasing capacitor C.sub.b4 between the RF.sup.+ positive current and a body contact of the second PMOS transistor MP2.

[0133] In an aspect, the method further includes configuring the first PMOS transistor MP1 and the second NMOS transistor MN2 for operating in an ON state during the first half cycle and for operating in an OFF state during the second half cycle.

[0134] In an aspect, the method further includes configuring the second PMOS transistor MP2 and the first NMOS transistor MN1 for operating in an OFF state during the first half cycle and operating in an ON state during the second half cycle.

[0135] In an aspect, the method further includes connecting a load in parallel with the first output capacitor C.sub.s1, wherein the cross coupled CMOS circuit is configured for converting the oscillating current generated by the energy harvesting antenna to a DC voltage at the first output capacitor and providing the DC voltage to the load.

[0136] In an aspect, the method further includes configuring a threshold voltage of the first NMOS transistor MN1 for increasing during the first half cycle of the oscillating current and for decreasing during the second half cycle due to the charging and discharging respectively of the body biasing first capacitor C.sub.b1 which biases the body contact of the first NMOS transistor MN1; and configuring a threshold voltage of the first PMOS transistor MP1 for decreasing during the first half cycle of the oscillating current and for increasing during the second half cycle due to the charging and discharging respectively of the body biasing second capacitor C.sub.b2 which biases the body contact of the first PMOS transistor MP1.

[0137] In an aspect, the method further includes configuring a threshold voltage of the second PMOS transistor MP2 for increasing during the first half cycle of the oscillating current and for decreasing during the second half cycle due to the charging and discharging respectively body biasing third capacitor C.sub.b3 which biases the body contact of the second PMOS transistor MP2; and configuring a threshold voltage of the second NMOS transistor MN2 for decreasing during the first half cycle of the oscillating current and for increasing during the second half cycle due to the charging and discharging respectively of the body biasing fourth capacitor C.sub.b4 which biases the body contact of the second NMOS transistor MN2.

[0138] In an aspect, the method further includes connecting an input of a second cross coupled CMOS circuit to a third linking capacitor C.sub.13 and a fourth linking capacitor C.sub.14, wherein the second cross coupled CMOS circuit includes: a second output capacitor C.sub.s2 having a second stage voltage output terminal, wherein a second terminal of C.sub.s2 is connected to the ground; a first PMOS transistor MP3 connected at its drain to the first capacitor C.sub.1, at its source to the second stage voltage output terminal and at its gate to the second capacitor C.sub.2; a first NMOS transistor MN3 connected at its drain to the first capacitor C.sub.1, at its source to the input and at its gate to the second capacitor C.sub.2; a second PMOS transistor MP4 connected at its drain to the second capacitor C.sub.2, at its source to the second stage voltage output terminal and at its gate to the first capacitor C.sub.1; a second NMOS transistor MN4 connected at its drain to the second capacitor C.sub.2, at its source to the input and at its gate to the first capacitor C.sub.1; a seventh capacitor C.sub.7 connected between the RF.sup.? negative current and a body contact of the first NMOS transistor MN3; an eight capacitor C.sub.8 connected between the RF.sup.? negative current and a body contact of the first PMOS transistor MP3; a fifth capacitor C.sub.5 connected between the RF.sup.+ positive current and a body contact of the second PMOS transistor MP2; and a sixth capacitor C.sub.6 connected between the RF.sup.+ positive current and a body contact of the second NMOS transistor MN2.

[0139] The above-described hardware description is a non-limiting example of corresponding structure for performing the functionality described herein.

[0140] Numerous modifications and variations of the present disclosure are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the disclosure may be practiced otherwise than as specifically described herein.